^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ov2735 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X05 add function g_mbus_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* 45Mhz * 4 Binning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OV2735_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PAGE_SELECT_REG 0xfd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PAGE_ZERO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PAGE_ONE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PAGE_TWO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PAGE_OTP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) //PAGE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OV2735_PIDH_ADDR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OV2735_PIDL_ADDR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OV2735_PIDH_MAGIC 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV2735_PIDL_MAGIC 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) //PAGE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STREAM_CTRL_REG 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define STREAM_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STREAM_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define UPDOWN_MIRROR_REG 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define H_V_NORMAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define H_MIRROR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define V_FLIP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MIRROR_AND_FLIP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OV2735_VTS_HIGH_REG 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OV2735_VTS_LOW_REG 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OV2735_COARSE_INTG_TIME_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OV2735_COARSE_INTG_TIME_MAX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OV2735_VTS_ENABLE_REG 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OV2735_VTS_ENABLE_VALUE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OV2735_FRAME_SYNC_REG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OV2735_FRAME_SYNC_VALUE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OV2735_REG_TEST_PATTERN 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OV2735_HTS_HIGH_REG 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OV2735_HTS_LOW_REG 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OV2735_TEST_PATTERN_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OV2735_TEST_PATTERN_DISABLE 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OV2735_FINE_INTG_TIME_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OV2735_FINE_INTG_TIME_MAX_MARGIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OV2735_COARSE_INTG_TIME_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OV2735_COARSE_INTG_TIME_MAX_MARGIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OV2735_AEC_PK_LONG_EXPO_2ND_REG 0x03 /* Exposure Bits 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OV2735_AEC_PK_LONG_EXPO_1ST_REG 0x04 /* Exposure Bits 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OV2735_FETCH_2ND_BYTE_EXP(VAL) ((VAL >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OV2735_FETCH_1ST_BYTE_EXP(VAL) (VAL & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OV2735_AEC_PK_GAIN_REG 0x24 /* GAIN Bits 0 -7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OV2735_FETCH_LSB_GAIN(VAL) (VAL & 0x00FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OV2735_FETCH_MSB_GAIN(VAL) ((VAL >> 8) & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OV2735_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OV2735_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OV2735_VTS_MAX 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ANALOG_GAIN_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ANALOG_GAIN_MAX 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ANALOG_GAIN_DEFAULT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OV2735_NAME "ov2735"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OV2735_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const char * const ov2735_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OV2735_NUM_SUPPLIES ARRAY_SIZE(ov2735_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct ov2735_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct ov2735 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct regulator_bulk_data supplies[OV2735_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const struct ov2735_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define to_ov2735(sd) container_of(sd, struct ov2735, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct regval ov2735_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0xfd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x20, 0x01}, // soft reset modify to 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x0, 0x3}, // delay 3ms // delay 3ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Base sensor configs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * ov2735_init_tab_1920_1080_30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * MCLK:24MHz 1920x1080 30fps mipi 2lane 420Mbps/lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct regval ov2735_1920_1080_30fps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0xfd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x2f, 0x10}, // clk and pll setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x34, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x30, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x33, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x35, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x0d, 0x00}, // disable modify VTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x30, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x03, 0x01}, // exposure time, MSB default 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x04, 0x8f}, // exposure time, LSB default 0x8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x01, 0x01}, // enable of frame sync signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x09, 0x00}, // HBLANK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x0a, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x06, 0x0a}, // VBLANK 8LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x24, 0x10}, // gain default 0x10, by yjz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0xfb, 0x73}, // ABL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x1a, 0x6b}, // Timing ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x1c, 0xea},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x16, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x21, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x11, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x19, 0xc3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x26, 0x5a}, // ANALOG CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x29, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x33, 0x6f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x2a, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x2c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0xd0, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0xd1, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0xd2, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0xd3, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0xd4, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x50, 0x00}, // Timing ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x51, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x52, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x53, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x55, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x58, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x5a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x5b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x5d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x64, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x66, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x68, 0x5b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x75, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x76, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x77, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x78, 0xef},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x72, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x73, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x7d, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x7e, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x8a, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x8b, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0xb1, 0x83}, // MIPI register ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0xb3, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0xb4, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x9d, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0xa1, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x94, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x95, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x96, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x98, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x9c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0xb5, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x25, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x20, 0x7b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x8f, 0x88}, // H_SIZE_MIPI_8LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x91, 0x40}, // V_SIZE_MIPI_8LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0xfd, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0xa1, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0xa3, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0xa5, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0xa7, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x86, 0x77}, // BLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x89, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x87, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x88, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0xfc, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0xfe, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0xf0, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0xf1, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0xf2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0xf3, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) //1920x1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0xfd, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0xa0, 0x00}, // Image vertical start MSB3bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0xa1, 0x08}, // Image vertical start LSB8bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0xa2, 0x04}, // image vertical size MSB8bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0xa3, 0x38}, // image vertical size LSB8bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0xa4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0xa5, 0x08}, // H start 8Lsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0xa6, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0xa7, 0xc0}, // Half H size Lsb8bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x8e, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x8f, 0x80}, // MIPI column number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x90, 0x04}, // MIPI row number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x91, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) //TV1080_30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x0d, 0x10}, // enable manual modify the VTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x0e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x0f, 0xc1}, // Vblank, VTS:0x4c1, 30.037fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x01, 0x01}, // enable of frame sync signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define HTS_DEF 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define VTS_DEF 0x4c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define MAX_FPS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct ov2735_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .exp_def = 0x18f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .hts_def = HTS_DEF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .vts_def = VTS_DEF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .reg_list = ov2735_1920_1080_30fps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define OV2735_LINK_FREQ_420MHZ 420000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define OV2735_PIXEL_RATE (MAX_FPS * HTS_DEF * VTS_DEF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) OV2735_LINK_FREQ_420MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const char * const ov2735_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "Vertical Color",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int ov2735_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "ov2735 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int ov2735_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) while (regs[i].addr != REG_NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = ov2735_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_err(&client->dev, "%s failed !\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* sensor register read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int ov2735_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "ov2735 read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int ov2735_get_reso_dist(const struct ov2735_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct ov2735_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ov2735_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dist = ov2735_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int ov2735_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct ov2735 *ov2735 = to_ov2735(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) const struct ov2735_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mutex_lock(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) mode = ov2735_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mutex_unlock(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ov2735->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) __v4l2_ctrl_modify_range(ov2735->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) __v4l2_ctrl_modify_range(ov2735->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) OV2735_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) mutex_unlock(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int ov2735_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct ov2735 *ov2735 = to_ov2735(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) const struct ov2735_mode *mode = ov2735->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mutex_lock(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) mutex_unlock(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) mutex_unlock(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int ov2735_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int ov2735_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int ov2735_enable_test_pattern(struct ov2735 *ov2735, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ret = ov2735_read_reg(ov2735->client, OV2735_REG_TEST_PATTERN, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) switch (pattern) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) val &= ~OV2735_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) val |= OV2735_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return ov2735_write_reg(ov2735->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) OV2735_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static void ov2735_get_module_inf(struct ov2735 *ov2735,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) strlcpy(inf->base.sensor, OV2735_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) strlcpy(inf->base.module, ov2735->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) strlcpy(inf->base.lens, ov2735->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static long ov2735_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct ov2735 *ov2735 = to_ov2735(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ov2735_get_module_inf(ov2735, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ret = ov2735_write_reg(ov2735->client, PAGE_SELECT_REG, PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret |= ov2735_write_reg(ov2735->client, STREAM_CTRL_REG, STREAM_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = ov2735_write_reg(ov2735->client, PAGE_SELECT_REG, PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret |= ov2735_write_reg(ov2735->client, STREAM_CTRL_REG, STREAM_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static long ov2735_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = ov2735_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret = ov2735_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret = ov2735_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int __ov2735_start_stream(struct ov2735 *ov2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = ov2735_write_array(ov2735->client, ov2735->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = ov2735_write_reg(ov2735->client, PAGE_SELECT_REG, PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) mutex_unlock(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = v4l2_ctrl_handler_setup(&ov2735->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) mutex_lock(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret |= ov2735_write_reg(ov2735->client, STREAM_CTRL_REG, STREAM_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int __ov2735_stop_stream(struct ov2735 *ov2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ret = ov2735_write_reg(ov2735->client, PAGE_SELECT_REG, PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret |= ov2735_write_reg(ov2735->client, STREAM_CTRL_REG, STREAM_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int ov2735_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct ov2735 *ov2735 = to_ov2735(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct i2c_client *client = ov2735->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mutex_lock(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (on == ov2735->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret = __ov2735_start_stream(ov2735);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) __ov2735_stop_stream(ov2735);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ov2735->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) mutex_unlock(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static int ov2735_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct ov2735 *ov2735 = to_ov2735(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct i2c_client *client = ov2735->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) mutex_lock(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (ov2735->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ret = ov2735_write_array(ov2735->client, ov2735_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ov2735->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ov2735->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) mutex_unlock(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static inline u32 ov2735_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return DIV_ROUND_UP(cycles, OV2735_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int __ov2735_power_on(struct ov2735 *ov2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct device *dev = &ov2735->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (!IS_ERR(ov2735->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) gpiod_set_value_cansleep(ov2735->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ret = regulator_bulk_enable(OV2735_NUM_SUPPLIES, ov2735->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) usleep_range(20000, 50000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (!IS_ERR(ov2735->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) gpiod_set_value_cansleep(ov2735->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (!IS_ERR(ov2735->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) gpiod_set_value_cansleep(ov2735->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = clk_set_rate(ov2735->xvclk, OV2735_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (clk_get_rate(ov2735->xvclk) != OV2735_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ret = clk_prepare_enable(ov2735->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_info(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) delay_us = ov2735_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) clk_disable_unprepare(ov2735->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static void __ov2735_power_off(struct ov2735 *ov2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (!IS_ERR(ov2735->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) gpiod_set_value_cansleep(ov2735->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) clk_disable_unprepare(ov2735->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!IS_ERR(ov2735->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) gpiod_set_value_cansleep(ov2735->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) regulator_bulk_disable(OV2735_NUM_SUPPLIES, ov2735->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static int ov2735_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct ov2735 *ov2735 = to_ov2735(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return __ov2735_power_on(ov2735);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int ov2735_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct ov2735 *ov2735 = to_ov2735(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) __ov2735_power_off(ov2735);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int ov2735_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct ov2735 *ov2735 = to_ov2735(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) const struct ov2735_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) mutex_lock(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) mutex_unlock(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static int ov2735_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static int ov2735_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) val = 1 << (OV2735_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) config->type = V4L2_MBUS_CSI2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const struct dev_pm_ops ov2735_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) SET_RUNTIME_PM_OPS(ov2735_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ov2735_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const struct v4l2_subdev_internal_ops ov2735_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .open = ov2735_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static const struct v4l2_subdev_core_ops ov2735_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .s_power = ov2735_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .ioctl = ov2735_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .compat_ioctl32 = ov2735_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static const struct v4l2_subdev_video_ops ov2735_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .s_stream = ov2735_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .g_mbus_config = ov2735_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static const struct v4l2_subdev_pad_ops ov2735_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .enum_mbus_code = ov2735_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .enum_frame_size = ov2735_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .enum_frame_interval = ov2735_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .get_fmt = ov2735_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .set_fmt = ov2735_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static const struct v4l2_subdev_ops ov2735_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .core = &ov2735_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .video = &ov2735_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .pad = &ov2735_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static int ov2735_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct ov2735 *ov2735 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct ov2735, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct i2c_client *client = ov2735->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) max = ov2735->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) __v4l2_ctrl_modify_range(ov2735->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ov2735->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ov2735->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ov2735->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ret = ov2735_write_reg(client, PAGE_SELECT_REG, PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret |= ov2735_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) OV2735_AEC_PK_LONG_EXPO_2ND_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) OV2735_FETCH_2ND_BYTE_EXP(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ret |= ov2735_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) OV2735_AEC_PK_LONG_EXPO_1ST_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) OV2735_FETCH_1ST_BYTE_EXP(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ret |= ov2735_write_reg(client, OV2735_AEC_PK_GAIN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ret |= ov2735_write_reg(client, OV2735_VTS_ENABLE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) OV2735_VTS_ENABLE_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret |= ov2735_write_reg(client, OV2735_VTS_LOW_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) (ctrl->val + ov2735->cur_mode->height) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ret |= ov2735_write_reg(client, OV2735_VTS_HIGH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ((ctrl->val + ov2735->cur_mode->height) >> 8) & 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ret = ov2735_enable_test_pattern(ov2735, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ret |= ov2735_write_reg(client, OV2735_FRAME_SYNC_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) OV2735_FRAME_SYNC_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static const struct v4l2_ctrl_ops ov2735_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .s_ctrl = ov2735_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static int ov2735_initialize_controls(struct ov2735 *ov2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) const struct ov2735_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) handler = &ov2735->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) mode = ov2735->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ret = v4l2_ctrl_handler_init(handler, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) handler->lock = &ov2735->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) 0, OV2735_PIXEL_RATE, 1, OV2735_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ov2735->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (ov2735->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ov2735->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ov2735->vblank = v4l2_ctrl_new_std(handler, &ov2735_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) OV2735_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ov2735->exposure = v4l2_ctrl_new_std(handler, &ov2735_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) V4L2_CID_EXPOSURE, OV2735_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) exposure_max, OV2735_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ov2735->anal_gain = v4l2_ctrl_new_std(handler, &ov2735_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ov2735->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) &ov2735_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ARRAY_SIZE(ov2735_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) 0, 0, ov2735_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) dev_err(&ov2735->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ov2735->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static int ov2735_check_sensor_id(struct ov2735 *ov2735,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct device *dev = &ov2735->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) u8 pidh = 0x55, pidl = 0xaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret = ov2735_write_reg(ov2735->client, PAGE_SELECT_REG, PAGE_ZERO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ret |= ov2735_read_reg(ov2735->client, OV2735_PIDH_ADDR, &pidh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ret |= ov2735_read_reg(ov2735->client, OV2735_PIDL_ADDR, &pidl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) "register read failed, camera module powered off?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if ((pidh == OV2735_PIDH_MAGIC) && (pidl == OV2735_PIDL_MAGIC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) "Found cameraID 0x%02x%02x\n", pidh, pidl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) "wrong camera ID, expected 0x%02x%02x, detected 0x%02x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) OV2735_PIDH_MAGIC, OV2735_PIDL_MAGIC, pidh, pidl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dev_err(dev, "failed with error (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static int ov2735_configure_regulators(struct ov2735 *ov2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) for (i = 0; i < OV2735_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ov2735->supplies[i].supply = ov2735_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return devm_regulator_bulk_get(&ov2735->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) OV2735_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ov2735->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static int ov2735_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct ov2735 *ov2735;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ov2735 = devm_kzalloc(dev, sizeof(*ov2735), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (!ov2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) &ov2735->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) &ov2735->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) &ov2735->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) &ov2735->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ov2735->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ov2735->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ov2735->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (IS_ERR(ov2735->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ov2735->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (IS_ERR(ov2735->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ov2735->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (IS_ERR(ov2735->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ret = ov2735_configure_regulators(ov2735);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) mutex_init(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) sd = &ov2735->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) v4l2_i2c_subdev_init(sd, client, &ov2735_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret = ov2735_initialize_controls(ov2735);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ret = __ov2735_power_on(ov2735);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ret = ov2735_check_sensor_id(ov2735, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) sd->internal_ops = &ov2735_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ov2735->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ret = media_entity_pads_init(&sd->entity, 1, &ov2735->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (strcmp(ov2735->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) ov2735->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) OV2735_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) __ov2735_power_off(ov2735);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) v4l2_ctrl_handler_free(&ov2735->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) mutex_destroy(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static int ov2735_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct ov2735 *ov2735 = to_ov2735(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) v4l2_ctrl_handler_free(&ov2735->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) mutex_destroy(&ov2735->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) __ov2735_power_off(ov2735);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static const struct of_device_id ov2735_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) { .compatible = "ovti,ov2735" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) MODULE_DEVICE_TABLE(of, ov2735_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static const struct i2c_device_id ov2735_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) { "ovti,ov2735", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static struct i2c_driver ov2735_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .name = OV2735_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .pm = &ov2735_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .of_match_table = of_match_ptr(ov2735_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .probe = &ov2735_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .remove = &ov2735_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .id_table = ov2735_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return i2c_add_driver(&ov2735_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) i2c_del_driver(&ov2735_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) MODULE_DESCRIPTION("OmniVision ov2735 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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