Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * ov2685 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CHIP_ID				0x2685
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define OV2685_REG_CHIP_ID		0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define OV2685_XVCLK_FREQ		24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define REG_SC_CTRL_MODE		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define     SC_CTRL_MODE_STANDBY	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define     SC_CTRL_MODE_STREAMING	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define OV2685_REG_EXPOSURE		0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define	OV2685_EXPOSURE_MIN		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define	OV2685_EXPOSURE_STEP		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define OV2685_REG_VTS			0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define OV2685_VTS_MAX			0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define OV2685_REG_GAIN			0x350a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define OV2685_GAIN_MIN			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define OV2685_GAIN_MAX			0x07ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define OV2685_GAIN_STEP		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define OV2685_GAIN_DEFAULT		0x0036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define OV2685_REG_TEST_PATTERN		0x5080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define OV2685_TEST_PATTERN_DISABLED		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define OV2685_TEST_PATTERN_COLOR_BAR		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define OV2685_TEST_PATTERN_RANDOM		0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define OV2685_TEST_PATTERN_COLOR_BAR_FADE	0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define OV2685_TEST_PATTERN_BW_SQUARE		0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define OV2685_TEST_PATTERN_COLOR_SQUARE	0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define REG_NULL			0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define OV2685_REG_VALUE_08BIT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define OV2685_REG_VALUE_16BIT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define OV2685_REG_VALUE_24BIT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define OV2685_LANES			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define OV2685_BITS_PER_SAMPLE		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static const char * const ov2685_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	"avdd",		/* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	"dovdd",	/* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	"dvdd",		/* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define OV2685_NUM_SUPPLIES ARRAY_SIZE(ov2685_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) struct ov2685_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) struct ov2685 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct i2c_client	*client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct clk		*xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct gpio_desc	*reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct regulator_bulk_data supplies[OV2685_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	bool			streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct mutex		mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct v4l2_subdev	subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct media_pad	pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct v4l2_ctrl	*anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct v4l2_ctrl	*exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct v4l2_ctrl	*hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct v4l2_ctrl	*vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct v4l2_ctrl	*test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	const struct ov2685_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define to_ov2685(sd) container_of(sd, struct ov2685, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* PLL settings bases on 24M xvclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct regval ov2685_1600x1200_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	{0x3016, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	{0x3018, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	{0x301d, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{0x3020, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	{0x3082, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	{0x3083, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	{0x3084, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	{0x3085, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	{0x3086, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{0x3087, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	{0x3501, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	{0x3502, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	{0x3503, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{0x350b, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{0x3600, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{0x3603, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{0x3604, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{0x3605, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{0x3620, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{0x3621, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{0x3622, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{0x3628, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{0x3705, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{0x370a, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	{0x370c, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{0x370d, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	{0x3717, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	{0x3718, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	{0x3720, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	{0x3721, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	{0x3722, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	{0x3723, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	{0x3738, 0x99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{0x3781, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	{0x3784, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	{0x3789, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	{0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	{0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	{0x3803, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	{0x3804, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	{0x3805, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{0x3806, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{0x3807, 0xbf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	{0x3808, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	{0x3809, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	{0x380a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	{0x380b, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{0x380c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	{0x380d, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	{0x380e, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	{0x380f, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	{0x3810, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	{0x3811, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	{0x3812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	{0x3813, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	{0x3814, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	{0x3815, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	{0x3819, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{0x3820, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	{0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	{0x3a06, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	{0x3a07, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	{0x3a08, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	{0x3a09, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	{0x3a0a, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	{0x3a0b, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	{0x3a0c, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	{0x3a0d, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	{0x3a0e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	{0x3a0f, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	{0x3a10, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	{0x3a11, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	{0x4000, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	{0x4001, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	{0x4008, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	{0x4009, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	{0x4300, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	{0x430e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	{0x4602, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	{0x481b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	{0x481f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	{0x4837, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	{0x5000, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	{0x5001, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	{0x5002, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	{0x5003, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	{0x5004, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	{0x5005, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	{0x5280, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	{0x5281, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	{0x5282, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	{0x5283, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	{0x5284, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	{0x5285, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	{0x5286, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	{0x5287, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	{REG_NULL, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OV2685_LINK_FREQ_330MHZ		330000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	OV2685_LINK_FREQ_330MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const char * const ov2685_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	"Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	"Color Bar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	"Color Bar FADE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	"Random Data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	"Black White Square",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	"Color Square"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const int ov2685_test_pattern_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	OV2685_TEST_PATTERN_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	OV2685_TEST_PATTERN_COLOR_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	OV2685_TEST_PATTERN_COLOR_BAR_FADE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	OV2685_TEST_PATTERN_RANDOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	OV2685_TEST_PATTERN_BW_SQUARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	OV2685_TEST_PATTERN_COLOR_SQUARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const struct ov2685_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.width = 1600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.height = 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.exp_def = 0x04ee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.hts_def = 0x06a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.vts_def = 0x050e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.reg_list = ov2685_1600x1200_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int ov2685_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			    u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	u32 val_i, buf_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	__be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int ov2685_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			      const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		ret = ov2685_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 				       OV2685_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int ov2685_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			   u32 len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	__be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	__be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	/* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	msgs[0].buf = (u8 *)&reg_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	/* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	*val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void ov2685_fill_fmt(const struct ov2685_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			    struct v4l2_mbus_framefmt *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	fmt->width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	fmt->height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int ov2685_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			  struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			  struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	struct ov2685 *ov2685 = to_ov2685(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	/* only one mode supported for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ov2685_fill_fmt(ov2685->cur_mode, mbus_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int ov2685_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			  struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			  struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct ov2685 *ov2685 = to_ov2685(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	ov2685_fill_fmt(ov2685->cur_mode, mbus_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int ov2685_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 				 struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 				 struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	if (code->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int ov2685_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 				   struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 				   struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	int index = fse->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	fse->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	fse->min_width  = supported_modes[index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	fse->max_width  = supported_modes[index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	fse->max_height = supported_modes[index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	fse->min_height = supported_modes[index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static inline u32 ov2685_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	return DIV_ROUND_UP(cycles, OV2685_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int __ov2685_power_on(struct ov2685 *ov2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	struct device *dev = &ov2685->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	ret = clk_prepare_enable(ov2685->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	gpiod_set_value_cansleep(ov2685->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	ret = regulator_bulk_enable(OV2685_NUM_SUPPLIES, ov2685->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	/* The minimum delay between power supplies and reset rising can be 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	gpiod_set_value_cansleep(ov2685->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	/* 8192 xvclk cycles prior to the first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	delay_us = ov2685_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	/* HACK: ov2685 would output messy data after reset(R0103),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	 * writing register before .s_stream() as a workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	ret = ov2685_write_array(ov2685->client, ov2685->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		goto disable_supplies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) disable_supplies:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	regulator_bulk_disable(OV2685_NUM_SUPPLIES, ov2685->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	clk_disable_unprepare(ov2685->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void __ov2685_power_off(struct ov2685 *ov2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	/* 512 xvclk cycles after the last SCCB transaction or MIPI frame end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	u32 delay_us = ov2685_cal_delay(512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	clk_disable_unprepare(ov2685->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	gpiod_set_value_cansleep(ov2685->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	regulator_bulk_disable(OV2685_NUM_SUPPLIES, ov2685->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int ov2685_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	struct ov2685 *ov2685 = to_ov2685(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	struct i2c_client *client = ov2685->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	mutex_lock(&ov2685->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	if (on == ov2685->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		ret = pm_runtime_get_sync(&ov2685->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 			pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 			goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		ret = __v4l2_ctrl_handler_setup(&ov2685->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 			pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 			goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		ret = ov2685_write_reg(client, REG_SC_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 				OV2685_REG_VALUE_08BIT, SC_CTRL_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 			pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 			goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		ov2685_write_reg(client, REG_SC_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 				OV2685_REG_VALUE_08BIT, SC_CTRL_MODE_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		pm_runtime_put(&ov2685->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	ov2685->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	mutex_unlock(&ov2685->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int ov2685_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	struct ov2685 *ov2685 = to_ov2685(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	struct v4l2_mbus_framefmt *try_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	mutex_lock(&ov2685->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	try_fmt = v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	/* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	ov2685_fill_fmt(&supported_modes[0], try_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	mutex_unlock(&ov2685->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int __maybe_unused ov2685_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	struct ov2685 *ov2685 = to_ov2685(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	return __ov2685_power_on(ov2685);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int __maybe_unused ov2685_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	struct ov2685 *ov2685 = to_ov2685(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	__ov2685_power_off(ov2685);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const struct dev_pm_ops ov2685_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	SET_RUNTIME_PM_OPS(ov2685_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 			   ov2685_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int ov2685_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	struct ov2685 *ov2685 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 					     struct ov2685, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	struct i2c_client *client = ov2685->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	s64 max_expo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	/* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 		/* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 		max_expo = ov2685->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 		__v4l2_ctrl_modify_range(ov2685->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 					 ov2685->exposure->minimum, max_expo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 					 ov2685->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 					 ov2685->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 		ret = ov2685_write_reg(ov2685->client, OV2685_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 				       OV2685_REG_VALUE_24BIT, ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 		ret = ov2685_write_reg(ov2685->client, OV2685_REG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 				       OV2685_REG_VALUE_16BIT, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 		ret = ov2685_write_reg(ov2685->client, OV2685_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 				       OV2685_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 				       ctrl->val + ov2685->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 		ret = ov2685_write_reg(ov2685->client, OV2685_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 				       OV2685_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 				       ov2685_test_pattern_val[ctrl->val]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 		dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 			 __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static const struct v4l2_subdev_video_ops ov2685_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	.s_stream = ov2685_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static const struct v4l2_subdev_pad_ops ov2685_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	.enum_mbus_code = ov2685_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	.enum_frame_size = ov2685_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	.get_fmt = ov2685_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	.set_fmt = ov2685_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static const struct v4l2_subdev_ops ov2685_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	.video	= &ov2685_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	.pad	= &ov2685_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static const struct v4l2_subdev_internal_ops ov2685_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	.open = ov2685_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const struct v4l2_ctrl_ops ov2685_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	.s_ctrl = ov2685_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int ov2685_initialize_controls(struct ov2685 *ov2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	const struct ov2685_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	u64 exposure_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 	u32 pixel_rate, h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	handler = &ov2685->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	mode = ov2685->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	handler->lock = &ov2685->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 				      0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 	if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 		ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 	pixel_rate = (link_freq_menu_items[0] * 2 * OV2685_LANES) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 		     OV2685_BITS_PER_SAMPLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 			  0, pixel_rate, 1, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 	ov2685->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 				h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 	if (ov2685->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 		ov2685->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 	ov2685->vblank = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 				V4L2_CID_VBLANK, mode->vts_def - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 				OV2685_VTS_MAX - mode->height, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 				mode->vts_def - mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 	exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 	ov2685->exposure = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 				V4L2_CID_EXPOSURE, OV2685_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 				exposure_max, OV2685_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 				mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 	ov2685->anal_gain = v4l2_ctrl_new_std(handler, &ov2685_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 				V4L2_CID_ANALOGUE_GAIN, OV2685_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 				OV2685_GAIN_MAX, OV2685_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 				OV2685_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 	ov2685->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 				&ov2685_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 				ARRAY_SIZE(ov2685_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 				0, 0, ov2685_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 	if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 		ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 		dev_err(&ov2685->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 			"Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 		goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 	ov2685->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 	v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static int ov2685_check_sensor_id(struct ov2685 *ov2685,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 				  struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 	struct device *dev = &ov2685->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 	u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 	ret = ov2685_read_reg(client, OV2685_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 			      OV2685_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 	if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 		dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 	dev_info(dev, "Detected OV%04x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int ov2685_configure_regulators(struct ov2685 *ov2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 	for (i = 0; i < OV2685_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 		ov2685->supplies[i].supply = ov2685_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 	return devm_regulator_bulk_get(&ov2685->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 				       OV2685_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 				       ov2685->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int ov2685_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 			const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 	struct ov2685 *ov2685;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 	ov2685 = devm_kzalloc(dev, sizeof(*ov2685), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 	if (!ov2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 	ov2685->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 	ov2685->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 	ov2685->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 	if (IS_ERR(ov2685->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 		dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 	ret = clk_set_rate(ov2685->xvclk, OV2685_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 		dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 	if (clk_get_rate(ov2685->xvclk) != OV2685_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 		dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 	ov2685->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 	if (IS_ERR(ov2685->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 		dev_err(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 	ret = ov2685_configure_regulators(ov2685);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 		dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 	mutex_init(&ov2685->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) 	v4l2_i2c_subdev_init(&ov2685->subdev, client, &ov2685_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 	ret = ov2685_initialize_controls(ov2685);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) 		goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) 	ret = __ov2685_power_on(ov2685);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 		goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 	ret = ov2685_check_sensor_id(ov2685, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 		goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 	ov2685->subdev.internal_ops = &ov2685_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 	ov2685->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 	ov2685->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 	ov2685->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 	ret = media_entity_pads_init(&ov2685->subdev.entity, 1, &ov2685->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 		goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 	ret = v4l2_async_register_subdev(&ov2685->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 		dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 		goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 	pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 	pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 	pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 	media_entity_cleanup(&ov2685->subdev.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) 	__ov2685_power_off(ov2685);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) 	v4l2_ctrl_handler_free(&ov2685->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) 	mutex_destroy(&ov2685->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int ov2685_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) 	struct ov2685 *ov2685 = to_ov2685(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) 	v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 	media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) 	v4l2_ctrl_handler_free(&ov2685->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 	mutex_destroy(&ov2685->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) 	pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) 	if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 		__ov2685_power_off(ov2685);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) 	pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static const struct of_device_id ov2685_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) 	{ .compatible = "ovti,ov2685" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) MODULE_DEVICE_TABLE(of, ov2685_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static struct i2c_driver ov2685_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) 		.name = "ov2685",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) 		.pm = &ov2685_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 		.of_match_table = of_match_ptr(ov2685_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) 	.probe		= &ov2685_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) 	.remove		= &ov2685_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) module_i2c_driver(ov2685_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) MODULE_DESCRIPTION("OmniVision ov2685 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) MODULE_LICENSE("GPL v2");