^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ov2640 Camera Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on ov772x, ov9640 drivers and previous non merged implementations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2006, OmniVision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-image-sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VAL_SET(x, mask, rshift, lshift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ((((x) >> rshift) & mask) << lshift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * DSP registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * register offset for BANK_SEL == BANK_SEL_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R_BYPASS 0x05 /* Bypass DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define QS 0x44 /* Quantization Scale Factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CTRLI 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CTRLI_LP_DP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CTRLI_ROUND 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define XOFFL 0x53 /* OFFSET_X[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define YOFFL 0x54 /* OFFSET_Y[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VHYX 0x55 /* Offset and size completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DPRP 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TEST 0x57 /* Horizontal size completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ZMHH 0x5C /* Zoom: Speed and H&W completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BPADDR 0x7C /* SDE Indirect Register Access: Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BPDATA 0x7D /* SDE Indirect Register Access: Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CTRL2 0x86 /* DSP Module enable 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CTRL2_DCW_EN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CTRL2_SDE_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CTRL2_UV_ADJ_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CTRL2_UV_AVG_EN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CTRL2_CMX_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CTRL3 0x87 /* DSP Module enable 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CTRL3_BPC_EN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CTRL3_WPC_EN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SIZEL 0x8C /* Image Size Completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CTRL0 0xC2 /* DSP Module enable 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CTRL0_AEC_EN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CTRL0_AEC_SEL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CTRL0_STAT_SEL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CTRL0_VFIRST 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CTRL0_YUV422 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CTRL0_YUV_EN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CTRL0_RGB_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CTRL0_RAW_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CTRL1 0xC3 /* DSP Module enable 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CTRL1_CIP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CTRL1_DMY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CTRL1_RAW_GMA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CTRL1_DG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CTRL1_AWB 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CTRL1_AWB_GAIN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CTRL1_LENC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CTRL1_PRE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* REG 0xC7 (unknown name): affects Auto White Balance (AWB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * AWB_OFF 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * AWB_SIMPLE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * AWB_ON 0x00 (Advanced AWB ?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define R_DVP_SP 0xD3 /* DVP output speed control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define R_DVP_SP_AUTO_MODE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * = sysclk (48)/(2*[6:0]) (RAW);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMAGE_MODE 0xDA /* Image Output Format Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMAGE_MODE_Y8_DVP_EN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMAGE_MODE_JPEG_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMAGE_MODE_YUV422 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMAGE_MODE_RAW10 0x04 /* (DVP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMAGE_MODE_RGB565 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * mode (0 for HREF is same as sensor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * 1: Low byte first UYVY (C2[4] =0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * VYUY (C2[4] =1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * 0: High byte first YUYV (C2[4]=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * YVYU (C2[4] = 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RESET 0xE0 /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RESET_MICROC 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RESET_SCCB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RESET_JPEG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RESET_DVP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RESET_IPU 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RESET_CIF 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define REGED 0xED /* Register ED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define REGED_CLK_OUT_DIS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MS_SP 0xF0 /* SCCB Master Speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SS_ID 0xF7 /* SCCB Slave ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SS_CTRL 0xF8 /* SCCB Slave Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SS_CTRL_ADD_AUTO_INC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SS_CTRL_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SS_CTRL_DELAY_CLK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SS_CTRL_ACC_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SS_CTRL_SEN_PASS_THR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MC_BIST 0xF9 /* Microcontroller misc register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MC_BIST_RESET 0x80 /* Microcontroller Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MC_BIST_BOOT_ROM_SEL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MC_BIST_12KB_SEL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MC_BIST_12KB_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MC_BIST_512KB_SEL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MC_BIST_512KB_MASK 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MC_BIST_BUSY_BIT_R 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MC_BIST_MC_RES_ONE_SH_W 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MC_BIST_LAUNCH 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define BANK_SEL 0xFF /* Register Bank Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define BANK_SEL_DSP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define BANK_SEL_SENS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Sensor registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * register offset for BANK_SEL == BANK_SEL_SENS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GAIN 0x00 /* AGC - Gain control gain setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define COM1 0x03 /* Common control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define COM1_1_DUMMY_FR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define COM1_3_DUMMY_FR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define COM1_7_DUMMY_FR 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define COM1_VWIN_LSB_UXGA 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define COM1_VWIN_LSB_SVGA 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define COM1_VWIN_LSB_CIF 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define REG04 0x04 /* Register 04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define REG04_DEF 0x20 /* Always set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define REG04_VREF_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define REG04_HREF_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define COM2 0x09 /* Common control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Output drive capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PID 0x0A /* Product ID Number MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define VER 0x0B /* Product ID Number LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define COM3 0x0C /* Common control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define COM3_BAND_AUTO 0x02 /* Auto Banding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * snapshot sequence*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AEC 0x10 /* AEC[9:2] Exposure Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLKRC 0x11 /* Internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CLKRC_EN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define COM7 0x12 /* Common control 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define COM7_SRST 0x80 /* Initiates system reset. All registers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * set to factory default values after which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * the chip resumes normal operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define COM7_RES_SVGA 0x40 /* SVGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define COM7_RES_CIF 0x20 /* CIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define COM8 0x13 /* Common control 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define COM8_DEF 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define COM9 0x14 /* Common control 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Automatic gain ceiling - maximum AGC value [7:5]*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define COM10 0x15 /* Common control 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * PCLK (user can latch data at the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * falling edge of PCLK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * 0 otherwise. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define COM10_HREF_INV 0x08 /* Invert HREF polarity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * HREF negative for valid data*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define HSTART 0x17 /* Horizontal Window start MSB 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define HEND 0x18 /* Horizontal Window end MSB 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define VSTART 0x19 /* Vertical Window start MSB 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define VEND 0x1A /* Vertical Window end MSB 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MIDH 0x1C /* Manufacturer ID byte - high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MIDL 0x1D /* Manufacturer ID byte - low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define VV 0x26 /* AGC/AEC Fast mode operating region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define REG2A 0x2A /* Dummy pixel insert MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define FRARL 0x2B /* Dummy pixel insert LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define YAVG 0x2F /* Y/G Channel Average value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define REG32 0x32 /* Common Control 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ARCOM2 0x34 /* Zoom: Horizontal start point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define REG45 0x45 /* Register 45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define FLL 0x46 /* Frame Length Adjustment LSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define FLH 0x47 /* Frame Length Adjustment MSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define COM19 0x48 /* Zoom: Vertical start point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ZOOMS 0x49 /* Zoom: Vertical start point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define COM22 0x4B /* Flash light control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define COM25 0x4E /* For Banding operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define COM25_50HZ_BANDING_AEC_MSBS_MASK 0xC0 /* 50Hz Bd. AEC 2 MSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define COM25_60HZ_BANDING_AEC_MSBS_MASK 0x30 /* 60Hz Bd. AEC 2 MSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define COM25_50HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define COM25_60HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define BD50_50HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define BD60_60HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define REG5A 0x5A /* 50/60Hz Banding Maximum AEC Step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define BD50_MAX_AEC_STEP_MASK 0xF0 /* 50Hz Banding Max. AEC Step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define BD60_MAX_AEC_STEP_MASK 0x0F /* 60Hz Banding Max. AEC Step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define BD50_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define BD60_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MANUFACTURER_ID 0x7FA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define PID_OV2640 0x2642
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct regval_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u8 reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct ov2640_win_size {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) const struct regval_list *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct ov2640_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 cfmt_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) const struct ov2640_win_size *win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct gpio_desc *resetb_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct mutex lock; /* lock to protect streaming and power_count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int power_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * Registers settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define ENDMARKER { 0xff, 0xff }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct regval_list ov2640_init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { BANK_SEL, BANK_SEL_DSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { 0x2c, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { 0x2e, 0xdf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { BANK_SEL, BANK_SEL_SENS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 0x3c, 0x32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { CLKRC, CLKRC_DIV_SET(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { COM2, COM2_OCAP_Nx_SET(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { REG04, REG04_DEF | REG04_HREF_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { COM8, COM8_DEF | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { COM9, COM9_AGC_GAIN_8x | 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 0x2c, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 0x33, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 0x3a, 0x33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 0x3b, 0xfb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 0x3e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { 0x43, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { 0x16, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { 0x39, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { 0x35, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { 0x22, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { 0x37, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { 0x23, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { ARCOM2, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { 0x06, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { 0x06, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { 0x07, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { 0x0d, 0xb7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { 0x0e, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { 0x4c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { 0x4a, 0x81 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { 0x21, 0x99 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { AEW, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { AEB, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { 0x5c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { 0x63, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { FLL, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { COM3, 0x38 | COM3_BAND_AUTO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { REG5D, 0x55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { REG5E, 0x7d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { REG5F, 0x7d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { REG60, 0x55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { HISTO_LOW, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { HISTO_HIGH, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { 0x7c, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { 0x20, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { 0x28, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { 0x6c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { 0x6d, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { 0x6e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { 0x70, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { 0x71, 0x94 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { 0x73, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { 0x3d, 0x34 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { COM7, COM7_RES_UXGA | COM7_ZOOM_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { REG5A, BD50_MAX_AEC_STEP_SET(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) | BD60_MAX_AEC_STEP_SET(8) }, /* 0x57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { COM25, COM25_50HZ_BANDING_AEC_MSBS_SET(0x0bb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) | COM25_60HZ_BANDING_AEC_MSBS_SET(0x09c) }, /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { BD50, BD50_50HZ_BANDING_AEC_LSBS_SET(0x0bb) }, /* 0xbb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { BD60, BD60_60HZ_BANDING_AEC_LSBS_SET(0x09c) }, /* 0x9c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { BANK_SEL, BANK_SEL_DSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { 0xe5, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { 0x41, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { RESET, RESET_JPEG | RESET_DVP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { 0x76, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { 0x33, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { 0x42, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { 0x43, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { 0x4c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { 0x88, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { 0xd7, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { 0xd9, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { 0xc8, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { 0xc9, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { BPADDR, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { BPDATA, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { BPADDR, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { BPDATA, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { BPDATA, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) { BPADDR, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { BPDATA, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { BPDATA, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { BPDATA, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { 0x90, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { 0x91, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { 0x91, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { 0x91, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { 0x91, 0x5a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { 0x91, 0x69 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { 0x91, 0x75 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { 0x91, 0x7e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { 0x91, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { 0x91, 0x8f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { 0x91, 0x96 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { 0x91, 0xa3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { 0x91, 0xaf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { 0x91, 0xc4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { 0x91, 0xd7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { 0x91, 0xe8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { 0x91, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { 0x92, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { 0x93, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { 0x93, 0xe3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { 0x93, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { 0x93, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { 0x93, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { 0x93, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { 0x93, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { 0x93, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { 0x93, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { 0x93, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { 0x93, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { 0x93, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { 0x93, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { 0x96, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) { 0x97, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) { 0x97, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) { 0x97, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) { 0x97, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { 0x97, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { 0x97, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { 0x97, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { 0x97, 0x26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { 0x97, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { 0x97, 0x98 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { 0x97, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { 0x97, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { 0x97, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { 0xa4, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { 0xa8, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { 0xc5, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { 0xc6, 0x51 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { 0xbf, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) { 0xc7, 0x10 }, /* simple AWB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { 0xb6, 0x66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { 0xb8, 0xA5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { 0xb7, 0x64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { 0xb9, 0x7C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { 0xb3, 0xaf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { 0xb4, 0x97 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { 0xb5, 0xFF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { 0xb0, 0xC5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { 0xb1, 0x94 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { 0xb2, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { 0xc4, 0x5c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { 0xa6, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { 0xa7, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { 0xa7, 0xd8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { 0xa7, 0x1b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { 0xa7, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) { 0xa7, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { 0xa7, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { 0xa7, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { 0xa7, 0xd8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { 0xa7, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { 0xa7, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { 0xa7, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { 0xa7, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { 0xa7, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { 0xa7, 0xd8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) { 0xa7, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { 0xa7, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { 0xa7, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { 0xa7, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { 0x7f, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { 0xe5, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { 0xe1, 0x77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { 0xdd, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * Register settings for window size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * The preamble, setup the internal DSP to input an UXGA (1600x1200) image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * Then the different zooming configurations will setup the output image size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const struct regval_list ov2640_size_change_preamble_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { BANK_SEL, BANK_SEL_DSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) { RESET, RESET_DVP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { SIZEL, SIZEL_HSIZE8_11_SET(UXGA_WIDTH) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) SIZEL_HSIZE8_SET(UXGA_WIDTH) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) SIZEL_VSIZE8_SET(UXGA_HEIGHT) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) { HSIZE8, HSIZE8_SET(UXGA_WIDTH) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { VSIZE8, VSIZE8_SET(UXGA_HEIGHT) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) { HSIZE, HSIZE_SET(UXGA_WIDTH) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) { VSIZE, VSIZE_SET(UXGA_HEIGHT) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) { XOFFL, XOFFL_SET(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) { YOFFL, YOFFL_SET(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) { VHYX, VHYX_HSIZE_SET(UXGA_WIDTH) | VHYX_VSIZE_SET(UXGA_HEIGHT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) { TEST, TEST_HSIZE_SET(UXGA_WIDTH) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) CTRLI_H_DIV_SET(h_div)}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) { ZMOW, ZMOW_OUTW_SET(x) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) { ZMOH, ZMOH_OUTH_SET(y) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) { R_DVP_SP, pclk_div }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { RESET, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const struct regval_list ov2640_qcif_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PER_SIZE_REG_SEQ(QCIF_WIDTH, QCIF_HEIGHT, 3, 3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static const struct regval_list ov2640_qvga_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PER_SIZE_REG_SEQ(QVGA_WIDTH, QVGA_HEIGHT, 2, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const struct regval_list ov2640_cif_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PER_SIZE_REG_SEQ(CIF_WIDTH, CIF_HEIGHT, 2, 2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const struct regval_list ov2640_vga_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PER_SIZE_REG_SEQ(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const struct regval_list ov2640_svga_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PER_SIZE_REG_SEQ(SVGA_WIDTH, SVGA_HEIGHT, 1, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const struct regval_list ov2640_xga_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PER_SIZE_REG_SEQ(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) { CTRLI, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const struct regval_list ov2640_sxga_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PER_SIZE_REG_SEQ(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { CTRLI, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const struct regval_list ov2640_uxga_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PER_SIZE_REG_SEQ(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { CTRLI, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define OV2640_SIZE(n, w, h, r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {.name = n, .width = w , .height = h, .regs = r }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const struct ov2640_win_size ov2640_supported_win_sizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) OV2640_SIZE("QCIF", QCIF_WIDTH, QCIF_HEIGHT, ov2640_qcif_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) OV2640_SIZE("QVGA", QVGA_WIDTH, QVGA_HEIGHT, ov2640_qvga_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) OV2640_SIZE("CIF", CIF_WIDTH, CIF_HEIGHT, ov2640_cif_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) OV2640_SIZE("VGA", VGA_WIDTH, VGA_HEIGHT, ov2640_vga_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) OV2640_SIZE("SVGA", SVGA_WIDTH, SVGA_HEIGHT, ov2640_svga_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) OV2640_SIZE("XGA", XGA_WIDTH, XGA_HEIGHT, ov2640_xga_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) OV2640_SIZE("SXGA", SXGA_WIDTH, SXGA_HEIGHT, ov2640_sxga_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) OV2640_SIZE("UXGA", UXGA_WIDTH, UXGA_HEIGHT, ov2640_uxga_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * Register settings for pixel formats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const struct regval_list ov2640_format_change_preamble_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { BANK_SEL, BANK_SEL_DSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { R_BYPASS, R_BYPASS_USE_DSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static const struct regval_list ov2640_yuyv_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { IMAGE_MODE, IMAGE_MODE_YUV422 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { 0xd7, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { 0x33, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) { 0xe5, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { 0xe1, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) { RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { R_BYPASS, R_BYPASS_USE_DSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const struct regval_list ov2640_uyvy_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { 0xd7, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) { 0x33, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { 0xe1, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) { RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) { R_BYPASS, R_BYPASS_USE_DSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const struct regval_list ov2640_rgb565_be_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) { IMAGE_MODE, IMAGE_MODE_RGB565 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { 0xd7, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) { RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) { R_BYPASS, R_BYPASS_USE_DSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const struct regval_list ov2640_rgb565_le_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { 0xd7, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { RESET, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { R_BYPASS, R_BYPASS_USE_DSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static u32 ov2640_codes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MEDIA_BUS_FMT_YUYV8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) MEDIA_BUS_FMT_YVYU8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MEDIA_BUS_FMT_VYUY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) MEDIA_BUS_FMT_RGB565_2X8_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MEDIA_BUS_FMT_RGB565_2X8_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * General functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static struct ov2640_priv *to_ov2640(const struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return container_of(i2c_get_clientdata(client), struct ov2640_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static int ov2640_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) const struct regval_list *vals)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) while ((vals->reg_num != 0xff) || (vals->value != 0xff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = i2c_smbus_write_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) vals->reg_num, vals->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) vals->reg_num, vals->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) vals++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static int ov2640_mask_set(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u8 reg, u8 mask, u8 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) s32 val = i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) val |= set & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return i2c_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int ov2640_reset(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static const struct regval_list reset_seq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {BANK_SEL, BANK_SEL_SENS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {COM7, COM7_SRST},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ENDMARKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = ov2640_write_array(client, reset_seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_dbg(&client->dev, "%s: (ret %d)", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static const char * const ov2640_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) "Eight Vertical Colour Bars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct v4l2_subdev *sd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) &container_of(ctrl->handler, struct ov2640_priv, hdl)->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct ov2640_priv *priv = to_ov2640(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* v4l2_ctrl_lock() locks our own mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * If the device is not powered up by the host driver, do not apply any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * controls to H/W at this time. Instead the controls will be restored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * when the streaming is started.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (!priv->power_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ret = i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) val = ctrl->val ? REG04_VFLIP_IMG | REG04_VREF_EN : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return ov2640_mask_set(client, REG04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) REG04_VFLIP_IMG | REG04_VREF_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* NOTE: REG04_VREF_EN: 1 line shift / even/odd line swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) val = ctrl->val ? REG04_HFLIP_IMG : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) val = ctrl->val ? COM7_COLOR_BAR_TEST : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return ov2640_mask_set(client, COM7, COM7_COLOR_BAR_TEST, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static int ov2640_g_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (reg->reg > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ret = i2c_smbus_read_byte_data(client, reg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) reg->val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int ov2640_s_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (reg->reg > 0xff ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) reg->val > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static void ov2640_set_power(struct ov2640_priv *priv, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (priv->pwdn_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) gpiod_direction_output(priv->pwdn_gpio, !on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (on && priv->resetb_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* Active the resetb pin to perform a reset pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) gpiod_direction_output(priv->resetb_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) gpiod_set_value(priv->resetb_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static int ov2640_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct ov2640_priv *priv = to_ov2640(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * If the power count is modified from 0 to != 0 or from != 0 to 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * update the power state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (priv->power_count == !on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ov2640_set_power(priv, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) priv->power_count += on ? 1 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) WARN_ON(priv->power_count < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* Select the nearest higher resolution for capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static const struct ov2640_win_size *ov2640_select_win(u32 width, u32 height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) int i, default_size = ARRAY_SIZE(ov2640_supported_win_sizes) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (ov2640_supported_win_sizes[i].width >= width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ov2640_supported_win_sizes[i].height >= height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return &ov2640_supported_win_sizes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return &ov2640_supported_win_sizes[default_size];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int ov2640_set_params(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) const struct ov2640_win_size *win, u32 code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) const struct regval_list *selected_cfmt_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) switch (code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) case MEDIA_BUS_FMT_RGB565_2X8_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) dev_dbg(&client->dev, "%s: Selected cfmt RGB565 BE", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) selected_cfmt_regs = ov2640_rgb565_be_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) case MEDIA_BUS_FMT_RGB565_2X8_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_dbg(&client->dev, "%s: Selected cfmt RGB565 LE", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) selected_cfmt_regs = ov2640_rgb565_le_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) case MEDIA_BUS_FMT_YUYV8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev_dbg(&client->dev, "%s: Selected cfmt YUYV (YUV422)", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) selected_cfmt_regs = ov2640_yuyv_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dev_dbg(&client->dev, "%s: Selected cfmt UYVY", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) selected_cfmt_regs = ov2640_uyvy_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) case MEDIA_BUS_FMT_YVYU8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dev_dbg(&client->dev, "%s: Selected cfmt YVYU", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) selected_cfmt_regs = ov2640_yuyv_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) case MEDIA_BUS_FMT_VYUY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dev_dbg(&client->dev, "%s: Selected cfmt VYUY", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) selected_cfmt_regs = ov2640_uyvy_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* reset hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ov2640_reset(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* initialize the sensor with default data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dev_dbg(&client->dev, "%s: Init default", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ret = ov2640_write_array(client, ov2640_init_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* select preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) dev_dbg(&client->dev, "%s: Set size to %s", __func__, win->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = ov2640_write_array(client, ov2640_size_change_preamble_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* set size win */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ret = ov2640_write_array(client, win->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* cfmt preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dev_dbg(&client->dev, "%s: Set cfmt", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret = ov2640_write_array(client, ov2640_format_change_preamble_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* set cfmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ret = ov2640_write_array(client, selected_cfmt_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) val = (code == MEDIA_BUS_FMT_YVYU8_2X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) || (code == MEDIA_BUS_FMT_VYUY8_2X8) ? CTRL0_VFIRST : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ret = ov2640_mask_set(client, CTRL0, CTRL0_VFIRST, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dev_err(&client->dev, "%s: Error %d", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ov2640_reset(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static int ov2640_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct ov2640_priv *priv = to_ov2640(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) mf = v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) format->format = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) mf->width = priv->win->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) mf->height = priv->win->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) mf->code = priv->cfmt_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) mf->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) mf->quantization = V4L2_QUANTIZATION_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static int ov2640_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct ov2640_priv *priv = to_ov2640(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) const struct ov2640_win_size *win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* select suitable win */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) win = ov2640_select_win(mf->width, mf->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) mf->width = win->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) mf->height = win->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) mf->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) mf->quantization = V4L2_QUANTIZATION_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) switch (mf->code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) case MEDIA_BUS_FMT_RGB565_2X8_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) case MEDIA_BUS_FMT_RGB565_2X8_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) case MEDIA_BUS_FMT_YUYV8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) case MEDIA_BUS_FMT_YVYU8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) case MEDIA_BUS_FMT_VYUY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct ov2640_priv *priv = to_ov2640(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (priv->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* select win */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) priv->win = win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* select format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) priv->cfmt_code = mf->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) cfg->try_fmt = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static int ov2640_init_cfg(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct v4l2_subdev_pad_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) const struct ov2640_win_size *win =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ov2640_select_win(SVGA_WIDTH, SVGA_HEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) try_fmt->width = win->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) try_fmt->height = win->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) try_fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) try_fmt->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) try_fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) try_fmt->quantization = V4L2_QUANTIZATION_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) try_fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static int ov2640_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (code->pad || code->index >= ARRAY_SIZE(ov2640_codes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) code->code = ov2640_codes[code->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static int ov2640_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) switch (sel->target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) case V4L2_SEL_TGT_CROP_BOUNDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) case V4L2_SEL_TGT_CROP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) sel->r.top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) sel->r.width = UXGA_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) sel->r.height = UXGA_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static int ov2640_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct ov2640_priv *priv = to_ov2640(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (priv->streaming == !on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ret = ov2640_set_params(client, priv->win,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) priv->cfmt_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ret = __v4l2_ctrl_handler_setup(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) priv->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static int ov2640_video_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct ov2640_priv *priv = to_ov2640(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) u8 pid, ver, midh, midl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) const char *devname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ret = ov2640_s_power(&priv->subdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * check and show product ID and manufacturer ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) pid = i2c_smbus_read_byte_data(client, PID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ver = i2c_smbus_read_byte_data(client, VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) midh = i2c_smbus_read_byte_data(client, MIDH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) midl = i2c_smbus_read_byte_data(client, MIDL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) switch (VERSION(pid, ver)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) case PID_OV2640:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) devname = "ov2640";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) "Product ID error %x:%x\n", pid, ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) dev_info(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) devname, pid, ver, midh, midl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ov2640_s_power(&priv->subdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static const struct v4l2_ctrl_ops ov2640_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .s_ctrl = ov2640_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static const struct v4l2_subdev_core_ops ov2640_subdev_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .log_status = v4l2_ctrl_subdev_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .g_register = ov2640_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .s_register = ov2640_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .s_power = ov2640_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static const struct v4l2_subdev_pad_ops ov2640_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .init_cfg = ov2640_init_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .enum_mbus_code = ov2640_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .get_selection = ov2640_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .get_fmt = ov2640_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .set_fmt = ov2640_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static const struct v4l2_subdev_video_ops ov2640_subdev_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .s_stream = ov2640_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static const struct v4l2_subdev_ops ov2640_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .core = &ov2640_subdev_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .pad = &ov2640_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .video = &ov2640_subdev_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static int ov2640_probe_dt(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct ov2640_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Request the reset GPIO deasserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (!priv->resetb_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) dev_dbg(&client->dev, "resetb gpio is not assigned!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ret = PTR_ERR_OR_ZERO(priv->resetb_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (ret && ret != -ENOSYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) "Error %d while getting resetb gpio\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* Request the power down GPIO asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (!priv->pwdn_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) dev_dbg(&client->dev, "pwdn gpio is not assigned!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ret = PTR_ERR_OR_ZERO(priv->pwdn_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (ret && ret != -ENOSYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) "Error %d while getting pwdn gpio\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * i2c_driver functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static int ov2640_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct ov2640_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) dev_err(&adapter->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) "OV2640: I2C-Adapter doesn't support SMBUS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (client->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) priv->clk = devm_clk_get(&client->dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ret = ov2640_probe_dt(client, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) priv->win = ov2640_select_win(SVGA_WIDTH, SVGA_HEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) priv->cfmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) v4l2_i2c_subdev_init(&priv->subdev, client, &ov2640_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) v4l2_ctrl_handler_init(&priv->hdl, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) priv->hdl.lock = &priv->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) v4l2_ctrl_new_std_menu_items(&priv->hdl, &ov2640_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) ARRAY_SIZE(ov2640_test_pattern_menu) - 1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ov2640_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) priv->subdev.ctrl_handler = &priv->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (priv->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) ret = priv->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) priv->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) priv->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ret = media_entity_pads_init(&priv->subdev.entity, 1, &priv->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) ret = ov2640_video_probe(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) goto err_videoprobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) ret = v4l2_async_register_subdev(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) goto err_videoprobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dev_info(&adapter->dev, "OV2640 Probed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) err_videoprobe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) media_entity_cleanup(&priv->subdev.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) err_hdl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) v4l2_ctrl_handler_free(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) mutex_destroy(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static int ov2640_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) struct ov2640_priv *priv = to_ov2640(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) v4l2_async_unregister_subdev(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) v4l2_ctrl_handler_free(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) mutex_destroy(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) media_entity_cleanup(&priv->subdev.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) v4l2_device_unregister_subdev(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static const struct i2c_device_id ov2640_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) { "ov2640", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) MODULE_DEVICE_TABLE(i2c, ov2640_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static const struct of_device_id ov2640_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {.compatible = "ovti,ov2640", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) MODULE_DEVICE_TABLE(of, ov2640_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static struct i2c_driver ov2640_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .name = "ov2640",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .of_match_table = of_match_ptr(ov2640_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .probe_new = ov2640_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .remove = ov2640_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .id_table = ov2640_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) module_i2c_driver(ov2640_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) MODULE_DESCRIPTION("Driver for Omni Vision 2640 sensor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) MODULE_AUTHOR("Alberto Panizzo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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