^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2017 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define OV13858_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define OV13858_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define OV13858_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OV13858_REG_MODE_SELECT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define OV13858_MODE_STANDBY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define OV13858_MODE_STREAMING 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OV13858_REG_SOFTWARE_RST 0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OV13858_SOFTWARE_RST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* PLL1 generates PCLK and MIPI_PHY_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OV13858_REG_PLL1_CTRL_0 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OV13858_REG_PLL1_CTRL_1 0x0301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OV13858_REG_PLL1_CTRL_2 0x0302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OV13858_REG_PLL1_CTRL_3 0x0303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OV13858_REG_PLL1_CTRL_4 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OV13858_REG_PLL1_CTRL_5 0x0305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OV13858_REG_PLL2_CTRL_B 0x030b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OV13858_REG_PLL2_CTRL_C 0x030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OV13858_REG_PLL2_CTRL_D 0x030d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OV13858_REG_PLL2_CTRL_E 0x030e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OV13858_REG_PLL2_CTRL_F 0x030f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OV13858_REG_PLL2_CTRL_12 0x0312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OV13858_REG_MIPI_SC_CTRL0 0x3016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OV13858_REG_MIPI_SC_CTRL1 0x3022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Chip ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OV13858_REG_CHIP_ID 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OV13858_CHIP_ID 0x00d855
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* V_TIMING internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OV13858_REG_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OV13858_VTS_30FPS 0x0c8e /* 30 fps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OV13858_VTS_60FPS 0x0648 /* 60 fps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OV13858_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* HBLANK control - read only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OV13858_PPL_270MHZ 2244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OV13858_PPL_540MHZ 4488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Exposure control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OV13858_REG_EXPOSURE 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OV13858_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV13858_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV13858_EXPOSURE_DEFAULT 0x640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Analog gain control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OV13858_REG_ANALOG_GAIN 0x3508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OV13858_ANA_GAIN_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OV13858_ANA_GAIN_MAX 0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OV13858_ANA_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OV13858_ANA_GAIN_DEFAULT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Digital gain control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OV13858_REG_B_MWB_GAIN 0x5100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OV13858_REG_G_MWB_GAIN 0x5102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OV13858_REG_R_MWB_GAIN 0x5104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OV13858_DGTL_GAIN_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OV13858_DGTL_GAIN_MAX 16384 /* Max = 16 X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OV13858_DGTL_GAIN_DEFAULT 1024 /* Default gain = 1 X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OV13858_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Test Pattern Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OV13858_REG_TEST_PATTERN 0x4503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OV13858_TEST_PATTERN_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OV13858_TEST_PATTERN_MASK 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Number of frames to skip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OV13858_NUM_OF_SKIP_FRAMES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct ov13858_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u16 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct ov13858_reg_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 num_of_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const struct ov13858_reg *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Link frequency config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct ov13858_link_freq_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 pixels_per_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* PLL registers for this link frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct ov13858_reg_list reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Mode : resolution and related config&values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct ov13858_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Frame width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Frame height */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* V-timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 vts_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Index of Link frequency config to be used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 link_freq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Default register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct ov13858_reg_list reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* 4224x3136 needs 1080Mbps/lane, 4 lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct ov13858_reg mipi_data_rate_1080mbps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* PLL1 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {OV13858_REG_PLL1_CTRL_0, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {OV13858_REG_PLL1_CTRL_1, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {OV13858_REG_PLL1_CTRL_2, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {OV13858_REG_PLL1_CTRL_3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {OV13858_REG_PLL1_CTRL_4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {OV13858_REG_PLL1_CTRL_5, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* PLL2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {OV13858_REG_PLL2_CTRL_B, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {OV13858_REG_PLL2_CTRL_C, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {OV13858_REG_PLL2_CTRL_D, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {OV13858_REG_PLL2_CTRL_E, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {OV13858_REG_PLL2_CTRL_F, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {OV13858_REG_PLL2_CTRL_12, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {OV13858_REG_MIPI_SC_CTRL0, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {OV13858_REG_MIPI_SC_CTRL1, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * 4 lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct ov13858_reg mipi_data_rate_540mbps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* PLL1 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {OV13858_REG_PLL1_CTRL_0, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {OV13858_REG_PLL1_CTRL_1, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {OV13858_REG_PLL1_CTRL_2, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {OV13858_REG_PLL1_CTRL_3, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {OV13858_REG_PLL1_CTRL_4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {OV13858_REG_PLL1_CTRL_5, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* PLL2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {OV13858_REG_PLL2_CTRL_B, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {OV13858_REG_PLL2_CTRL_C, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {OV13858_REG_PLL2_CTRL_D, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {OV13858_REG_PLL2_CTRL_E, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {OV13858_REG_PLL2_CTRL_F, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {OV13858_REG_PLL2_CTRL_12, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {OV13858_REG_MIPI_SC_CTRL0, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {OV13858_REG_MIPI_SC_CTRL1, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct ov13858_reg mode_4224x3136_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x3013, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x301b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x301f, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x3106, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x3107, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x350a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x350e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x3510, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x3511, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x3512, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x3600, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x3601, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x3602, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x3612, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x3613, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3620, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3621, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3622, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3624, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3640, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x3641, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x3660, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3661, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3662, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3664, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3665, 0xa7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x366e, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x366f, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3674, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3679, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x367f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3680, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3681, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3682, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3683, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3684, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3709, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3714, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x371a, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3737, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3738, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3739, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x373d, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3764, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3765, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x37a1, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x37a8, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x37ab, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x37c2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x37c3, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x37c5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x37d8, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x37d9, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x37da, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x37dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x37e0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x37e1, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x37e2, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x37e3, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x37e4, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x37e5, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x37e6, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3803, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3804, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3805, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3806, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3807, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3808, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x380a, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x380b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x380c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x380d, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x380e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x380f, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3811, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3813, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3815, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3816, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3817, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3820, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3822, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3823, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3826, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3827, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3829, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3832, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3c80, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3c87, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3c8c, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3c8d, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3c90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3c91, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3c92, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x3c93, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3c94, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3c95, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3c96, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3c97, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3c98, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3d8c, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3d8d, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3f00, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3f03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x4001, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x4008, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x4009, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x4011, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x4017, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x4050, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x4051, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x4052, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x4053, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x4054, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x4055, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x4056, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x4057, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x4058, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x4059, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x405e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x4500, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x4503, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x450a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x4809, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x480c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x481f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x4833, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x4837, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x4902, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x4d00, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x4d01, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x4d02, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x4d03, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x4d04, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x4d05, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x5000, 0xfd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x5001, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x5040, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x5041, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x5042, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x5043, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x5044, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x5180, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x5181, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x5182, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x5183, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x5200, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x520b, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x520c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x5300, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x5301, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x5302, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x5303, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x5304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x5305, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x5306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x5307, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x5308, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x5309, 0xa5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x530a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x530b, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x530c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x530d, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x530e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x530f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x5310, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x5311, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x5312, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x5313, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x5314, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x5315, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x5316, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x5317, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x5318, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x5319, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x531a, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x531b, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x531c, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x531d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x5405, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x5406, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x5407, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x5408, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const struct ov13858_reg mode_2112x1568_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x3013, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x301b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x301f, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x3106, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x3107, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x350a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x350e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3510, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3511, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3512, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3600, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x3601, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x3602, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3612, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x3613, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x3620, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x3621, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x3622, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x3624, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3640, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3641, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x3660, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x3661, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x3662, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x3664, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x3665, 0xa7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x366e, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x366f, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x3674, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3679, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x367f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3680, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x3681, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3682, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x3683, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x3684, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x3709, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x3714, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x371a, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x3737, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x3738, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x3739, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x373d, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x3764, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x3765, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x37a1, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x37a8, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x37ab, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x37c2, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x37c3, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x37c5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x37d8, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x37d9, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x37da, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x37dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x37e0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x37e1, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x37e2, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x37e3, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x37e4, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x37e5, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x37e6, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3803, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x3804, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x3805, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3806, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3807, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3808, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3809, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x380a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x380b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x380c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x380d, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x380e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x380f, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x3811, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x3813, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x3814, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x3815, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3816, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3817, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x3820, 0xab},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x3822, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x3823, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x3826, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x3827, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x3829, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x3832, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x3c80, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x3c87, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x3c8c, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x3c8d, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x3c90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x3c91, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x3c92, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x3c93, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x3c94, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x3c95, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x3c96, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x3c97, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x3c98, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x3d8c, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x3d8d, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x3f00, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x3f03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x4001, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x4008, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x4009, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x4011, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x4017, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x4050, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x4051, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x4052, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x4053, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x4054, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x4055, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x4056, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x4057, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x4058, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x4059, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x405e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x4500, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x4503, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x450a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x4809, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x480c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x481f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x4833, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x4837, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x4902, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x4d00, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x4d01, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x4d02, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x4d03, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x4d04, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x4d05, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x5000, 0xfd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x5001, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x5040, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x5041, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x5042, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x5043, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x5044, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x5180, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x5181, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x5182, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x5183, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x5200, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x520b, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x520c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x5300, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x5301, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x5302, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x5303, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x5304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x5305, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x5306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x5307, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x5308, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x5309, 0xa5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x530a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x530b, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x530c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x530d, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x530e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x530f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x5310, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x5311, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x5312, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x5313, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x5314, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x5315, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x5316, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x5317, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x5318, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x5319, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x531a, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x531b, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x531c, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x531d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x5405, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x5406, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x5407, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x5408, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const struct ov13858_reg mode_2112x1188_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x3013, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x301b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x301f, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x3106, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x3107, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x350a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x350e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x3510, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x3511, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x3512, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x3600, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x3601, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x3602, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x3612, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x3613, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x3620, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x3621, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x3622, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x3624, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x3640, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x3641, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x3660, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x3661, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x3662, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x3664, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x3665, 0xa7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x366e, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x366f, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x3674, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x3679, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x367f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x3680, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x3681, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x3682, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x3683, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x3684, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x3709, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x3714, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x371a, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x3737, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x3738, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x3739, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x373d, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x3764, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x3765, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x37a1, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x37a8, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x37ab, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x37c2, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x37c3, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x37c5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x37d8, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x37d9, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x37da, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x37dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x37e0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x37e1, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x37e2, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x37e3, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x37e4, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x37e5, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x37e6, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x3802, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x3803, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x3804, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x3805, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x3806, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x3807, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {0x3808, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0x3809, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x380a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x380b, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x380c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x380d, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x380e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x380f, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x3811, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x3813, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x3814, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x3815, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x3816, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x3817, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x3820, 0xab},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x3822, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x3823, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x3826, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x3827, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x3829, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x3832, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x3c80, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x3c87, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x3c8c, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {0x3c8d, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {0x3c90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {0x3c91, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {0x3c92, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {0x3c93, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {0x3c94, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {0x3c95, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {0x3c96, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {0x3c97, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0x3c98, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {0x3d8c, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {0x3d8d, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {0x3f00, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {0x3f03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {0x4001, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {0x4008, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {0x4009, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {0x4011, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {0x4017, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {0x4050, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {0x4051, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x4052, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x4053, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x4054, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x4055, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x4056, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {0x4057, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {0x4058, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {0x4059, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {0x405e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {0x4500, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {0x4503, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {0x450a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {0x4809, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {0x480c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {0x481f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {0x4833, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {0x4837, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {0x4902, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {0x4d00, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {0x4d01, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {0x4d02, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {0x4d03, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {0x4d04, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {0x4d05, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {0x5000, 0xfd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {0x5001, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {0x5040, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {0x5041, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {0x5042, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {0x5043, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {0x5044, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {0x5180, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {0x5181, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {0x5182, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {0x5183, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {0x5200, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {0x520b, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {0x520c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {0x5300, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {0x5301, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {0x5302, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {0x5303, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {0x5304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {0x5305, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {0x5306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {0x5307, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {0x5308, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {0x5309, 0xa5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {0x530a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {0x530b, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {0x530c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {0x530d, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {0x530e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {0x530f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {0x5310, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {0x5311, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {0x5312, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {0x5313, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {0x5314, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {0x5315, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {0x5316, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {0x5317, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {0x5318, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {0x5319, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {0x531a, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {0x531b, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {0x531c, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {0x531d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {0x5405, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {0x5406, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {0x5407, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {0x5408, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const struct ov13858_reg mode_1056x784_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {0x3013, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {0x301b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0x301f, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0x3106, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0x3107, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0x350a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {0x350e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {0x3510, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {0x3511, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {0x3512, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {0x3600, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {0x3601, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {0x3602, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {0x3612, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {0x3613, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {0x3620, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {0x3621, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {0x3622, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0x3624, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {0x3640, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {0x3641, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {0x3660, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {0x3661, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {0x3662, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {0x3664, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {0x3665, 0xa7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {0x366e, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {0x366f, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {0x3674, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {0x3679, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {0x367f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {0x3680, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {0x3681, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {0x3682, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {0x3683, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {0x3684, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {0x3709, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {0x3714, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {0x371a, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {0x3737, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {0x3738, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {0x3739, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {0x373d, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {0x3764, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {0x3765, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {0x37a1, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {0x37a8, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {0x37ab, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {0x37c2, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {0x37c3, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {0x37c5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {0x37d8, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {0x37d9, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {0x37da, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {0x37dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {0x37e0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {0x37e1, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {0x37e2, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {0x37e3, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {0x37e4, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {0x37e5, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {0x37e6, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {0x3803, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {0x3804, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {0x3805, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {0x3806, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {0x3807, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {0x3808, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {0x3809, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {0x380a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {0x380b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {0x380c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {0x380d, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {0x380e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {0x380f, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {0x3811, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {0x3813, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {0x3814, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {0x3815, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {0x3816, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {0x3817, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {0x3820, 0xac},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {0x3822, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {0x3823, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {0x3826, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {0x3827, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {0x3829, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {0x3832, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {0x3c80, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {0x3c87, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {0x3c8c, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {0x3c8d, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {0x3c90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {0x3c91, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {0x3c92, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {0x3c93, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {0x3c94, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {0x3c95, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {0x3c96, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {0x3c97, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {0x3c98, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {0x3d8c, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {0x3d8d, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {0x3f00, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {0x3f03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {0x4001, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {0x4008, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {0x4009, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {0x4011, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {0x4017, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {0x4050, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {0x4051, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {0x4052, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {0x4053, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {0x4054, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {0x4055, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {0x4056, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {0x4057, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {0x4058, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {0x4059, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {0x405e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {0x4500, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {0x4503, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {0x450a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {0x4809, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {0x480c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {0x481f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {0x4833, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {0x4837, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {0x4902, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {0x4d00, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {0x4d01, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {0x4d02, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {0x4d03, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {0x4d04, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {0x4d05, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {0x5000, 0xfd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {0x5001, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {0x5040, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {0x5041, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {0x5042, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {0x5043, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {0x5044, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {0x5180, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {0x5181, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {0x5182, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {0x5183, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {0x5200, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {0x520b, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {0x520c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {0x5300, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {0x5301, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {0x5302, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {0x5303, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {0x5304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {0x5305, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {0x5306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {0x5307, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {0x5308, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {0x5309, 0xa5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {0x530a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {0x530b, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {0x530c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {0x530d, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {0x530e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {0x530f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {0x5310, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {0x5311, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {0x5312, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {0x5313, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {0x5314, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {0x5315, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {0x5316, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {0x5317, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {0x5318, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {0x5319, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {0x531a, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {0x531b, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {0x531c, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {0x531d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {0x5405, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {0x5406, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {0x5407, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {0x5408, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static const char * const ov13858_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* Configurations for supported link frequencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define OV13858_NUM_OF_LINK_FREQS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define OV13858_LINK_FREQ_540MHZ 540000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define OV13858_LINK_FREQ_270MHZ 270000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define OV13858_LINK_FREQ_INDEX_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define OV13858_LINK_FREQ_INDEX_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * data rate => double data rate; number of lanes => 4; bits per pixel => 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static u64 link_freq_to_pixel_rate(u64 f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) f *= 2 * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) do_div(f, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* Menu items for LINK_FREQ V4L2 control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) OV13858_LINK_FREQ_540MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) OV13858_LINK_FREQ_270MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* Link frequency configs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static const struct ov13858_link_freq_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .pixels_per_line = OV13858_PPL_540MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .reg_list = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .num_of_regs = ARRAY_SIZE(mipi_data_rate_1080mbps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .regs = mipi_data_rate_1080mbps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .pixels_per_line = OV13858_PPL_270MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .reg_list = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .num_of_regs = ARRAY_SIZE(mipi_data_rate_540mbps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .regs = mipi_data_rate_540mbps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* Mode configs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static const struct ov13858_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .width = 4224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .height = 3136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .vts_def = OV13858_VTS_30FPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .vts_min = OV13858_VTS_30FPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .reg_list = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .num_of_regs = ARRAY_SIZE(mode_4224x3136_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .regs = mode_4224x3136_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .link_freq_index = OV13858_LINK_FREQ_INDEX_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .width = 2112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .height = 1568,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .vts_def = OV13858_VTS_30FPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .vts_min = 1608,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .reg_list = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .num_of_regs = ARRAY_SIZE(mode_2112x1568_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .regs = mode_2112x1568_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .width = 2112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .height = 1188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .vts_def = OV13858_VTS_30FPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .vts_min = 1608,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .reg_list = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .num_of_regs = ARRAY_SIZE(mode_2112x1188_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .regs = mode_2112x1188_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .width = 1056,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .height = 784,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .vts_def = OV13858_VTS_30FPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .vts_min = 804,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .reg_list = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .num_of_regs = ARRAY_SIZE(mode_1056x784_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .regs = mode_1056x784_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct ov13858 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* V4L2 Controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* Current mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) const struct ov13858_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* Mutex for serialized access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* Streaming on/off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define to_ov13858(_sd) container_of(_sd, struct ov13858, sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) u32 __val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) int buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) u8 buf[6], *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) __be32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) val = cpu_to_be32(__val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) val_p = (u8 *)&val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* Write a list of registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static int ov13858_write_regs(struct ov13858 *ov13858,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) const struct ov13858_reg *regs, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ret = ov13858_write_reg(ov13858, regs[i].address, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dev_err_ratelimited(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) &client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) "Failed to write reg 0x%4.4x. error = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) regs[i].address, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static int ov13858_write_reg_list(struct ov13858 *ov13858,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) const struct ov13858_reg_list *r_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return ov13858_write_regs(ov13858, r_list->regs, r_list->num_of_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* Open sub-device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct ov13858 *ov13858 = to_ov13858(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) fh->pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) mutex_lock(&ov13858->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) try_fmt->width = ov13858->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) try_fmt->height = ov13858->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) mutex_unlock(&ov13858->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) OV13858_REG_VALUE_16BIT, d_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) OV13858_REG_VALUE_16BIT, d_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) OV13858_REG_VALUE_16BIT, d_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) ret = ov13858_read_reg(ov13858, OV13858_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) OV13858_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (pattern) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) val &= OV13858_TEST_PATTERN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) val |= (pattern - 1) | OV13858_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) val &= ~OV13858_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return ov13858_write_reg(ov13858, OV13858_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) OV13858_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct ov13858 *ov13858 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct ov13858, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) max = ov13858->cur_mode->height + ctrl->val - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) __v4l2_ctrl_modify_range(ov13858->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ov13858->exposure->minimum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) max, ov13858->exposure->step, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * Applying V4L2 control value only happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * when power is up for streaming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ret = ov13858_write_reg(ov13858, OV13858_REG_ANALOG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) OV13858_REG_VALUE_16BIT, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) case V4L2_CID_DIGITAL_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ret = ov13858_update_digital_gain(ov13858, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ret = ov13858_write_reg(ov13858, OV13858_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) OV13858_REG_VALUE_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /* Update VTS that meets expected vertical blanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ret = ov13858_write_reg(ov13858, OV13858_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) OV13858_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ov13858->cur_mode->height
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) + ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ret = ov13858_enable_test_pattern(ov13858, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) dev_info(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) "ctrl(id:0x%x,val:0x%x) is not handled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static const struct v4l2_ctrl_ops ov13858_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .s_ctrl = ov13858_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static int ov13858_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* Only one bayer order(GRBG) is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (code->index > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static int ov13858_enum_frame_size(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) fse->max_width = fse->min_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) fse->max_height = fse->min_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static void ov13858_update_pad_format(const struct ov13858_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static int ov13858_do_get_pad_format(struct ov13858 *ov13858,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) struct v4l2_mbus_framefmt *framefmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct v4l2_subdev *sd = &ov13858->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) fmt->format = *framefmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ov13858_update_pad_format(ov13858->cur_mode, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static int ov13858_get_pad_format(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct ov13858 *ov13858 = to_ov13858(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) mutex_lock(&ov13858->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) ret = ov13858_do_get_pad_format(ov13858, cfg, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) mutex_unlock(&ov13858->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ov13858_set_pad_format(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) struct ov13858 *ov13858 = to_ov13858(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) const struct ov13858_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct v4l2_mbus_framefmt *framefmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) s32 vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) s32 vblank_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) s64 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) s64 pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) s64 link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) mutex_lock(&ov13858->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* Only one raw bayer(GRBG) order is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) mode = v4l2_find_nearest_size(supported_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ARRAY_SIZE(supported_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) width, height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) fmt->format.width, fmt->format.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) ov13858_update_pad_format(mode, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) *framefmt = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) ov13858->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) __v4l2_ctrl_s_ctrl(ov13858->link_freq, mode->link_freq_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) link_freq = link_freq_menu_items[mode->link_freq_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) pixel_rate = link_freq_to_pixel_rate(link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) __v4l2_ctrl_s_ctrl_int64(ov13858->pixel_rate, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /* Update limits and set FPS to default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) vblank_def = ov13858->cur_mode->vts_def -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ov13858->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) vblank_min = ov13858->cur_mode->vts_min -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) ov13858->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) __v4l2_ctrl_modify_range(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) ov13858->vblank, vblank_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) OV13858_VTS_MAX - ov13858->cur_mode->height, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) __v4l2_ctrl_s_ctrl(ov13858->vblank, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) h_blank =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) link_freq_configs[mode->link_freq_index].pixels_per_line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) - ov13858->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) __v4l2_ctrl_modify_range(ov13858->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) mutex_unlock(&ov13858->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) *frames = OV13858_NUM_OF_SKIP_FRAMES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) /* Start streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static int ov13858_start_streaming(struct ov13858 *ov13858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) const struct ov13858_reg_list *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) int ret, link_freq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /* Get out of from software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ret = ov13858_write_reg(ov13858, OV13858_REG_SOFTWARE_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) OV13858_REG_VALUE_08BIT, OV13858_SOFTWARE_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) dev_err(&client->dev, "%s failed to set powerup registers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /* Setup PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) link_freq_index = ov13858->cur_mode->link_freq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) reg_list = &link_freq_configs[link_freq_index].reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) ret = ov13858_write_reg_list(ov13858, reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) dev_err(&client->dev, "%s failed to set plls\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* Apply default values of current mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) reg_list = &ov13858->cur_mode->reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ret = ov13858_write_reg_list(ov13858, reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) dev_err(&client->dev, "%s failed to set mode\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /* Apply customized values from user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) ret = __v4l2_ctrl_handler_setup(ov13858->sd.ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) OV13858_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) OV13858_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /* Stop streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static int ov13858_stop_streaming(struct ov13858 *ov13858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) OV13858_REG_VALUE_08BIT, OV13858_MODE_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static int ov13858_set_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) struct ov13858 *ov13858 = to_ov13858(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) mutex_lock(&ov13858->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (ov13858->streaming == enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) mutex_unlock(&ov13858->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) * Apply default & customized values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) * and then start streaming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) ret = ov13858_start_streaming(ov13858);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) goto err_rpm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) ov13858_stop_streaming(ov13858);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) ov13858->streaming = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) mutex_unlock(&ov13858->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) err_rpm_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) mutex_unlock(&ov13858->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static int __maybe_unused ov13858_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) struct ov13858 *ov13858 = to_ov13858(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (ov13858->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) ov13858_stop_streaming(ov13858);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static int __maybe_unused ov13858_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) struct ov13858 *ov13858 = to_ov13858(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if (ov13858->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) ret = ov13858_start_streaming(ov13858);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) ov13858_stop_streaming(ov13858);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) ov13858->streaming = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* Verify chip ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static int ov13858_identify_module(struct ov13858 *ov13858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) ret = ov13858_read_reg(ov13858, OV13858_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) OV13858_REG_VALUE_24BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (val != OV13858_CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) OV13858_CHIP_ID, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) static const struct v4l2_subdev_video_ops ov13858_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .s_stream = ov13858_set_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static const struct v4l2_subdev_pad_ops ov13858_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .enum_mbus_code = ov13858_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .get_fmt = ov13858_get_pad_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .set_fmt = ov13858_set_pad_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .enum_frame_size = ov13858_enum_frame_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .g_skip_frames = ov13858_get_skip_frames,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static const struct v4l2_subdev_ops ov13858_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .video = &ov13858_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .pad = &ov13858_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .sensor = &ov13858_sensor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) static const struct media_entity_operations ov13858_subdev_entity_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .link_validate = v4l2_subdev_link_validate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static const struct v4l2_subdev_internal_ops ov13858_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .open = ov13858_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) /* Initialize control handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) static int ov13858_init_controls(struct ov13858 *ov13858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct v4l2_fwnode_device_properties props;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct v4l2_ctrl_handler *ctrl_hdlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) s64 exposure_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) s64 vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) s64 vblank_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) s64 hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) s64 pixel_rate_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) s64 pixel_rate_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) const struct ov13858_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) ctrl_hdlr = &ov13858->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) mutex_init(&ov13858->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) ctrl_hdlr->lock = &ov13858->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) ov13858->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) &ov13858_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) OV13858_NUM_OF_LINK_FREQS - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (ov13858->link_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) pixel_rate_min = link_freq_to_pixel_rate(link_freq_menu_items[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* By default, PIXEL_RATE is read only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) ov13858->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) pixel_rate_min, pixel_rate_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) 1, pixel_rate_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) mode = ov13858->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) vblank_min = mode->vts_min - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) ov13858->vblank = v4l2_ctrl_new_std(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_VBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) vblank_min, OV13858_VTS_MAX - mode->height, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) hblank = link_freq_configs[mode->link_freq_index].pixels_per_line -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) ov13858->hblank = v4l2_ctrl_new_std(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) hblank, hblank, 1, hblank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (ov13858->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) exposure_max = mode->vts_def - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) ov13858->exposure = v4l2_ctrl_new_std(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) ctrl_hdlr, &ov13858_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) V4L2_CID_EXPOSURE, OV13858_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) exposure_max, OV13858_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) OV13858_EXPOSURE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) OV13858_ANA_GAIN_MIN, OV13858_ANA_GAIN_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) OV13858_ANA_GAIN_STEP, OV13858_ANA_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) /* Digital gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) OV13858_DGTL_GAIN_MIN, OV13858_DGTL_GAIN_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) OV13858_DGTL_GAIN_STEP, OV13858_DGTL_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13858_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) ARRAY_SIZE(ov13858_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) 0, 0, ov13858_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (ctrl_hdlr->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ret = ctrl_hdlr->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) dev_err(&client->dev, "%s control init failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) ret = v4l2_fwnode_device_parse(&client->dev, &props);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov13858_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) &props);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ov13858->sd.ctrl_handler = ctrl_hdlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) v4l2_ctrl_handler_free(ctrl_hdlr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) mutex_destroy(&ov13858->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static void ov13858_free_controls(struct ov13858 *ov13858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) v4l2_ctrl_handler_free(ov13858->sd.ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) mutex_destroy(&ov13858->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) static int ov13858_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) const struct i2c_device_id *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct ov13858 *ov13858;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) device_property_read_u32(&client->dev, "clock-frequency", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (val != 19200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) ov13858 = devm_kzalloc(&client->dev, sizeof(*ov13858), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (!ov13858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* Initialize subdev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) v4l2_i2c_subdev_init(&ov13858->sd, client, &ov13858_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* Check module identity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) ret = ov13858_identify_module(ov13858);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) dev_err(&client->dev, "failed to find sensor: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) /* Set default mode to max resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) ov13858->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) ret = ov13858_init_controls(ov13858);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) /* Initialize subdev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) ov13858->sd.internal_ops = &ov13858_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) ov13858->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) ov13858->sd.entity.ops = &ov13858_subdev_entity_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) ov13858->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) /* Initialize source pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) ov13858->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) ret = media_entity_pads_init(&ov13858->sd.entity, 1, &ov13858->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) goto error_handler_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) ret = v4l2_async_register_subdev_sensor_common(&ov13858->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) goto error_media_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) * Device is already turned on by i2c-core with ACPI domain PM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) * Enable runtime PM and turn off the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) pm_runtime_set_active(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) pm_runtime_enable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) pm_runtime_idle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) error_media_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) media_entity_cleanup(&ov13858->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) error_handler_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) ov13858_free_controls(ov13858);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static int ov13858_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) struct ov13858 *ov13858 = to_ov13858(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) ov13858_free_controls(ov13858);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static const struct i2c_device_id ov13858_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) {"ov13858", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) MODULE_DEVICE_TABLE(i2c, ov13858_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) static const struct dev_pm_ops ov13858_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) SET_SYSTEM_SLEEP_PM_OPS(ov13858_suspend, ov13858_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) static const struct acpi_device_id ov13858_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) {"OVTID858"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) static struct i2c_driver ov13858_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .name = "ov13858",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .pm = &ov13858_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .acpi_match_table = ACPI_PTR(ov13858_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .probe = ov13858_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .remove = ov13858_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .id_table = ov13858_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) module_i2c_driver(ov13858_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) MODULE_AUTHOR("Kan, Chris <chris.kan@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) MODULE_AUTHOR("Rapolu, Chiranjeevi <chiranjeevi.rapolu@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) MODULE_AUTHOR("Yang, Hyungwoo <hyungwoo.yang@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) MODULE_DESCRIPTION("Omnivision ov13858 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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