^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ov13855 camera driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 fix some errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X02 add get_selection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 1. 4224x3136@15fps & 2114x1568@60fps only enable for debug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * 2. fix some regs setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * V0.0X01.0X04 fix power on sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) //#define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OV13855_LINK_FREQ_540MHZ 540000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OV13855_LINK_FREQ_270MHZ 270000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OV13855_PIXEL_RATE (OV13855_LINK_FREQ_540MHZ * 2LL * 4LL / 10LL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OV13855_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CHIP_ID 0x00d855
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OV13855_REG_CHIP_ID 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OV13855_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV13855_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OV13855_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OV13855_REG_EXPOSURE 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OV13855_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OV13855_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OV13855_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV13855_REG_GAIN_H 0x3508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OV13855_REG_GAIN_L 0x3509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OV13855_GAIN_H_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OV13855_GAIN_H_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OV13855_GAIN_L_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OV13855_GAIN_MIN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OV13855_GAIN_MAX 0x7c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OV13855_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OV13855_GAIN_DEFAULT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OV13855_REG_TEST_PATTERN 0x5e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OV13855_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OV13855_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OV13855_REG_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OV13855_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OV13855_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OV13855_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OV13855_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OV13855_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OV13855_CHIP_REVISION_REG 0x302A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OV13855_NAME "ov13855"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OV13855_MEDIA_BUS_FMT MEDIA_BUS_FMT_SBGGR10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const char * const ov13855_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OV13855_NUM_SUPPLIES ARRAY_SIZE(ov13855_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct ov13855_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 link_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct ov13855 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct regulator_bulk_data supplies[OV13855_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct ov13855_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define to_ov13855(sd) container_of(sd, struct ov13855, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct regval ov13855_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x0300, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x0301, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x0302, 0x5a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x0303, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x0304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x0305, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x030b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x030c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x030d, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x0312, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x3022, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x3013, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x3016, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x301b, 0xF0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x301f, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x3106, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x3107, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x3501, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x3502, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x3508, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x3509, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x350a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x350e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3510, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3511, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3512, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3600, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3601, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x3602, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x3612, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3613, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3620, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3621, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3622, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3624, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3640, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3641, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3661, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3662, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3664, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3665, 0xa7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x366e, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x366f, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3674, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3679, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x367f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3680, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3681, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3682, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3683, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3684, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3709, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3714, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x371a, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3737, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3738, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3739, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x373d, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3764, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3765, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x37a1, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x37a8, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x37ab, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x37c2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x37c3, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x37c5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x37d8, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x37d9, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x37da, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x37dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x37e0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x37e1, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x37e2, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x37e3, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x37e4, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x37e5, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x37e6, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3803, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3804, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3805, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3806, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3807, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3808, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x380a, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x380b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x380c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x380d, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x380e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x380f, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3811, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3813, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3815, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3816, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3817, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3820, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3822, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3823, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3826, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3827, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3829, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3832, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x3c80, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3c87, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3c8c, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3c8d, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3c90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3c91, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3c92, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3c93, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3c94, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3c95, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3c96, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x3c97, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3c98, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3d8c, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3d8d, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3f00, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3f03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x4001, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x4008, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x4009, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x4011, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x4050, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x4051, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x4052, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x4053, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x4054, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x4055, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x4056, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x4057, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x4058, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x4059, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x405e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x4500, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x4503, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x450a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x4809, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x480c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x481f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x4833, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x4837, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x4902, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x4d00, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x4d01, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x4d02, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x4d03, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x4d04, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x4d05, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x5000, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x5001, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x5040, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x5041, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x5042, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x5043, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x5044, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x5180, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x5181, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x5182, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x5183, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x5200, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x520b, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x520c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x5300, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x5301, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x5302, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x5303, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x5304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x5305, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x5306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x5307, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x5308, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x5309, 0xa5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x530a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x530b, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x530c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x530d, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x530e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x530f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x5310, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x5311, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x5312, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x5313, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x5314, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x5315, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x5316, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x5317, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x5318, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x5319, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x531a, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x531b, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x531c, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x531d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x5405, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x5406, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x5407, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x5408, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * mipi_datarate per lane 540Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct regval ov13855_2112x1568_60fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x0300, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x0301, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x0302, 0x5a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x0303, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x0304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x0305, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3022, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3013, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x3016, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x301b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x301f, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x3106, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x3107, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x3501, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x3502, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3622, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3624, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3662, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x3709, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3714, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x3737, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x3739, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x37a1, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x37a8, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x37ab, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x37c2, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x37d9, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x37e1, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x37e2, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x37e3, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x37e4, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x37e5, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x37e6, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x3803, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x3804, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x3805, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x3806, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x3807, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x3808, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x3809, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x380a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x380b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x380c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x380d, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x380e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x380f, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x3811, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x3813, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x3814, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3815, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3816, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3817, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3820, 0xab},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x3826, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x3827, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x3829, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x3f03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x4009, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x4011, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x4050, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x4051, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x4500, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x4837, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x4902, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x4d00, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x4d01, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x4d02, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x4d03, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x4d04, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x4d05, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x5000, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x5041, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x5042, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x5043, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x5044, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x5300, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x5301, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x5302, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x5303, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x5305, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x5307, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x5309, 0xa5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x530b, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x5319, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x531a, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x531b, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x531c, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x531d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x5405, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x5406, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x5407, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x5408, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * max_framerate 15fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * mipi_datarate per lane 1080Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static const struct regval ov13855_4224x3136_15fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x0300, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x0301, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x0302, 0x5a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x0303, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x0304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x0305, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x030b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x030c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x030d, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x0312, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x3022, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x3012, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x3013, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x3016, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x301b, 0xF0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x301f, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3106, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x3107, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x3501, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x3502, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x3508, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x3509, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x350a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x350e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x3510, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x3511, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x3512, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x3600, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x3601, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x3602, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x3612, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x3613, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x3620, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x3621, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x3622, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x3624, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x3640, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x3641, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x3660, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x3661, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x3662, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x3664, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x3665, 0xa7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x366e, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x366f, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x3674, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x3679, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x367f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x3680, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x3681, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x3682, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x3683, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x3684, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x3706, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x3709, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x3714, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x371a, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x3737, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x3738, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x3739, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x373d, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x3764, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x3765, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x37a1, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x37a8, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x37ab, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x37c2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x37c3, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x37c5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x37d8, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x37d9, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x37da, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x37dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x37e0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x37e1, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x37e2, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x37e3, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x37e4, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x37e5, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x37e6, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x3803, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x3804, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x3805, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x3806, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x3807, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x3808, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x380a, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x380b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x380c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x380d, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x380e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x380f, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x3811, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x3813, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x3814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x3815, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x3816, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x3817, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x3820, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x3822, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x3823, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x3826, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x3827, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x3829, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x3832, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x3c80, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x3c87, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x3c8c, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x3c8d, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x3c90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x3c91, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x3c92, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x3c93, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x3c94, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x3c95, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x3c96, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x3c97, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x3c98, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x3d8c, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x3d8d, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x3f00, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x3f03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x4001, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x4008, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x4009, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x4011, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x4017, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x4050, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x4051, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x4052, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x4053, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x4054, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {0x4055, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0x4056, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x4057, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x4058, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x4059, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x405e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x4500, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x4503, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x450a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x4800, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x4809, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x480c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x481f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x4833, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x4837, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x4902, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x4d00, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x4d01, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x4d02, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x4d03, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x4d04, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x4d05, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x5000, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x5001, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x5040, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {0x5041, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {0x5042, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {0x5043, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {0x5044, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {0x5180, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {0x5181, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {0x5182, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {0x5183, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {0x5200, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0x520b, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {0x520c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {0x5300, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {0x5301, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {0x5302, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {0x5303, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {0x5304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {0x5305, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {0x5306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {0x5307, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {0x5308, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {0x5309, 0xa5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x530a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x530b, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x530c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x530d, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x530e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {0x530f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {0x5310, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {0x5311, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {0x5312, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {0x5313, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {0x5314, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {0x5315, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {0x5316, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {0x5317, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {0x5318, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {0x5319, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {0x531a, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {0x531b, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {0x531c, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {0x531d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {0x5405, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {0x5406, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {0x5407, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {0x5408, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {0x380c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {0x380d, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {0x0303, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {0x4837, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) //{0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * mipi_datarate per lane 1080Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static const struct regval ov13855_4224x3136_30fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {0x0300, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {0x0301, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {0x0302, 0x5a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {0x0303, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {0x0304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {0x0305, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {0x030b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {0x030c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {0x030d, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {0x0312, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {0x3022, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {0x3012, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {0x3013, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {0x3016, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {0x301b, 0xF0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {0x301f, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {0x3106, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {0x3107, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {0x3501, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {0x3502, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {0x3508, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {0x3509, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {0x350a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {0x350e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {0x3510, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {0x3511, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {0x3512, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {0x3600, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {0x3601, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {0x3602, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {0x3612, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {0x3613, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {0x3620, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {0x3621, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {0x3622, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0x3624, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0x3640, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0x3641, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0x3660, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {0x3661, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {0x3662, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {0x3664, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {0x3665, 0xa7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {0x366e, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {0x366f, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {0x3674, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {0x3679, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {0x367f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {0x3680, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {0x3681, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {0x3682, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0x3683, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {0x3684, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {0x3706, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {0x3709, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {0x3714, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {0x371a, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {0x3737, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {0x3738, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {0x3739, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {0x373d, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {0x3764, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {0x3765, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {0x37a1, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {0x37a8, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {0x37ab, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {0x37c2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {0x37c3, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {0x37c5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {0x37d8, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {0x37d9, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {0x37da, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {0x37dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {0x37e0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {0x37e1, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {0x37e2, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {0x37e3, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {0x37e4, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {0x37e5, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {0x37e6, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {0x3803, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {0x3804, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {0x3805, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {0x3806, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {0x3807, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {0x3808, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {0x380a, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {0x380b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {0x380c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {0x380d, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {0x380e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {0x380f, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {0x3811, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {0x3813, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {0x3814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {0x3815, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {0x3816, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {0x3817, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {0x3820, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {0x3822, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {0x3823, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {0x3826, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {0x3827, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {0x3829, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {0x3832, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {0x3c80, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {0x3c87, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {0x3c8c, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {0x3c8d, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {0x3c90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {0x3c91, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {0x3c92, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {0x3c93, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {0x3c94, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {0x3c95, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {0x3c96, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {0x3c97, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {0x3c98, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {0x3d8c, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {0x3d8d, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {0x3f00, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {0x3f03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {0x4001, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {0x4008, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {0x4009, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {0x4011, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {0x4017, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {0x4050, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {0x4051, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {0x4052, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {0x4053, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {0x4054, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {0x4055, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {0x4056, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {0x4057, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {0x4058, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {0x4059, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {0x405e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {0x4500, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {0x4503, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {0x450a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {0x4800, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {0x4809, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {0x480c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {0x481f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {0x4833, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {0x4837, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {0x4902, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {0x4d00, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {0x4d01, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {0x4d02, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {0x4d03, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {0x4d04, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {0x4d05, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {0x5000, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {0x5001, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {0x5040, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {0x5041, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {0x5042, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {0x5043, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {0x5044, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {0x5180, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {0x5181, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {0x5182, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {0x5183, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {0x5200, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {0x520b, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {0x520c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {0x5300, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {0x5301, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {0x5302, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {0x5303, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {0x5304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {0x5305, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {0x5306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {0x5307, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {0x5308, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {0x5309, 0xa5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {0x530a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {0x530b, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {0x530c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {0x530d, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {0x530e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {0x530f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {0x5310, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {0x5311, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {0x5312, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {0x5313, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {0x5314, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {0x5315, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {0x5316, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {0x5317, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {0x5318, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {0x5319, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {0x531a, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {0x531b, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {0x531c, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {0x531d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {0x5405, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {0x5406, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {0x5407, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {0x5408, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {0x380c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {0x380d, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {0x0303, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {0x4837, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) //{0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static const struct ov13855_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .width = 4224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .height = 3136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .exp_def = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .hts_def = 0x0462,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .vts_def = 0x0c8e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .reg_list = ov13855_4224x3136_30fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .width = 2112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .height = 1568,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .exp_def = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .hts_def = 0x0462,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .vts_def = 0x0c89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .reg_list = ov13855_2112x1568_60fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .link_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .width = 4224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .height = 3136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .denominator = 150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .exp_def = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .hts_def = 0x08c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .vts_def = 0x0c8e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .reg_list = ov13855_4224x3136_15fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static const s64 link_freq_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) OV13855_LINK_FREQ_540MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) OV13855_LINK_FREQ_270MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static const char * const ov13855_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static int ov13855_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static int ov13855_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret = ov13855_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) OV13855_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static int ov13855_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static int ov13855_get_reso_dist(const struct ov13855_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static const struct ov13855_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ov13855_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dist = ov13855_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static int ov13855_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) struct ov13855 *ov13855 = to_ov13855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) const struct ov13855_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) u32 lane_num = OV13855_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) mutex_lock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) mode = ov13855_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) fmt->format.code = OV13855_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) mutex_unlock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ov13855->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) __v4l2_ctrl_modify_range(ov13855->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) __v4l2_ctrl_modify_range(ov13855->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) OV13855_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) __v4l2_ctrl_s_ctrl(ov13855->vblank, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) __v4l2_ctrl_s_ctrl_int64(ov13855->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) __v4l2_ctrl_s_ctrl(ov13855->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) mode->link_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) dev_info(&ov13855->client->dev, "%s: mode->link_freq_idx(%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) __func__, mode->link_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) mutex_unlock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static int ov13855_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct ov13855 *ov13855 = to_ov13855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) const struct ov13855_mode *mode = ov13855->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) mutex_lock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) mutex_unlock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) fmt->format.code = OV13855_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) mutex_unlock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static int ov13855_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) code->code = OV13855_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static int ov13855_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (fse->code != OV13855_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static int ov13855_enable_test_pattern(struct ov13855 *ov13855, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) val = (pattern - 1) | OV13855_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) val = OV13855_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return ov13855_write_reg(ov13855->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) OV13855_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) OV13855_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static int ov13855_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct ov13855 *ov13855 = to_ov13855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) const struct ov13855_mode *mode = ov13855->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) mutex_lock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) mutex_unlock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static void ov13855_get_module_inf(struct ov13855 *ov13855,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) strscpy(inf->base.sensor, OV13855_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) strscpy(inf->base.module, ov13855->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) strscpy(inf->base.lens, ov13855->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static long ov13855_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct ov13855 *ov13855 = to_ov13855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ov13855_get_module_inf(ov13855, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ret = ov13855_write_reg(ov13855->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) OV13855_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) OV13855_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) OV13855_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) ret = ov13855_write_reg(ov13855->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) OV13855_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) OV13855_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) OV13855_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static long ov13855_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ret = ov13855_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) ret = ov13855_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) ret = ov13855_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static int __ov13855_start_stream(struct ov13855 *ov13855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ret = ov13855_write_array(ov13855->client, ov13855->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) mutex_unlock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ret = v4l2_ctrl_handler_setup(&ov13855->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) mutex_lock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) return ov13855_write_reg(ov13855->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) OV13855_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) OV13855_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) OV13855_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static int __ov13855_stop_stream(struct ov13855 *ov13855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return ov13855_write_reg(ov13855->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) OV13855_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) OV13855_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) OV13855_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static int ov13855_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) struct ov13855 *ov13855 = to_ov13855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) struct i2c_client *client = ov13855->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) ov13855->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) ov13855->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) DIV_ROUND_CLOSEST(ov13855->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) ov13855->cur_mode->max_fps.numerator));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) mutex_lock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (on == ov13855->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) ret = __ov13855_start_stream(ov13855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) __ov13855_stop_stream(ov13855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ov13855->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) mutex_unlock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) static int ov13855_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) struct ov13855 *ov13855 = to_ov13855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) struct i2c_client *client = ov13855->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) mutex_lock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (ov13855->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) ret = ov13855_write_array(ov13855->client, ov13855_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) ov13855->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ov13855->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) mutex_unlock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static inline u32 ov13855_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return DIV_ROUND_UP(cycles, OV13855_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) static int __ov13855_power_on(struct ov13855 *ov13855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) struct device *dev = &ov13855->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (!IS_ERR(ov13855->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) gpiod_set_value_cansleep(ov13855->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (!IS_ERR_OR_NULL(ov13855->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) ret = pinctrl_select_state(ov13855->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) ov13855->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) ret = clk_set_rate(ov13855->xvclk, OV13855_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (clk_get_rate(ov13855->xvclk) != OV13855_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) ret = clk_prepare_enable(ov13855->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (!IS_ERR(ov13855->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) gpiod_set_value_cansleep(ov13855->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ret = regulator_bulk_enable(OV13855_NUM_SUPPLIES, ov13855->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (!IS_ERR(ov13855->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) gpiod_set_value_cansleep(ov13855->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (!IS_ERR(ov13855->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) gpiod_set_value_cansleep(ov13855->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) delay_us = ov13855_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) usleep_range(delay_us * 2, delay_us * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) clk_disable_unprepare(ov13855->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static void __ov13855_power_off(struct ov13855 *ov13855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) struct device *dev = &ov13855->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (!IS_ERR(ov13855->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) gpiod_set_value_cansleep(ov13855->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) clk_disable_unprepare(ov13855->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (!IS_ERR(ov13855->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) gpiod_set_value_cansleep(ov13855->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (!IS_ERR_OR_NULL(ov13855->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) ret = pinctrl_select_state(ov13855->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) ov13855->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (!IS_ERR(ov13855->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) gpiod_set_value_cansleep(ov13855->power_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) regulator_bulk_disable(OV13855_NUM_SUPPLIES, ov13855->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static int ov13855_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) struct ov13855 *ov13855 = to_ov13855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) return __ov13855_power_on(ov13855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static int ov13855_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) struct ov13855 *ov13855 = to_ov13855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) __ov13855_power_off(ov13855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static int ov13855_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) struct ov13855 *ov13855 = to_ov13855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) const struct ov13855_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) mutex_lock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) try_fmt->code = OV13855_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) mutex_unlock(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static int ov13855_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (fie->code != OV13855_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static int ov13855_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (2 == OV13855_LANES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) config->flags = V4L2_MBUS_CSI2_2_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) } else if (4 == OV13855_LANES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) config->flags = V4L2_MBUS_CSI2_4_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static int ov13855_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) struct ov13855 *ov13855 = to_ov13855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) sel->r.width = ov13855->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) sel->r.top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) sel->r.height = ov13855->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static const struct dev_pm_ops ov13855_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) SET_RUNTIME_PM_OPS(ov13855_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) ov13855_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) static const struct v4l2_subdev_internal_ops ov13855_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .open = ov13855_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static const struct v4l2_subdev_core_ops ov13855_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .s_power = ov13855_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .ioctl = ov13855_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .compat_ioctl32 = ov13855_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) static const struct v4l2_subdev_video_ops ov13855_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .s_stream = ov13855_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .g_frame_interval = ov13855_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static const struct v4l2_subdev_pad_ops ov13855_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .enum_mbus_code = ov13855_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .enum_frame_size = ov13855_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .enum_frame_interval = ov13855_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .get_fmt = ov13855_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .set_fmt = ov13855_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .get_selection = ov13855_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .get_mbus_config = ov13855_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static const struct v4l2_subdev_ops ov13855_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .core = &ov13855_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .video = &ov13855_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .pad = &ov13855_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) static int ov13855_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct ov13855 *ov13855 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct ov13855, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct i2c_client *client = ov13855->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) max = ov13855->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) __v4l2_ctrl_modify_range(ov13855->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) ov13855->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) ov13855->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ov13855->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) ret = ov13855_write_reg(ov13855->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) OV13855_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) OV13855_REG_VALUE_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) ret = ov13855_write_reg(ov13855->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) OV13855_REG_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) OV13855_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) (ctrl->val >> OV13855_GAIN_H_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) OV13855_GAIN_H_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) ret |= ov13855_write_reg(ov13855->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) OV13855_REG_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) OV13855_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) ctrl->val & OV13855_GAIN_L_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) ret = ov13855_write_reg(ov13855->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) OV13855_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) OV13855_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) ctrl->val + ov13855->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) ret = ov13855_enable_test_pattern(ov13855, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static const struct v4l2_ctrl_ops ov13855_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .s_ctrl = ov13855_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static int ov13855_initialize_controls(struct ov13855 *ov13855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) const struct ov13855_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) u32 lane_num = OV13855_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) handler = &ov13855->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) mode = ov13855->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) handler->lock = &ov13855->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) ov13855->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) 1, 0, link_freq_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) dst_pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) ov13855->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) 0, OV13855_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) __v4l2_ctrl_s_ctrl(ov13855->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) mode->link_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) ov13855->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) if (ov13855->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) ov13855->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) ov13855->vblank = v4l2_ctrl_new_std(handler, &ov13855_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) OV13855_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) ov13855->exposure = v4l2_ctrl_new_std(handler, &ov13855_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) V4L2_CID_EXPOSURE, OV13855_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) exposure_max, OV13855_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) ov13855->anal_gain = v4l2_ctrl_new_std(handler, &ov13855_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) V4L2_CID_ANALOGUE_GAIN, OV13855_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) OV13855_GAIN_MAX, OV13855_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) OV13855_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) ov13855->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) &ov13855_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) ARRAY_SIZE(ov13855_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) 0, 0, ov13855_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) dev_err(&ov13855->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) ov13855->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) static int ov13855_check_sensor_id(struct ov13855 *ov13855,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) struct device *dev = &ov13855->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) ret = ov13855_read_reg(client, OV13855_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) OV13855_REG_VALUE_24BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) ret = ov13855_read_reg(client, OV13855_CHIP_REVISION_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) OV13855_REG_VALUE_08BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) dev_err(dev, "Read chip revision register error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) dev_info(dev, "Detected OV%06x sensor, REVISION 0x%x\n", CHIP_ID, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) static int ov13855_configure_regulators(struct ov13855 *ov13855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) for (i = 0; i < OV13855_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) ov13855->supplies[i].supply = ov13855_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) return devm_regulator_bulk_get(&ov13855->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) OV13855_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) ov13855->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) static int ov13855_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) struct ov13855 *ov13855;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) ov13855 = devm_kzalloc(dev, sizeof(*ov13855), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (!ov13855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) &ov13855->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) &ov13855->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) &ov13855->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) &ov13855->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) ov13855->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ov13855->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) ov13855->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) if (IS_ERR(ov13855->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) ov13855->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (IS_ERR(ov13855->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) ov13855->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (IS_ERR(ov13855->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) ov13855->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (IS_ERR(ov13855->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) ret = ov13855_configure_regulators(ov13855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) ov13855->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (!IS_ERR(ov13855->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ov13855->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) pinctrl_lookup_state(ov13855->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) if (IS_ERR(ov13855->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) ov13855->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) pinctrl_lookup_state(ov13855->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if (IS_ERR(ov13855->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) mutex_init(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) sd = &ov13855->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) v4l2_i2c_subdev_init(sd, client, &ov13855_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) ret = ov13855_initialize_controls(ov13855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) ret = __ov13855_power_on(ov13855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) ret = ov13855_check_sensor_id(ov13855, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) sd->internal_ops = &ov13855_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) ov13855->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) ret = media_entity_pads_init(&sd->entity, 1, &ov13855->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) if (strcmp(ov13855->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) ov13855->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) OV13855_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) __ov13855_power_off(ov13855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) v4l2_ctrl_handler_free(&ov13855->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) mutex_destroy(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) static int ov13855_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) struct ov13855 *ov13855 = to_ov13855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) v4l2_ctrl_handler_free(&ov13855->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) mutex_destroy(&ov13855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) __ov13855_power_off(ov13855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) static const struct of_device_id ov13855_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) { .compatible = "ovti,ov13855" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) MODULE_DEVICE_TABLE(of, ov13855_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) static const struct i2c_device_id ov13855_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) { "ovti,ov13855", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) static struct i2c_driver ov13855_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .name = OV13855_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .pm = &ov13855_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .of_match_table = of_match_ptr(ov13855_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .probe = &ov13855_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .remove = &ov13855_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .id_table = ov13855_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) return i2c_add_driver(&ov13855_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) i2c_del_driver(&ov13855_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) MODULE_DESCRIPTION("OmniVision ov13855 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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