^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ov13850 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X05 add function g_mbus_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OV13850_LINK_FREQ_300MHZ 300000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OV13850_PIXEL_RATE (OV13850_LINK_FREQ_300MHZ * 2 * 2 / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OV13850_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CHIP_ID 0x00d850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OV13850_REG_CHIP_ID 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OV13850_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OV13850_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OV13850_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OV13850_REG_EXPOSURE 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV13850_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OV13850_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OV13850_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OV13850_REG_GAIN_H 0x350a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OV13850_REG_GAIN_L 0x350b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OV13850_GAIN_H_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV13850_GAIN_H_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV13850_GAIN_L_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OV13850_GAIN_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OV13850_GAIN_MAX 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OV13850_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OV13850_GAIN_DEFAULT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OV13850_REG_TEST_PATTERN 0x5e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OV13850_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OV13850_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OV13850_REG_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OV13850_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OV13850_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OV13850_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OV13850_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OV13850_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OV13850_CHIP_REVISION_REG 0x302A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OV13850_R1A 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OV13850_R2A 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OV13850_NAME "ov13850"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct regval *ov13850_global_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const char * const ov13850_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OV13850_NUM_SUPPLIES ARRAY_SIZE(ov13850_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct ov13850_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct ov13850 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct regulator_bulk_data supplies[OV13850_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const struct ov13850_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define to_ov13850(sd) container_of(sd, struct ov13850, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct regval ov13850_global_regs_r1a[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x0300, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x0301, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x0302, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x0303, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x030a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x300f, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x3010, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x3011, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x3012, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x3013, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x3014, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x3015, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x301f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x3106, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x3210, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x3501, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x3502, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x3506, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x3507, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x3508, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x350a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x350b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x350e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x350f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x3600, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x3601, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x3602, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x3603, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3604, 0xa5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3605, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3607, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x360a, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x360b, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x360c, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x360f, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3611, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3612, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3613, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3615, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3641, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3660, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3668, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3669, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3667, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3702, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3703, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3704, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3705, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3706, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3707, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3708, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3709, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x370a, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x370b, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3720, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3722, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3728, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x372a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x372f, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3710, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3716, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3718, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3719, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x371c, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3760, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3761, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3767, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3768, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3769, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x376c, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3d84, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3d85, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3d8c, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3d8d, 0xbf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3801, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3803, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3804, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3805, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3806, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3807, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3808, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3809, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x380a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x380b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x380c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x380d, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x380e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x380f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3810, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3811, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3813, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3814, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3815, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3820, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3821, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3834, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3835, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3836, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3837, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x4000, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x4001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x400b, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x4011, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x401a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x401b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x401c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x401d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x4020, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x4021, 0xE4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x4022, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x4023, 0x5F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x4024, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x4025, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x4026, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x4027, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x4028, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x4029, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x402a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x402b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x402c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x402d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x402e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x402f, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x403d, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x403f, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x4500, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x4501, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x4601, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x4602, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x4603, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x4800, 0x24}, //MIPI CLK control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x4837, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x4d00, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x4d01, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x4d02, 0xd1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x4d03, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x4d04, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x4d05, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x5000, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x5001, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x5002, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x5013, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x501c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x501d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x5242, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x5243, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x5244, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x5245, 0xf9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x5246, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x5247, 0xf6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x5248, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x5249, 0xa6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x5300, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x5301, 0xdf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x5302, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x5303, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x5304, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x5305, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x5306, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x5307, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x5308, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x5309, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x530a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x530b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x530c, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x530d, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x530e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x530f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x5310, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x5400, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x5401, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x5402, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x5403, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x5404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x5405, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x540c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x5b00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x5b01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x5b02, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x5b03, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x5b04, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x5b05, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x5b09, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x5e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x5e10, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x0102, 0x01}, //Fast standby enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct regval ov13850_global_regs_r2a[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x0300, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x0301, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x0302, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x0303, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x030a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x300f, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x3010, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x3011, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x3012, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x3013, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x3014, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x301f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x3106, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x3210, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3501, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3502, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3506, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3507, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x3508, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x350a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x350b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x350e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x350f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x351a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x351b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x351c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x351d, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x351e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x351f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x3520, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x3521, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x3600, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x3601, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x3602, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x3603, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x3604, 0xb1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3605, 0xb5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3606, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3607, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x3609, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x360a, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x360b, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x360c, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x360f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x3611, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x3612, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x3613, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x3615, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x3616, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x3641, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x3660, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x3668, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x3669, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x366a, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x3667, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x3702, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x3703, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x3704, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x3705, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x3706, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x3707, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x3708, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x3709, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x370a, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x370b, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x3720, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3722, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x3728, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x372a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x372b, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x372e, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x372f, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3730, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x3731, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x3732, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3733, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3710, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3716, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3718, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3719, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x371a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x371c, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x3748, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x3760, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x3761, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x3762, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x3763, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x3767, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x3768, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3769, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x376c, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x376f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x3773, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x3d84, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x3d85, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x3d8c, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x3d8d, 0xbf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x3801, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x3803, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x3804, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x3805, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x3806, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x3807, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x3808, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x3809, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x380a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x380b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x380c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x380d, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x380e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x380f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x3810, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x3811, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x3812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x3813, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x3814, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x3815, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x3820, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x3821, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x3823, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x3826, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x3827, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x3834, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x3835, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x3836, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3837, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x4000, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x4001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x4006, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x4007, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x400b, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x4011, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x401a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x401b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x401c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x401d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x4020, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x4021, 0xe4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x4022, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x4023, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x4024, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x4025, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x4026, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x4027, 0xbf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x4028, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x4029, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x402a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x402b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x402c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x402d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x402e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x402f, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x403d, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x403f, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x4041, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x4500, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x4501, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x458b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x459c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x459d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x459e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x4601, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x4602, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x4603, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x4800, 0x24}, //MIPI CLK control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x4837, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x4d00, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x4d01, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x4d02, 0xd1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x4d03, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x4d04, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x4d05, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x4d0b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x5000, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x5001, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x5002, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x5013, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x501c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x501d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x510f, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x5110, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x5111, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x536d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x536e, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x536f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x5370, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x5400, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x5400, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x5401, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x5402, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x5403, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x5404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x5405, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x540c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x5501, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x5b00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x5b01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x5b02, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x5b03, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x5b04, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x5b05, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x5b09, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x5e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x5e10, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x0102, 0x01}, //Fast standby enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * mipi_datarate per lane 600Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const struct regval ov13850_2112x1568_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x3612, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x370a, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x372a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x372f, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x3801, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x3805, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x3807, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x3808, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x3809, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x380a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x380b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x380c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x380d, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x380e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x380f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x3813, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x3814, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x3815, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x3820, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x3821, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x3836, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x3837, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x4601, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x4603, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x4020, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x4021, 0xE4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x4022, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x4023, 0x5F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x4024, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x4025, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x4026, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x4027, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x4603, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x5401, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x5405, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * max_framerate 7fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * mipi_datarate per lane 600Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static const struct regval ov13850_4224x3136_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x3612, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x370a, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x372a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x372f, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x3801, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x3805, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x3807, 0x4B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x3808, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0x380a, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x380b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x380e, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x380f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x3813, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x3814, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x3815, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x3820, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x3821, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x3836, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x3837, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x4601, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x4603, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x4020, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x4021, 0x4C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x4022, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x4023, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x4024, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x4025, 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x4026, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x4027, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x4603, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x5401, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x5405, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const struct ov13850_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .width = 4224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .height = 3136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .numerator = 20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .denominator = 150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .exp_def = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .hts_def = 0x12c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .vts_def = 0x0d00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .reg_list = ov13850_4224x3136_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .width = 2112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .height = 1568,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .exp_def = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .hts_def = 0x12c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .vts_def = 0x0680,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .reg_list = ov13850_2112x1568_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) OV13850_LINK_FREQ_300MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static const char * const ov13850_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static int ov13850_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int ov13850_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ret = ov13850_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) OV13850_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static int ov13850_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static int ov13850_get_reso_dist(const struct ov13850_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static const struct ov13850_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ov13850_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dist = ov13850_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int ov13850_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct ov13850 *ov13850 = to_ov13850(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) const struct ov13850_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) mutex_lock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) mode = ov13850_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) mutex_unlock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ov13850->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) __v4l2_ctrl_modify_range(ov13850->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) __v4l2_ctrl_modify_range(ov13850->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) OV13850_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) mutex_unlock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int ov13850_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct ov13850 *ov13850 = to_ov13850(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) const struct ov13850_mode *mode = ov13850->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) mutex_lock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) mutex_unlock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) mutex_unlock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int ov13850_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static int ov13850_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static int ov13850_enable_test_pattern(struct ov13850 *ov13850, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) val = (pattern - 1) | OV13850_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) val = OV13850_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return ov13850_write_reg(ov13850->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) OV13850_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) OV13850_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static int ov13850_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct ov13850 *ov13850 = to_ov13850(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) const struct ov13850_mode *mode = ov13850->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) mutex_lock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) mutex_unlock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static void ov13850_get_module_inf(struct ov13850 *ov13850,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) strlcpy(inf->base.sensor, OV13850_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) strlcpy(inf->base.module, ov13850->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) strlcpy(inf->base.lens, ov13850->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static long ov13850_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct ov13850 *ov13850 = to_ov13850(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ov13850_get_module_inf(ov13850, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ret = ov13850_write_reg(ov13850->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) OV13850_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) OV13850_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) OV13850_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ret = ov13850_write_reg(ov13850->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) OV13850_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) OV13850_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) OV13850_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static long ov13850_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ret = ov13850_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ret = ov13850_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ret = ov13850_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static int __ov13850_start_stream(struct ov13850 *ov13850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ret = ov13850_write_array(ov13850->client, ov13850->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) mutex_unlock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ret = v4l2_ctrl_handler_setup(&ov13850->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) mutex_lock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return ov13850_write_reg(ov13850->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) OV13850_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) OV13850_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) OV13850_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static int __ov13850_stop_stream(struct ov13850 *ov13850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return ov13850_write_reg(ov13850->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) OV13850_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) OV13850_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) OV13850_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static int ov13850_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct ov13850 *ov13850 = to_ov13850(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct i2c_client *client = ov13850->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) mutex_lock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (on == ov13850->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret = __ov13850_start_stream(ov13850);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) __ov13850_stop_stream(ov13850);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ov13850->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) mutex_unlock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static int ov13850_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct ov13850 *ov13850 = to_ov13850(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct i2c_client *client = ov13850->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) mutex_lock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (ov13850->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) ret = ov13850_write_array(ov13850->client, ov13850_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ov13850->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ov13850->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) mutex_unlock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static inline u32 ov13850_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return DIV_ROUND_UP(cycles, OV13850_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static int __ov13850_power_on(struct ov13850 *ov13850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct device *dev = &ov13850->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (!IS_ERR(ov13850->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) gpiod_set_value_cansleep(ov13850->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (!IS_ERR_OR_NULL(ov13850->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ret = pinctrl_select_state(ov13850->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ov13850->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret = clk_set_rate(ov13850->xvclk, OV13850_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (clk_get_rate(ov13850->xvclk) != OV13850_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ret = clk_prepare_enable(ov13850->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (!IS_ERR(ov13850->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) gpiod_set_value_cansleep(ov13850->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) ret = regulator_bulk_enable(OV13850_NUM_SUPPLIES, ov13850->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (!IS_ERR(ov13850->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) gpiod_set_value_cansleep(ov13850->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (!IS_ERR(ov13850->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) gpiod_set_value_cansleep(ov13850->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) delay_us = ov13850_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) clk_disable_unprepare(ov13850->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static void __ov13850_power_off(struct ov13850 *ov13850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct device *dev = &ov13850->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (!IS_ERR(ov13850->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) gpiod_set_value_cansleep(ov13850->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) clk_disable_unprepare(ov13850->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (!IS_ERR(ov13850->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) gpiod_set_value_cansleep(ov13850->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (!IS_ERR_OR_NULL(ov13850->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ret = pinctrl_select_state(ov13850->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ov13850->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (!IS_ERR(ov13850->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) gpiod_set_value_cansleep(ov13850->power_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) regulator_bulk_disable(OV13850_NUM_SUPPLIES, ov13850->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static int ov13850_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct ov13850 *ov13850 = to_ov13850(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return __ov13850_power_on(ov13850);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static int ov13850_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct ov13850 *ov13850 = to_ov13850(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) __ov13850_power_off(ov13850);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static int ov13850_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) struct ov13850 *ov13850 = to_ov13850(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) const struct ov13850_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) mutex_lock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) mutex_unlock(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static int ov13850_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static int ov13850_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) val = 1 << (OV13850_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static const struct dev_pm_ops ov13850_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) SET_RUNTIME_PM_OPS(ov13850_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ov13850_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static const struct v4l2_subdev_internal_ops ov13850_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .open = ov13850_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static const struct v4l2_subdev_core_ops ov13850_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .s_power = ov13850_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .ioctl = ov13850_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .compat_ioctl32 = ov13850_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static const struct v4l2_subdev_video_ops ov13850_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .s_stream = ov13850_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .g_frame_interval = ov13850_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static const struct v4l2_subdev_pad_ops ov13850_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .enum_mbus_code = ov13850_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .enum_frame_size = ov13850_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .enum_frame_interval = ov13850_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .get_fmt = ov13850_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .set_fmt = ov13850_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .get_mbus_config = ov13850_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static const struct v4l2_subdev_ops ov13850_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .core = &ov13850_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .video = &ov13850_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .pad = &ov13850_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static int ov13850_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct ov13850 *ov13850 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct ov13850, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct i2c_client *client = ov13850->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) max = ov13850->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) __v4l2_ctrl_modify_range(ov13850->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ov13850->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ov13850->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) ov13850->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ret = ov13850_write_reg(ov13850->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) OV13850_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) OV13850_REG_VALUE_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ret = ov13850_write_reg(ov13850->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) OV13850_REG_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) OV13850_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) (ctrl->val >> OV13850_GAIN_H_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) OV13850_GAIN_H_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ret |= ov13850_write_reg(ov13850->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) OV13850_REG_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) OV13850_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ctrl->val & OV13850_GAIN_L_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ret = ov13850_write_reg(ov13850->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) OV13850_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) OV13850_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ctrl->val + ov13850->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) ret = ov13850_enable_test_pattern(ov13850, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static const struct v4l2_ctrl_ops ov13850_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .s_ctrl = ov13850_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static int ov13850_initialize_controls(struct ov13850 *ov13850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) const struct ov13850_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) handler = &ov13850->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) mode = ov13850->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) handler->lock = &ov13850->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) 0, OV13850_PIXEL_RATE, 1, OV13850_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ov13850->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (ov13850->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ov13850->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ov13850->vblank = v4l2_ctrl_new_std(handler, &ov13850_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) OV13850_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ov13850->exposure = v4l2_ctrl_new_std(handler, &ov13850_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) V4L2_CID_EXPOSURE, OV13850_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) exposure_max, OV13850_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) ov13850->anal_gain = v4l2_ctrl_new_std(handler, &ov13850_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) V4L2_CID_ANALOGUE_GAIN, OV13850_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) OV13850_GAIN_MAX, OV13850_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) OV13850_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ov13850->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) &ov13850_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) ARRAY_SIZE(ov13850_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) 0, 0, ov13850_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) dev_err(&ov13850->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) ov13850->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static int ov13850_check_sensor_id(struct ov13850 *ov13850,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) struct device *dev = &ov13850->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) ret = ov13850_read_reg(client, OV13850_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) OV13850_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ret = ov13850_read_reg(client, OV13850_CHIP_REVISION_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) OV13850_REG_VALUE_08BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) dev_err(dev, "Read chip revision register error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (id == OV13850_R2A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) ov13850_global_regs = ov13850_global_regs_r2a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) ov13850_global_regs = ov13850_global_regs_r1a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) dev_info(dev, "Detected OV%06x sensor, REVISION 0x%x\n", CHIP_ID, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static int ov13850_configure_regulators(struct ov13850 *ov13850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) for (i = 0; i < OV13850_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) ov13850->supplies[i].supply = ov13850_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) return devm_regulator_bulk_get(&ov13850->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) OV13850_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ov13850->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static int ov13850_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) struct ov13850 *ov13850;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) ov13850 = devm_kzalloc(dev, sizeof(*ov13850), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (!ov13850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) &ov13850->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) &ov13850->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) &ov13850->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) &ov13850->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) ov13850->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) ov13850->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) ov13850->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (IS_ERR(ov13850->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) ov13850->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (IS_ERR(ov13850->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) ov13850->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (IS_ERR(ov13850->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ov13850->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (IS_ERR(ov13850->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) ret = ov13850_configure_regulators(ov13850);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) ov13850->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (!IS_ERR(ov13850->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) ov13850->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) pinctrl_lookup_state(ov13850->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (IS_ERR(ov13850->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) ov13850->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) pinctrl_lookup_state(ov13850->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (IS_ERR(ov13850->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) mutex_init(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) sd = &ov13850->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) v4l2_i2c_subdev_init(sd, client, &ov13850_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ret = ov13850_initialize_controls(ov13850);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) ret = __ov13850_power_on(ov13850);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) ret = ov13850_check_sensor_id(ov13850, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) sd->internal_ops = &ov13850_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) ov13850->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) ret = media_entity_pads_init(&sd->entity, 1, &ov13850->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (strcmp(ov13850->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) ov13850->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) OV13850_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) __ov13850_power_off(ov13850);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) v4l2_ctrl_handler_free(&ov13850->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) mutex_destroy(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) static int ov13850_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct ov13850 *ov13850 = to_ov13850(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) v4l2_ctrl_handler_free(&ov13850->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) mutex_destroy(&ov13850->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) __ov13850_power_off(ov13850);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) static const struct of_device_id ov13850_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) { .compatible = "ovti,ov13850" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) MODULE_DEVICE_TABLE(of, ov13850_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static const struct i2c_device_id ov13850_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) { "ovti,ov13850", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static struct i2c_driver ov13850_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .name = OV13850_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .pm = &ov13850_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .of_match_table = of_match_ptr(ov13850_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .probe = &ov13850_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .remove = &ov13850_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .id_table = ov13850_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) return i2c_add_driver(&ov13850_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) i2c_del_driver(&ov13850_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) MODULE_DESCRIPTION("OmniVision ov13850 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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