^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ov12d2q driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "../platform/rockchip/isp/rkisp_tb_helper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OV12D2Q_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OV12D2Q_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MIPI_FREQ_625M 625000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PIXEL_RATE_WITH_625M (MIPI_FREQ_625M * 2 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) OV12D2Q_LANES / OV12D2Q_BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OV12D2Q_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CHIP_ID 0x561441
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OV12D2Q_REG_CHIP_ID 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OV12D2Q_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OV12D2Q_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV12D2Q_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OV12D2Q_EXPOSURE_MIN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OV12D2Q_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OV12D2Q_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OV12D2Q_GAIN_MIN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV12D2Q_GAIN_MAX 0x3df61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV12D2Q_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OV12D2Q_GAIN_DEFAULT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OV12D2Q_REG_AGAIN_L 0x3508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OV12D2Q_REG_AGAIN_M 0x3548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OV12D2Q_REG_AGAIN_S 0x3588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OV12D2Q_REG_DGAIN_L_H_B 0x350A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OV12D2Q_REG_DGAIN_L_H_GB 0x3510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OV12D2Q_REG_DGAIN_L_H_GR 0x3513
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OV12D2Q_REG_DGAIN_L_H_R 0x3516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OV12D2Q_REG_DGAIN_M_H_B 0x354A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OV12D2Q_REG_DGAIN_S_H_B 0x358A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OV12D2Q_REG_DGAIN_S_H_GB 0x3590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OV12D2Q_REG_DGAIN_S_H_GR 0x3593
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OV12D2Q_REG_DGAIN_S_H_R 0x3596
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OV12D2Q_REG_EXP_L_H 0x3501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OV12D2Q_REG_EXP_M_H 0x3541
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OV12D2Q_REG_EXP_S_H 0x3581
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OV12D2Q_SOFTWARE_RESET_REG 0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OV12D2Q_REG_ISP_X_WIN 0x3810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OV12D2Q_REG_ISP_Y_WIN 0x3812
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OV12D2Q_GROUP_UPDATE_ADDRESS 0x3208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OV12D2Q_GROUP_UPDATE_START_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OV12D2Q_GROUP_UPDATE_END_DATA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OV12D2Q_GROUP_UPDATE_LAUNCH 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OV12D2Q_REG_TEST_PATTERN 0x5081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OV12D2Q_TEST_PATTERN_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OV12D2Q_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OV12D2Q_REG_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OV12D2Q_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OV12D2Q_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OV12D2Q_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OV12D2Q_NAME "ov12d2q"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const char * const ov12d2q_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OV12D2Q_NUM_SUPPLIES ARRAY_SIZE(ov12d2q_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OV12D2Q_FLIP_REG 0x3820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OV12D2Q_MIRROR_REG 0x3821
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MIRROR_BIT_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define FLIP_BIT_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct ov12d2q_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct ov12d2q {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct regulator_bulk_data supplies[OV12D2Q_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct v4l2_ctrl *h_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct v4l2_ctrl *v_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) const struct ov12d2q_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bool is_thunderboot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bool is_thunderboot_ng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bool is_first_streamoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define to_ov12d2q(sd) container_of(sd, struct ov12d2q, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct regval ov12d2q_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * max_framerate 60fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct regval ov12d2q_2256x1256_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x0301, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x0302, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x0303, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x0304, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x0305, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x0306, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x0307, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x0309, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x0320, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x0323, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x0324, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x0325, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x0326, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x032b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x0343, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x0344, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x0345, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x0346, 0xcb},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3016, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3017, 0xd0},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3019, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x301a, 0xf0},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x382a, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x382c, 0x00},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x3835, 0x00},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x3837, 0x08},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x383b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x383c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x383d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x383e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x383f, 0x33},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x3859, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x3865, 0x70},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x3904, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x3907, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x390a, 0x9a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3914, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3938, 0x4b},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x393b, 0x4b},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x3975, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x3979, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x397d, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x3981, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x3983, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x3985, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x3986, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x398a, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x39cd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x39ce, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x39cf, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x39d0, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x39d1, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x39d2, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x39d3, 0x94},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x39d5, 0x79},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x3a12, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x3a13, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x3a14, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x3a15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x3a16, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x3a18, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x3a1a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x3a1c, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x3a1e, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x3a1f, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x3a22, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x3a24, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x3a25, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x3a26, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3a27, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x3a2a, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x3a2b, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x3a36, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x3d84, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x3d85, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x3d88, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x3d89, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x3d8a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x3d8b, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x3d8c, 0xa3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x3d8d, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x3da4, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x3daa, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x3dab, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x3dac, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x3dad, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x3dae, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x3daf, 0xb3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3e00, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x3e01, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x3e02, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x3e03, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x3e04, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x3e05, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x3e06, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x3e07, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x3e09, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x3e0b, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x3e0d, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x3e0f, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x3e11, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x3e13, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x3e15, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x3e17, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x3e18, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x3e19, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x3e1a, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x3e1b, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x3e1c, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x3e1d, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x3e1e, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x3e1f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x3e20, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x3e21, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x3e22, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x3e23, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x3e24, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x3e25, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x3e26, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x3e27, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x3e28, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x3e29, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x3e2a, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x3e2b, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x3e2c, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x3e2d, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x3e30, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x3e3a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x3e3b, 0xdf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x3e3c, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x3e3d, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x3e3e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x3e3f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x3e40, 0xc1},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x3e43, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x3e44, 0x54},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x3f00, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x3f01, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x3f03, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x4002, 0xf3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x4009, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x400e, 0xc6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x400f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x4010, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x4011, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x4012, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x4015, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x4016, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x4017, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x4018, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x401a, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x401e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x401f, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x4020, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x4021, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x4022, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x4023, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x4024, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x4025, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x4026, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x4027, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x4028, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x4030, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x4031, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x4032, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x4033, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x4034, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x4035, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x4036, 0x08},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x4040, 0x08},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x4044, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x4045, 0x10},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x4047, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x4050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x4051, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x4056, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x4102, 0xf3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x4109, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x410e, 0xc6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x410f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x4110, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x4111, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x4112, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x4115, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x4116, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x4117, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x4118, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x411a, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x411e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x411f, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x4128, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x4156, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x4702, 0xf3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x4709, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x470e, 0xc6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x470f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x4710, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x4711, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x4712, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x4715, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x4716, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x4717, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x4718, 0x07},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {0x557e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {0x557f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {0x5580, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {0x5581, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {0x5582, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {0x5583, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {0x5681, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {0x56c4, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {0x575a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {0x575b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {0x575c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {0x575d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {0x575e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {0x575f, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {0x5760, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {0x5761, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {0x5780, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {0x5781, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {0x5782, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {0x5783, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {0x5784, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {0x5785, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {0x5786, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {0x5787, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {0x5788, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {0x5789, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {0x578a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {0x578b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {0x578d, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {0x5793, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {0x57d2, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {0x57da, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {0x57db, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {0x5850, 0xec},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {0x5851, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {0x5852, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {0x5854, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {0x5855, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {0x5856, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {0x5857, 0xca},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {0x5858, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {0x5859, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {0x585a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {0x585b, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {0x585e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {0x585f, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {0x5860, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {0x5861, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {0x5862, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {0x5863, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {0x5864, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {0x5865, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {0x5866, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {0x5867, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {0x5868, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {0x5869, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {0x586a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {0x586b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {0x586c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {0x586d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {0x586e, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {0x586f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {0x587c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {0x587d, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {0x587e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {0x587f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {0x5880, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {0x5881, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {0x5882, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {0x5883, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {0x5f06, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {0x5f07, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {0x5f08, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {0x5f09, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {0x5f0a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {0x5f0b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {0x5f0c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {0x5f0d, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {0x5f0e, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {0x5f0f, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {0x5f10, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {0x5f11, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {0x5f18, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {0x5f19, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {0x5f1a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {0x5f1b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {0x5f1d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {0x5f1f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {0x5f20, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {0x5f21, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {0x5f22, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {0x5f23, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {0x5f25, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {0x5f2a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {0x5f2b, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {0x6600, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {0x6601, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {0x6602, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {0x6603, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {0x6960, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {0x69a2, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {0x69a3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {0x69a6, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {0x69a7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {0x69aa, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {0x69ab, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {0x69ae, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {0x69af, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {0x69b2, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {0x69b3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {0x69b6, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {0x69b7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {0x69ba, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {0x69bb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {0x69be, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {0x69bf, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {0x6a24, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {0x6a25, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {0x6a2a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {0x6a2b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {0x6a61, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {0x6a64, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {0x6a65, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {0x6a6a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {0x6a6b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {0x6a23, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {0x6a27, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {0x6a63, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {0x6a67, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {0x69a1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {0x69a5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {0x69a9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {0x69ad, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {0x69b1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {0x69b5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {0x69b9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {0x69bd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {0xfff4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {0xfff6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {0x0361, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {0x3644, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {0x5000, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {0x5001, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {0x50d4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {0x5171, 0xbe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {0x3222, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {0x3208, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {0x3938, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {0x393b, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {0x3208, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {0x3208, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {0x3938, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {0x393b, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {0x3208, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {0x3208, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {0x3938, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {0x393b, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {0x3208, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {0x3208, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {0x3938, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {0x393b, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {0x3208, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {0x5000, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {0x5001, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static const struct regval ov12d2q_4512x2512_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {0x0301, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {0x0302, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {0x0303, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {0x0304, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {0x0305, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {0x0306, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {0x0307, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {0x0309, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {0x0320, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {0x0323, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {0x0324, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {0x0325, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {0x0326, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {0x032b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {0x0343, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {0x0344, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {0x0345, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {0x0346, 0xcb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {0x0350, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {0x0360, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {0x3002, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {0x300d, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {0x300e, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {0x3012, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {0x3016, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {0x3017, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {0x3018, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {0x3019, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {0x301a, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {0x301b, 0x34},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {0x382a, 0x83},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {0x383b, 0x00},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {0x3907, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {0x390a, 0x9a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {0x3914, 0x34},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {0x3975, 0x05},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {0x397d, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) {0x3981, 0x15},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) {0x398a, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) {0x39cd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {0x39ce, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {0x39cf, 0x40},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {0x39d1, 0x50},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {0x3a1e, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {0x3a1f, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {0x3a22, 0x12},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {0x3a25, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {0x3a26, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {0x3a27, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {0x3a2a, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {0x3a2b, 0xa8},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {0x3d8a, 0x03},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {0x3d8c, 0xa3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {0x3d8d, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {0x3da4, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) {0x3daa, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {0x3dab, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {0x3dac, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {0x3dad, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {0x3dae, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) {0x3daf, 0xb3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {0x3e00, 0x0e},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {0x3e28, 0x07},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) {0x3e3c, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {0x3e3d, 0x44},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {0x3f03, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) {0x4002, 0xf3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) {0x4009, 0x02},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) {0x4109, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) {0x410e, 0xc6},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {0x4110, 0x28},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {0x4112, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) {0x4115, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) {0x4116, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) {0x4117, 0x00},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) {0x411a, 0x40},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {0x4128, 0x01},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) {0x4702, 0xf3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) {0x4709, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) {0x470e, 0xc6},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) {0x4710, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) {0x4711, 0x01},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) {0x52c0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) {0x52c1, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) {0x52c2, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) {0x52c3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) {0x52c4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) {0x52c5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) {0x52c6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) {0x52c7, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) {0x52c8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) {0x52c9, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) {0x52ca, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) {0x52cb, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) {0x52cc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) {0x52cd, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) {0x52ce, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) {0x52cf, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) {0x5f00, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) {0x5f2d, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) {0x5f2e, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) {0x52f0, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) {0x52f1, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) {0x52f2, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) {0x52f3, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) {0x52f4, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) {0x52f5, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) {0x52f6, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) {0x52f7, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) {0x52f8, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) {0x52f9, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) {0x52fa, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) {0x52fb, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) {0x52fc, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) {0x52fd, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) {0x52fe, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) {0x52ff, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) {0x5300, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) {0x5301, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) {0x5302, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) {0x5303, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) {0x5304, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) {0x5305, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) {0x5306, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) {0x5307, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) {0x5308, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) {0x5309, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) {0x530a, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) {0x530b, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) {0x530c, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) {0x530d, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) {0x530e, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) {0x530f, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) {0x5353, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) {0x5354, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) {0x5355, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) {0x5356, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) {0x5357, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) {0x5358, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) {0x5359, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) {0x535a, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) {0x535b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) {0x5990, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) {0x5991, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) {0x5992, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) {0x5993, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) {0x5994, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) {0x5995, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) {0x5996, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) {0x5997, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) {0x5998, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) {0x5999, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) {0x599a, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) {0x599b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) {0x599c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) {0x599d, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) {0x599e, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) {0x599f, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) {0x3222, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) {0x3208, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) {0x3938, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) {0x393b, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) {0x3208, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) {0x3208, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) {0x3938, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) {0x393b, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) {0x3208, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) {0x3208, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) {0x3938, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) {0x393b, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) {0x3208, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) {0x3208, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) {0x3938, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) {0x393b, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) {0x3208, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) {0x5000, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) {0x5001, 0xd1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) * The width and height must be configured to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) * the same as the current output resolution of the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) * The input width of the isp needs to be 16 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) * The input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) * If the width or height does not meet the alignment rules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) * you can configure the cropping parameters with the following function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) * crop out the appropriate resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) * struct v4l2_subdev_pad_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) * .get_selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static const struct ov12d2q_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .width = 2256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .height = 1256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .exp_def = 0x0560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .hts_def = 0x021b*5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .vts_def = 0x0570,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .reg_list = ov12d2q_2256x1256_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .width = 4512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .height = 2512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .exp_def = 0x0ad0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .hts_def = 0x021c*9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .vts_def = 0x0ae0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .reg_list = ov12d2q_4512x2512_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) MIPI_FREQ_625M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) static const char * const ov12d2q_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) static int __ov12d2q_power_on(struct ov12d2q *ov12d2q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static int ov12d2q_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) static int ov12d2q_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) ret |= ov12d2q_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) OV12D2Q_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static int ov12d2q_read_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static int ov12d2q_get_reso_dist(const struct ov12d2q_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) static const struct ov12d2q_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) ov12d2q_find_best_fit(struct ov12d2q *ov12d2q, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) for (i = 0; i < ov12d2q->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) dist = ov12d2q_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) (supported_modes[i].bus_fmt == framefmt->code)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) static int ov12d2q_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) struct ov12d2q *ov12d2q = to_ov12d2q(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) const struct ov12d2q_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) mutex_lock(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) mode = ov12d2q_find_best_fit(ov12d2q, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) mutex_unlock(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) ov12d2q->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) __v4l2_ctrl_modify_range(ov12d2q->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) __v4l2_ctrl_modify_range(ov12d2q->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) OV12D2Q_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) dst_pixel_rate = PIXEL_RATE_WITH_625M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) __v4l2_ctrl_s_ctrl_int64(ov12d2q->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) __v4l2_ctrl_s_ctrl(ov12d2q->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) mutex_unlock(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) static int ov12d2q_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) struct ov12d2q *ov12d2q = to_ov12d2q(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) const struct ov12d2q_mode *mode = ov12d2q->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) mutex_lock(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) mutex_unlock(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) mutex_unlock(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) static int ov12d2q_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) struct ov12d2q *ov12d2q = to_ov12d2q(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) code->code = ov12d2q->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) static int ov12d2q_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) struct ov12d2q *ov12d2q = to_ov12d2q(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) if (fse->index >= ov12d2q->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) static int ov12d2q_enable_test_pattern(struct ov12d2q *ov12d2q, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) val = ((pattern - 1) << 4) | OV12D2Q_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) val = OV12D2Q_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) ret = ov12d2q_write_reg(ov12d2q->client, OV12D2Q_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) OV12D2Q_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) static int ov12d2q_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) struct ov12d2q *ov12d2q = to_ov12d2q(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) const struct ov12d2q_mode *mode = ov12d2q->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) mutex_lock(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) mutex_unlock(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) static int ov12d2q_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) struct ov12d2q *ov12d2q = to_ov12d2q(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) const struct ov12d2q_mode *mode = ov12d2q->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) val = 1 << (OV12D2Q_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) if (mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) val = 1 << (OV12D2Q_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) static void ov12d2q_get_module_inf(struct ov12d2q *ov12d2q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) strlcpy(inf->base.sensor, OV12D2Q_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) strlcpy(inf->base.module, ov12d2q->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) strlcpy(inf->base.lens, ov12d2q->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) static long ov12d2q_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) struct ov12d2q *ov12d2q = to_ov12d2q(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) struct rkmodule_hdr_cfg *hdr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) w = ov12d2q->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) h = ov12d2q->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) for (i = 0; i < ov12d2q->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) ov12d2q->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (i == ov12d2q->cfg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) dev_err(&ov12d2q->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) hdr_cfg->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) w = ov12d2q->cur_mode->hts_def - ov12d2q->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) h = ov12d2q->cur_mode->vts_def - ov12d2q->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) __v4l2_ctrl_modify_range(ov12d2q->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) __v4l2_ctrl_modify_range(ov12d2q->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) OV12D2Q_VTS_MAX - ov12d2q->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) dev_info(&ov12d2q->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) "sensor mode: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) ov12d2q->cur_mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) ov12d2q_get_module_inf(ov12d2q, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) hdr_cfg->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) hdr_cfg->hdr_mode = ov12d2q->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) ret = ov12d2q_write_reg(ov12d2q->client, OV12D2Q_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) OV12D2Q_REG_VALUE_08BIT, OV12D2Q_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) ret = ov12d2q_write_reg(ov12d2q->client, OV12D2Q_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) OV12D2Q_REG_VALUE_08BIT, OV12D2Q_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) static long ov12d2q_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) u32 cg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) ret = ov12d2q_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) ret = ov12d2q_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) ret = ov12d2q_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) ret = ov12d2q_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) ret = ov12d2q_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) ret = copy_from_user(&cg, up, sizeof(cg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) ret = ov12d2q_ioctl(sd, cmd, &cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) ret = ov12d2q_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) static int __ov12d2q_start_stream(struct ov12d2q *ov12d2q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) if (!ov12d2q->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) ret = ov12d2q_write_array(ov12d2q->client, ov12d2q_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) dev_err(&ov12d2q->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) ret = ov12d2q_write_array(ov12d2q->client, ov12d2q->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) ret = __v4l2_ctrl_handler_setup(&ov12d2q->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) return ov12d2q_write_reg(ov12d2q->client, OV12D2Q_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) OV12D2Q_REG_VALUE_08BIT, OV12D2Q_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) static int __ov12d2q_stop_stream(struct ov12d2q *ov12d2q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) if (ov12d2q->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) ov12d2q->is_first_streamoff = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) return ov12d2q_write_reg(ov12d2q->client, OV12D2Q_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) OV12D2Q_REG_VALUE_08BIT, OV12D2Q_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) static int ov12d2q_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) struct ov12d2q *ov12d2q = to_ov12d2q(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) struct i2c_client *client = ov12d2q->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) mutex_lock(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) if (on == ov12d2q->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) if (ov12d2q->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) ov12d2q->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) __ov12d2q_power_on(ov12d2q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) ret = __ov12d2q_start_stream(ov12d2q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) __ov12d2q_stop_stream(ov12d2q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) ov12d2q->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) mutex_unlock(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) static int ov12d2q_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) struct ov12d2q *ov12d2q = to_ov12d2q(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) struct i2c_client *client = ov12d2q->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) mutex_lock(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) if (ov12d2q->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) if (!ov12d2q->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) ret |= ov12d2q_write_reg(ov12d2q->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) OV12D2Q_SOFTWARE_RESET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) OV12D2Q_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) ov12d2q->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) ov12d2q->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) mutex_unlock(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) static inline u32 ov12d2q_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) return DIV_ROUND_UP(cycles, OV12D2Q_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) static int __ov12d2q_power_on(struct ov12d2q *ov12d2q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) struct device *dev = &ov12d2q->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) if (ov12d2q->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) if (!IS_ERR_OR_NULL(ov12d2q->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) ret = pinctrl_select_state(ov12d2q->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) ov12d2q->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) ret = clk_set_rate(ov12d2q->xvclk, OV12D2Q_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) if (clk_get_rate(ov12d2q->xvclk) != OV12D2Q_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) ret = clk_prepare_enable(ov12d2q->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) if (!IS_ERR(ov12d2q->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) gpiod_direction_output(ov12d2q->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) ret = regulator_bulk_enable(OV12D2Q_NUM_SUPPLIES, ov12d2q->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) if (!IS_ERR(ov12d2q->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) gpiod_direction_output(ov12d2q->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) if (!IS_ERR(ov12d2q->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) gpiod_direction_output(ov12d2q->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) * There is no need to wait for the delay of RC circuit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) * if the reset signal is directly controlled by GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) if (!IS_ERR(ov12d2q->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) usleep_range(6000, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) usleep_range(12000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) delay_us = ov12d2q_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) clk_disable_unprepare(ov12d2q->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) static void __ov12d2q_power_off(struct ov12d2q *ov12d2q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) struct device *dev = &ov12d2q->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) if (ov12d2q->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) if (ov12d2q->is_first_streamoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) ov12d2q->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) ov12d2q->is_first_streamoff = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) if (!IS_ERR(ov12d2q->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) gpiod_direction_output(ov12d2q->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) clk_disable_unprepare(ov12d2q->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) if (!IS_ERR(ov12d2q->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) gpiod_direction_output(ov12d2q->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) if (!IS_ERR_OR_NULL(ov12d2q->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) ret = pinctrl_select_state(ov12d2q->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) ov12d2q->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) if (ov12d2q->is_thunderboot_ng) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) ov12d2q->is_thunderboot_ng = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) regulator_bulk_disable(OV12D2Q_NUM_SUPPLIES, ov12d2q->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) static int ov12d2q_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) struct ov12d2q *ov12d2q = to_ov12d2q(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) return __ov12d2q_power_on(ov12d2q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) static int ov12d2q_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) struct ov12d2q *ov12d2q = to_ov12d2q(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) __ov12d2q_power_off(ov12d2q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) static int ov12d2q_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) struct ov12d2q *ov12d2q = to_ov12d2q(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) const struct ov12d2q_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) mutex_lock(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) mutex_unlock(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static int ov12d2q_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) struct ov12d2q *ov12d2q = to_ov12d2q(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) if (fie->index >= ov12d2q->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) static const struct dev_pm_ops ov12d2q_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) SET_RUNTIME_PM_OPS(ov12d2q_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) ov12d2q_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) static const struct v4l2_subdev_internal_ops ov12d2q_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) .open = ov12d2q_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) static const struct v4l2_subdev_core_ops ov12d2q_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .s_power = ov12d2q_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .ioctl = ov12d2q_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .compat_ioctl32 = ov12d2q_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) static const struct v4l2_subdev_video_ops ov12d2q_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .s_stream = ov12d2q_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .g_frame_interval = ov12d2q_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) static const struct v4l2_subdev_pad_ops ov12d2q_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .enum_mbus_code = ov12d2q_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .enum_frame_size = ov12d2q_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) .enum_frame_interval = ov12d2q_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) .get_fmt = ov12d2q_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) .set_fmt = ov12d2q_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) .get_mbus_config = ov12d2q_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) static const struct v4l2_subdev_ops ov12d2q_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) .core = &ov12d2q_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) .video = &ov12d2q_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) .pad = &ov12d2q_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) static int ov12d2q_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) struct ov12d2q *ov12d2q = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) struct ov12d2q, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) struct i2c_client *client = ov12d2q->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) u32 again, dgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) u32 val = 0, x_win = 0, y_win = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) max = ov12d2q->cur_mode->height + ctrl->val - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) __v4l2_ctrl_modify_range(ov12d2q->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) ov12d2q->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) ov12d2q->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) ov12d2q->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) if (ov12d2q->cur_mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) ret = ov12d2q_write_reg(ov12d2q->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) OV12D2Q_REG_EXP_L_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) OV12D2Q_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) dev_dbg(&client->dev, "set exposure 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) if (ov12d2q->cur_mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) if (ctrl->val > 1984) {// >15.5x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) dgain = ctrl->val * 10 / 155;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) again = 1984;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) dgain = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) again = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) ret |= ov12d2q_write_reg(ov12d2q->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) OV12D2Q_REG_AGAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) OV12D2Q_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) (again << 1) & 0x7ffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) ret |= ov12d2q_write_reg(ov12d2q->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) OV12D2Q_REG_DGAIN_L_H_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) OV12D2Q_REG_VALUE_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) (dgain << 6) & 0xfffc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) dev_dbg(&client->dev, "set gain 0x%x set analog gain 0x%x digital gain 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) ctrl->val, again, dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) ret = ov12d2q_write_reg(ov12d2q->client, OV12D2Q_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) OV12D2Q_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) ctrl->val + ov12d2q->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) dev_dbg(&client->dev, "set vblank 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) ret = ov12d2q_enable_test_pattern(ov12d2q, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) ret = ov12d2q_read_reg(ov12d2q->client, OV12D2Q_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) OV12D2Q_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) val |= MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) val &= ~MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) ret |= ov12d2q_read_reg(ov12d2q->client, OV12D2Q_REG_ISP_X_WIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) OV12D2Q_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) &x_win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) if((x_win == 0x0021) && (!(val & 0x04))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) x_win = 0x0020;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) }else if((x_win == 0x0020) && (val & 0x04)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) x_win = 0x0021;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) ret |= ov12d2q_write_reg(ov12d2q->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) OV12D2Q_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) OV12D2Q_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) OV12D2Q_GROUP_UPDATE_START_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) ret |= ov12d2q_write_reg(ov12d2q->client, OV12D2Q_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) OV12D2Q_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) ret |= ov12d2q_write_reg(ov12d2q->client, OV12D2Q_REG_ISP_X_WIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) OV12D2Q_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) x_win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) ret |= ov12d2q_write_reg(ov12d2q->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) OV12D2Q_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) OV12D2Q_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) OV12D2Q_GROUP_UPDATE_END_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) ret |= ov12d2q_write_reg(ov12d2q->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) OV12D2Q_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) OV12D2Q_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) OV12D2Q_GROUP_UPDATE_LAUNCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) ret = ov12d2q_read_reg(ov12d2q->client, OV12D2Q_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) OV12D2Q_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) val |= FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) val &= ~FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) ret |= ov12d2q_read_reg(ov12d2q->client, OV12D2Q_REG_ISP_Y_WIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) OV12D2Q_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) &y_win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) if ((y_win == 0x0004) && (val & 0x04)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) y_win = 0x0005;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) } else if ((y_win == 0x0005) && (!(val & 0x04))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) y_win = 0x0004;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) ret |= ov12d2q_write_reg(ov12d2q->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) OV12D2Q_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) OV12D2Q_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) OV12D2Q_GROUP_UPDATE_START_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) ret |= ov12d2q_write_reg(ov12d2q->client, OV12D2Q_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) OV12D2Q_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) ret |= ov12d2q_write_reg(ov12d2q->client, OV12D2Q_REG_ISP_Y_WIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) OV12D2Q_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) y_win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) ret |= ov12d2q_write_reg(ov12d2q->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) OV12D2Q_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) OV12D2Q_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) OV12D2Q_GROUP_UPDATE_END_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) ret |= ov12d2q_write_reg(ov12d2q->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) OV12D2Q_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) OV12D2Q_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) OV12D2Q_GROUP_UPDATE_LAUNCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) static const struct v4l2_ctrl_ops ov12d2q_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) .s_ctrl = ov12d2q_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) static int ov12d2q_initialize_controls(struct ov12d2q *ov12d2q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) const struct ov12d2q_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) handler = &ov12d2q->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) mode = ov12d2q->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) handler->lock = &ov12d2q->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) ov12d2q->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) if (ov12d2q->cur_mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) dst_pixel_rate = PIXEL_RATE_WITH_625M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) ov12d2q->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) 0, PIXEL_RATE_WITH_625M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) __v4l2_ctrl_s_ctrl(ov12d2q->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) ov12d2q->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) if (ov12d2q->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) ov12d2q->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) ov12d2q->vblank = v4l2_ctrl_new_std(handler, &ov12d2q_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) OV12D2Q_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) exposure_max = mode->vts_def - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) ov12d2q->exposure = v4l2_ctrl_new_std(handler, &ov12d2q_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) V4L2_CID_EXPOSURE, OV12D2Q_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) exposure_max, OV12D2Q_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) ov12d2q->anal_gain = v4l2_ctrl_new_std(handler, &ov12d2q_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) V4L2_CID_ANALOGUE_GAIN, OV12D2Q_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) OV12D2Q_GAIN_MAX, OV12D2Q_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) OV12D2Q_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) ov12d2q->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) &ov12d2q_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) ARRAY_SIZE(ov12d2q_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) 0, 0, ov12d2q_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) ov12d2q->h_flip = v4l2_ctrl_new_std(handler, &ov12d2q_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) ov12d2q->v_flip = v4l2_ctrl_new_std(handler, &ov12d2q_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) dev_err(&ov12d2q->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) ov12d2q->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) static int ov12d2q_check_sensor_id(struct ov12d2q *ov12d2q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) struct device *dev = &ov12d2q->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) if (ov12d2q->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) ret = ov12d2q_read_reg(client, OV12D2Q_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) OV12D2Q_REG_VALUE_24BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) static int ov12d2q_configure_regulators(struct ov12d2q *ov12d2q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) for (i = 0; i < OV12D2Q_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) ov12d2q->supplies[i].supply = ov12d2q_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) return devm_regulator_bulk_get(&ov12d2q->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) OV12D2Q_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) ov12d2q->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) static int ov12d2q_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) struct ov12d2q *ov12d2q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) ov12d2q = devm_kzalloc(dev, sizeof(*ov12d2q), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) if (!ov12d2q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) &ov12d2q->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) &ov12d2q->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) &ov12d2q->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) &ov12d2q->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) ov12d2q->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) hdr_mode = NO_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) dev_warn(dev, " Get hdr mode failed! no hdr default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) ov12d2q->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) for (i = 0; i < ov12d2q->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) ov12d2q->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) ov12d2q->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) ov12d2q->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) if (IS_ERR(ov12d2q->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) ov12d2q->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) if (IS_ERR(ov12d2q->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) ov12d2q->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) if (IS_ERR(ov12d2q->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) ov12d2q->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) if (!IS_ERR(ov12d2q->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) ov12d2q->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) pinctrl_lookup_state(ov12d2q->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) if (IS_ERR(ov12d2q->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) ov12d2q->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) pinctrl_lookup_state(ov12d2q->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) if (IS_ERR(ov12d2q->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) ret = ov12d2q_configure_regulators(ov12d2q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) mutex_init(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) sd = &ov12d2q->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) v4l2_i2c_subdev_init(sd, client, &ov12d2q_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) ret = ov12d2q_initialize_controls(ov12d2q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) ret = __ov12d2q_power_on(ov12d2q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) ret = ov12d2q_check_sensor_id(ov12d2q, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) sd->internal_ops = &ov12d2q_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) ov12d2q->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) ret = media_entity_pads_init(&sd->entity, 1, &ov12d2q->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) if (strcmp(ov12d2q->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) ov12d2q->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) OV12D2Q_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) __ov12d2q_power_off(ov12d2q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) v4l2_ctrl_handler_free(&ov12d2q->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) mutex_destroy(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) static int ov12d2q_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) struct ov12d2q *ov12d2q = to_ov12d2q(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) v4l2_ctrl_handler_free(&ov12d2q->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) mutex_destroy(&ov12d2q->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) __ov12d2q_power_off(ov12d2q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) static const struct of_device_id ov12d2q_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) { .compatible = "ovti,ov12d2q" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) MODULE_DEVICE_TABLE(of, ov12d2q_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) static const struct i2c_device_id ov12d2q_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) { "ovti,ov12d2q", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) static struct i2c_driver ov12d2q_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) .name = OV12D2Q_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) .pm = &ov12d2q_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) .of_match_table = of_match_ptr(ov12d2q_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) .probe = &ov12d2q_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) .remove = &ov12d2q_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) .id_table = ov12d2q_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) module_i2c_driver(ov12d2q_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) return i2c_add_driver(&ov12d2q_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) i2c_del_driver(&ov12d2q_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) MODULE_DESCRIPTION("OmniVision ov12d2q sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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