^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ov02k10 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version, only linear mode ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 both linear and HDR modes are ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X02 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MIPI_FREQ_360M 360000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MIPI_FREQ_480M 480000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PIXEL_RATE_WITH_360M (MIPI_FREQ_360M * 2 / 12 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PIXEL_RATE_WITH_480M (MIPI_FREQ_480M * 2 / 12 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OV02K10_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CHIP_ID 0x530243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OV02K10_REG_CHIP_ID 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OV02K10_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OV02K10_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV02K10_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OV02K10_EXPOSURE_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OV02K10_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OV02K10_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OV02K10_REG_EXP_LONG_H 0x3501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV02K10_REG_EXP_MID_H 0x3541
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV02K10_REG_EXP_VS_H 0x3581
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OV02K10_REG_HCG_SWITCH 0x376C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OV02K10_REG_AGAIN_LONG_H 0x3508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OV02K10_REG_AGAIN_MID_H 0x3548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OV02K10_REG_AGAIN_VS_H 0x3588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OV02K10_REG_DGAIN_LONG_H 0x350A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OV02K10_REG_DGAIN_MID_H 0x354A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OV02K10_REG_DGAIN_VS_H 0x358A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OV02K10_GAIN_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OV02K10_GAIN_MAX 0xF7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OV02K10_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OV02K10_GAIN_DEFAULT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OV02K10_GROUP_UPDATE_ADDRESS 0x3208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OV02K10_GROUP_UPDATE_START_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OV02K10_GROUP_UPDATE_END_DATA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OV02K10_GROUP_UPDATE_LAUNCH 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OV02K10_SOFTWARE_RESET_REG 0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OV02K10_FETCH_MSB_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF) /* 8 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OV02K10_FETCH_LSB_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 8 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OV02K10_FETCH_LSB_GAIN(VAL) (((VAL) << 4) & 0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OV02K10_FETCH_MSB_GAIN(VAL) (((VAL) >> 4) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OV02K10_REG_TEST_PATTERN 0x50C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OV02K10_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OV02K10_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OV02K10_REG_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OV02K10_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OV02K10_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OV02K10_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OV02K10_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OV02K10_NAME "ov02k10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OV02K10_FLIP_REG 0x3820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MIRROR_BIT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define FLIP_BIT_MASK (BIT(2) | BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const char * const ov02k10_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OV02K10_NUM_SUPPLIES ARRAY_SIZE(ov02k10_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct ov02k10_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct ov02k10 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct regulator_bulk_data supplies[OV02K10_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct v4l2_ctrl *h_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct v4l2_ctrl *v_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) const struct ov02k10_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bool long_hcg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) bool middle_hcg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) bool short_hcg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define to_ov02k10(sd) container_of(sd, struct ov02k10, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct regval ov02k10_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x302a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x0109, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x0104, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x0306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x0307, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x032d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x0317, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x0323, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x0324, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x0325, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x0327, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x300f, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3012, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x302d, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3400, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3406, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3504, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3508, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3509, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3544, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3548, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3549, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3584, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3588, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3589, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3601, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3604, 0xe3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3608, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x360a, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x360b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x360e, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x360f, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3610, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3611, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3612, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3613, 0xbd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x362a, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x362b, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x362c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x362d, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x362e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x362f, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3630, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3631, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3638, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3643, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3644, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3645, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3646, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3647, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3648, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3649, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x364a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x364c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x364d, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x364e, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x364f, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3650, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3651, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3661, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3662, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3663, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3665, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3667, 0xd4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3668, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3681, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3700, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3701, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3702, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3703, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3790, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3793, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3794, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3796, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3797, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x37a1, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x37bb, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x37be, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x37bf, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x37c0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x37c7, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x37ca, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x37cd, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x37cf, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x37da, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x37db, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x37dd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x3803, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3804, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3805, 0x8f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3806, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3807, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3808, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x380a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x380b, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x3811, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x3813, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x3814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3815, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x3816, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x3817, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x3822, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x3865, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3866, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3867, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3868, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3900, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3940, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3980, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3c01, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3c05, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x3c0f, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x3c12, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x3c19, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x3c21, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x3c3b, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x3c3d, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3c55, 0xcb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3ce0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3ce1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3ce2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3ce3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3d8c, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3d8d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x4033, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x4008, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x4009, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x4004, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x4005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x410f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x402e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x402f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x4030, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x4031, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x4032, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x4050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x4051, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x4289, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x428a, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x430b, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x430c, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x430d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x430e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x4500, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x4501, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x4504, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x4603, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x4640, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x4646, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x4647, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x4648, 0x99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x4649, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x464d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x4654, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x4655, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x4800, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x4810, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x4811, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x4837, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x4d00, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x4d01, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x4d09, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x5000, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x5080, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x50c0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x5100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x5200, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x5201, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x5202, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x5203, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x3707, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x3714, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x371c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x371d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3762, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3777, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3779, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x377c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x379c, 0x4d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3784, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x3785, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x37d8, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x37dc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const struct regval ov02k10_linear12bit_1920x1080_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x0102, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x0305, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x3026, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x3027, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x3103, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x3106, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x3408, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x340c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3425, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3426, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3427, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x3428, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3429, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x342a, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x342b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x3605, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x3606, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x366f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x3670, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x3671, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x3673, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x3706, 0xb1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x3708, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x3709, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x370a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x370b, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x371b, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x3756, 0xe7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x3757, 0xe7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x376c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x3776, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x37cc, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x37d1, 0xb1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x37d2, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x37d3, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x37d5, 0xb1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x37d6, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x37d7, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x380d, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x380e, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x380f, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x381c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x3820, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x384d, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3858, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x3c5d, 0xec},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x3c5e, 0xec},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x4001, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x400a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x400b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x4011, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x4288, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x4314, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x4507, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x480e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x4813, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x484b, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x5780, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x5786, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x032e, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x032d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3501, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x380c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x380d, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x384c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x384d, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x380e, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x380f, 0x7c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x3834, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x3832, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const struct regval ov02k10_hdr12bit_1920x1080_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x0102, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x0305, 0x6d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x3026, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x3027, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x3103, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x3106, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x3408, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x340c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x3425, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x3426, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x3427, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x3428, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x3429, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x342a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x342b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x3605, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x3606, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x366f, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x3670, 0xc7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x3671, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x3673, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x3706, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x3708, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x3709, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x370a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x370b, 0xa3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x371b, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x3756, 0x9b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x3757, 0x9b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x376c, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x3776, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x37cc, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x37d1, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x37d2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x37d3, 0xa3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x37d5, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x37d6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x37d7, 0xa3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x380d, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x380e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x380f, 0xe2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x381c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x3820, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x384d, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x3858, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x3c5d, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x3c5e, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x4001, 0xef},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x400a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x400b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x4011, 0xbb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x4288, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x4314, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x4507, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x4508, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x480e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x4813, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x484b, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x5780, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x5786, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x032e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x032d, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x3106, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x380c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x380d, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x384c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x384d, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x380e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x380f, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x3834, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x3832, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x3002, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * The width and height must be configured to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * the same as the current output resolution of the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * The input width of the isp needs to be 16 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * The input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * If the width or height does not meet the alignment rules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * you can configure the cropping parameters with the following function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * crop out the appropriate resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * struct v4l2_subdev_pad_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * .get_selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const struct ov02k10_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .exp_def = 0x067a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .hts_def = 0x04c8 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .vts_def = 0x0b7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .reg_list = ov02k10_linear12bit_1920x1080_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .exp_def = 0x026c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .hts_def = 0x0420 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .vts_def = 0x06a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .reg_list = ov02k10_hdr12bit_1920x1080_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) MIPI_FREQ_360M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) MIPI_FREQ_480M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const char * const ov02k10_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int ov02k10_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int ov02k10_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ret |= ov02k10_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) OV02K10_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int ov02k10_read_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int ov02k10_get_reso_dist(const struct ov02k10_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static const struct ov02k10_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ov02k10_find_best_fit(struct ov02k10 *ov02k10, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) for (i = 0; i < ov02k10->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dist = ov02k10_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) (supported_modes[i].bus_fmt == framefmt->code)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static int ov02k10_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) const struct ov02k10_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) mutex_lock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mode = ov02k10_find_best_fit(ov02k10, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) mutex_unlock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ov02k10->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) __v4l2_ctrl_modify_range(ov02k10->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) __v4l2_ctrl_modify_range(ov02k10->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) OV02K10_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dst_pixel_rate = PIXEL_RATE_WITH_360M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) } else if (mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dst_link_freq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dst_pixel_rate = PIXEL_RATE_WITH_480M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) __v4l2_ctrl_s_ctrl_int64(ov02k10->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) __v4l2_ctrl_s_ctrl(ov02k10->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) mutex_unlock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static int ov02k10_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) const struct ov02k10_mode *mode = ov02k10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) mutex_lock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) mutex_unlock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mutex_unlock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static int ov02k10_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) code->code = ov02k10->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int ov02k10_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (fse->index >= ov02k10->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int ov02k10_enable_test_pattern(struct ov02k10 *ov02k10, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) val = (pattern - 1) | OV02K10_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) val = OV02K10_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return ov02k10_write_reg(ov02k10->client, OV02K10_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) OV02K10_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int ov02k10_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) const struct ov02k10_mode *mode = ov02k10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) mutex_lock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) mutex_unlock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int ov02k10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) const struct ov02k10_mode *mode = ov02k10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) val = 1 << (OV02K10_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) val = 1 << (OV02K10_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static void ov02k10_get_module_inf(struct ov02k10 *ov02k10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) strlcpy(inf->base.sensor, OV02K10_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) strlcpy(inf->base.module, ov02k10->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) strlcpy(inf->base.lens, ov02k10->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static int ov02k10_set_hdrae(struct ov02k10 *ov02k10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u32 l_a_gain, m_a_gain, s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) u32 l_d_gain = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 m_d_gain = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) u8 l_cg_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u8 m_cg_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u8 s_cg_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) u32 gain_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u8 is_need_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (!ov02k10->has_init_exp && !ov02k10->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ov02k10->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ov02k10->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dev_dbg(&ov02k10->client->dev, "ov02k10 don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) l_a_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) m_a_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) s_a_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) l_cg_mode = ae->long_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) m_cg_mode = ae->middle_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) s_cg_mode = ae->short_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dev_dbg(&ov02k10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) "rev exp:M_exp:0x%x,0x%x,cg %d,S_exp:0x%x,0x%x,cg %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) m_exp_time, m_a_gain, m_cg_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) s_exp_time, s_a_gain, s_cg_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (ov02k10->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) //2 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) l_a_gain = m_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) l_cg_mode = m_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) m_a_gain = s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) m_exp_time = s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) m_cg_mode = s_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ret = ov02k10_read_reg(ov02k10->client, OV02K10_REG_HCG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) OV02K10_REG_VALUE_08BIT, &gain_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (ov02k10->long_hcg && l_cg_mode == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) gain_switch |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ov02k10->long_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) is_need_switch++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) } else if (!ov02k10->long_hcg && l_cg_mode == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) gain_switch &= 0xef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ov02k10->long_hcg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) is_need_switch++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (ov02k10->middle_hcg && m_cg_mode == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) gain_switch |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ov02k10->middle_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) is_need_switch++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) } else if (!ov02k10->middle_hcg && m_cg_mode == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) gain_switch &= 0xdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ov02k10->middle_hcg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) is_need_switch++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (l_a_gain > 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) l_d_gain = l_a_gain * 1024 / 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) l_a_gain = 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (m_a_gain > 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) m_d_gain = m_a_gain * 1024 / 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) m_a_gain = 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ret |= ov02k10_write_reg(ov02k10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) OV02K10_REG_AGAIN_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) OV02K10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) (l_a_gain << 4) & 0xff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ret |= ov02k10_write_reg(ov02k10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) OV02K10_REG_DGAIN_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) OV02K10_REG_VALUE_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) (l_d_gain << 6) & 0xfffc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ret |= ov02k10_write_reg(ov02k10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) OV02K10_REG_EXP_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) OV02K10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) l_exp_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ret |= ov02k10_write_reg(ov02k10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) OV02K10_REG_AGAIN_MID_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) OV02K10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) (m_a_gain << 4) & 0xff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ret |= ov02k10_write_reg(ov02k10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) OV02K10_REG_DGAIN_MID_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) OV02K10_REG_VALUE_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) (m_d_gain << 6) & 0xfffc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ret |= ov02k10_write_reg(ov02k10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) OV02K10_REG_EXP_MID_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) OV02K10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) m_exp_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (is_need_switch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ret |= ov02k10_write_reg(ov02k10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) OV02K10_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) OV02K10_GROUP_UPDATE_START_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ret |= ov02k10_write_reg(ov02k10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) OV02K10_REG_HCG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) gain_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ret |= ov02k10_write_reg(ov02k10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) OV02K10_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) OV02K10_GROUP_UPDATE_END_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ret |= ov02k10_write_reg(ov02k10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) OV02K10_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) OV02K10_GROUP_UPDATE_LAUNCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static int ov02k10_set_conversion_gain(struct ov02k10 *ov02k10, u32 *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct i2c_client *client = ov02k10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) u32 cur_cg = *cg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) s32 is_need_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dev_dbg(&ov02k10->client->dev, "set conversion gain %d\n", cur_cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) mutex_lock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ret = ov02k10_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) OV02K10_REG_HCG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (ov02k10->long_hcg && cur_cg == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) val |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) is_need_change++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ov02k10->long_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) } else if (!ov02k10->long_hcg && cur_cg == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) val &= 0xef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) is_need_change++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ov02k10->long_hcg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (is_need_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ret |= ov02k10_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) OV02K10_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) OV02K10_GROUP_UPDATE_START_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ret |= ov02k10_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) OV02K10_REG_HCG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ret |= ov02k10_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) OV02K10_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) OV02K10_GROUP_UPDATE_END_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ret |= ov02k10_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) OV02K10_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) OV02K10_GROUP_UPDATE_LAUNCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) mutex_unlock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) dev_dbg(&client->dev, "set conversion gain %d, (reg,val)=(0x%x,0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) cur_cg, OV02K10_REG_HCG_SWITCH, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) //ag: echo 0 > /sys/devices/platform/ff510000.i2c/i2c-1/1-0036-1/cam_s_cg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static ssize_t set_conversion_gain_status(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret = kstrtoint(buf, 0, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (!ret && status >= 0 && status < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ov02k10_set_conversion_gain(ov02k10, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev_err(dev, "input 0 for LCG, 1 for HCG, cur %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static struct device_attribute attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) __ATTR(cam_s_cg, S_IWUSR, NULL, set_conversion_gain_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static int add_sysfs_interfaces(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) for (i = 0; i < ARRAY_SIZE(attributes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (device_create_file(dev, attributes + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) goto undo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) undo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) for (i--; i >= 0 ; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) device_remove_file(dev, attributes + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) dev_err(dev, "%s: failed to create sysfs interface\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static long ov02k10_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct rkmodule_hdr_cfg *hdr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return ov02k10_set_hdrae(ov02k10, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) w = ov02k10->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) h = ov02k10->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) for (i = 0; i < ov02k10->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ov02k10->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (i == ov02k10->cfg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) dev_err(&ov02k10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) hdr_cfg->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) w = ov02k10->cur_mode->hts_def - ov02k10->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) h = ov02k10->cur_mode->vts_def - ov02k10->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) __v4l2_ctrl_modify_range(ov02k10->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) __v4l2_ctrl_modify_range(ov02k10->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) OV02K10_VTS_MAX - ov02k10->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (ov02k10->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dst_pixel_rate = PIXEL_RATE_WITH_360M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) } else if (ov02k10->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) dst_link_freq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) dst_pixel_rate = PIXEL_RATE_WITH_480M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) __v4l2_ctrl_s_ctrl_int64(ov02k10->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) __v4l2_ctrl_s_ctrl(ov02k10->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) dev_info(&ov02k10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) "sensor mode: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ov02k10->cur_mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) ov02k10_get_module_inf(ov02k10, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) hdr_cfg->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) hdr_cfg->hdr_mode = ov02k10->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ret = ov02k10_set_conversion_gain(ov02k10, (u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ret = ov02k10_write_reg(ov02k10->client, OV02K10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) OV02K10_REG_VALUE_08BIT, OV02K10_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ret = ov02k10_write_reg(ov02k10->client, OV02K10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) OV02K10_REG_VALUE_08BIT, OV02K10_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static long ov02k10_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) u32 cg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ret = ov02k10_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ret = ov02k10_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ret = ov02k10_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ret = ov02k10_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ret = ov02k10_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) ret = copy_from_user(&cg, up, sizeof(cg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) ret = ov02k10_ioctl(sd, cmd, &cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ret = ov02k10_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static int ov02k10_init_conversion_gain(struct ov02k10 *ov02k10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct i2c_client *client = ov02k10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ret = ov02k10_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) OV02K10_REG_HCG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) val |= 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ret |= ov02k10_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) OV02K10_REG_HCG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ov02k10->long_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ov02k10->middle_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ov02k10->short_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static int __ov02k10_start_stream(struct ov02k10 *ov02k10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) ret = ov02k10_write_array(ov02k10->client, ov02k10_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) dev_err(&ov02k10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) ret = ov02k10_write_array(ov02k10->client, ov02k10->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ret = ov02k10_init_conversion_gain(ov02k10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) ret = __v4l2_ctrl_handler_setup(&ov02k10->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (ov02k10->has_init_exp && ov02k10->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ret = ov02k10_ioctl(&ov02k10->subdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) &ov02k10->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dev_err(&ov02k10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) return ov02k10_write_reg(ov02k10->client, OV02K10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) OV02K10_REG_VALUE_08BIT, OV02K10_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static int __ov02k10_stop_stream(struct ov02k10 *ov02k10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ov02k10->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return ov02k10_write_reg(ov02k10->client, OV02K10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) OV02K10_REG_VALUE_08BIT, OV02K10_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static int ov02k10_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct i2c_client *client = ov02k10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) mutex_lock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (on == ov02k10->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ret = __ov02k10_start_stream(ov02k10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) __ov02k10_stop_stream(ov02k10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ov02k10->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) mutex_unlock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static int ov02k10_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct i2c_client *client = ov02k10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) mutex_lock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (ov02k10->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) ret |= ov02k10_write_reg(ov02k10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) OV02K10_SOFTWARE_RESET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) ov02k10->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) ov02k10->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) mutex_unlock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static inline u32 ov02k10_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return DIV_ROUND_UP(cycles, OV02K10_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static int __ov02k10_power_on(struct ov02k10 *ov02k10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) struct device *dev = &ov02k10->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (!IS_ERR_OR_NULL(ov02k10->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ret = pinctrl_select_state(ov02k10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) ov02k10->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) ret = clk_set_rate(ov02k10->xvclk, OV02K10_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (clk_get_rate(ov02k10->xvclk) != OV02K10_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ret = clk_prepare_enable(ov02k10->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (!IS_ERR(ov02k10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) gpiod_set_value_cansleep(ov02k10->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (!IS_ERR(ov02k10->power_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) gpiod_set_value_cansleep(ov02k10->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) usleep_range(5000, 5100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) ret = regulator_bulk_enable(OV02K10_NUM_SUPPLIES, ov02k10->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (!IS_ERR(ov02k10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) gpiod_set_value_cansleep(ov02k10->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (!IS_ERR(ov02k10->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) gpiod_set_value_cansleep(ov02k10->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) usleep_range(12000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) delay_us = ov02k10_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) clk_disable_unprepare(ov02k10->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static void __ov02k10_power_off(struct ov02k10 *ov02k10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) struct device *dev = &ov02k10->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (!IS_ERR(ov02k10->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) gpiod_set_value_cansleep(ov02k10->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) clk_disable_unprepare(ov02k10->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (!IS_ERR(ov02k10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) gpiod_set_value_cansleep(ov02k10->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (!IS_ERR_OR_NULL(ov02k10->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) ret = pinctrl_select_state(ov02k10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ov02k10->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) regulator_bulk_disable(OV02K10_NUM_SUPPLIES, ov02k10->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static int ov02k10_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return __ov02k10_power_on(ov02k10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static int ov02k10_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) __ov02k10_power_off(ov02k10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static int ov02k10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) const struct ov02k10_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) mutex_lock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) mutex_unlock(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static int ov02k10_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (fie->index >= ov02k10->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static int ov02k10_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) sel->r.width = 1920;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) sel->r.top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) sel->r.height = 1080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) static const struct dev_pm_ops ov02k10_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) SET_RUNTIME_PM_OPS(ov02k10_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) ov02k10_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static const struct v4l2_subdev_internal_ops ov02k10_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .open = ov02k10_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static const struct v4l2_subdev_core_ops ov02k10_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .s_power = ov02k10_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .ioctl = ov02k10_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .compat_ioctl32 = ov02k10_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static const struct v4l2_subdev_video_ops ov02k10_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .s_stream = ov02k10_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .g_frame_interval = ov02k10_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static const struct v4l2_subdev_pad_ops ov02k10_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .enum_mbus_code = ov02k10_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .enum_frame_size = ov02k10_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .enum_frame_interval = ov02k10_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .get_fmt = ov02k10_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .set_fmt = ov02k10_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .get_selection = ov02k10_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .get_mbus_config = ov02k10_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) static const struct v4l2_subdev_ops ov02k10_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .core = &ov02k10_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .video = &ov02k10_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .pad = &ov02k10_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static int ov02k10_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct ov02k10 *ov02k10 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) struct ov02k10, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) struct i2c_client *client = ov02k10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) u32 again, dgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) max = ov02k10->cur_mode->height + ctrl->val - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) __v4l2_ctrl_modify_range(ov02k10->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) ov02k10->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) ov02k10->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) ov02k10->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) ret = ov02k10_write_reg(ov02k10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) OV02K10_REG_EXP_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) OV02K10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) dev_dbg(&client->dev, "set exposure 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (ctrl->val > 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) dgain = ctrl->val * 1024 / 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) again = 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) dgain = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) again = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) ret = ov02k10_write_reg(ov02k10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) OV02K10_REG_AGAIN_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) OV02K10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) (again << 4) & 0xff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) ret |= ov02k10_write_reg(ov02k10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) OV02K10_REG_DGAIN_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) OV02K10_REG_VALUE_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) (dgain << 6) & 0xfffc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) dev_dbg(&client->dev, "set analog gain 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) ret = ov02k10_write_reg(ov02k10->client, OV02K10_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) OV02K10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) ctrl->val + ov02k10->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) dev_dbg(&client->dev, "set vblank 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) ret = ov02k10_enable_test_pattern(ov02k10, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) dev_dbg(&client->dev, "set test pattern 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) ret = ov02k10_read_reg(ov02k10->client, OV02K10_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) val |= MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) val &= ~MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) ret = ov02k10_write_reg(ov02k10->client, OV02K10_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) ov02k10->flip = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) dev_dbg(&client->dev, "set hflip 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ret = ov02k10_read_reg(ov02k10->client, OV02K10_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) val |= FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) val &= ~FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) ret = ov02k10_write_reg(ov02k10->client, OV02K10_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) OV02K10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) ov02k10->flip = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) dev_dbg(&client->dev, "set vflip 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static const struct v4l2_ctrl_ops ov02k10_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .s_ctrl = ov02k10_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static int ov02k10_initialize_controls(struct ov02k10 *ov02k10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) const struct ov02k10_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) handler = &ov02k10->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) mode = ov02k10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) handler->lock = &ov02k10->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) ov02k10->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) 1, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) if (ov02k10->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) dst_pixel_rate = PIXEL_RATE_WITH_360M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) dst_link_freq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) dst_pixel_rate = PIXEL_RATE_WITH_480M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) ov02k10->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) 0, PIXEL_RATE_WITH_480M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) __v4l2_ctrl_s_ctrl(ov02k10->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) ov02k10->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) if (ov02k10->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) ov02k10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) ov02k10->vblank = v4l2_ctrl_new_std(handler, &ov02k10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) OV02K10_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) exposure_max = mode->vts_def - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) ov02k10->exposure = v4l2_ctrl_new_std(handler, &ov02k10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) V4L2_CID_EXPOSURE, OV02K10_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) exposure_max, OV02K10_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) ov02k10->anal_gain = v4l2_ctrl_new_std(handler, &ov02k10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) V4L2_CID_ANALOGUE_GAIN, OV02K10_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) OV02K10_GAIN_MAX, OV02K10_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) OV02K10_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) ov02k10->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) &ov02k10_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) ARRAY_SIZE(ov02k10_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) 0, 0, ov02k10_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) ov02k10->h_flip = v4l2_ctrl_new_std(handler, &ov02k10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) ov02k10->v_flip = v4l2_ctrl_new_std(handler, &ov02k10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) ov02k10->flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) dev_err(&ov02k10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) ov02k10->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) ov02k10->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) ov02k10->long_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) ov02k10->middle_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) ov02k10->short_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) static int ov02k10_check_sensor_id(struct ov02k10 *ov02k10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) struct device *dev = &ov02k10->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) ret = ov02k10_read_reg(client, OV02K10_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) OV02K10_REG_VALUE_24BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static int ov02k10_configure_regulators(struct ov02k10 *ov02k10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) for (i = 0; i < OV02K10_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) ov02k10->supplies[i].supply = ov02k10_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) return devm_regulator_bulk_get(&ov02k10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) OV02K10_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) ov02k10->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) static int ov02k10_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct ov02k10 *ov02k10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) ov02k10 = devm_kzalloc(dev, sizeof(*ov02k10), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if (!ov02k10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) &ov02k10->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) &ov02k10->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) &ov02k10->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) &ov02k10->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) hdr_mode = NO_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) dev_warn(dev, " Get hdr mode failed! no hdr default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) ov02k10->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) for (i = 0; i < ov02k10->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) ov02k10->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) ov02k10->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) ov02k10->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (IS_ERR(ov02k10->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) ov02k10->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (IS_ERR(ov02k10->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) dev_warn(dev, "Failed to get power-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) ov02k10->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (IS_ERR(ov02k10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) ov02k10->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (IS_ERR(ov02k10->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) ov02k10->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (!IS_ERR(ov02k10->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ov02k10->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) pinctrl_lookup_state(ov02k10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) if (IS_ERR(ov02k10->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) ov02k10->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) pinctrl_lookup_state(ov02k10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if (IS_ERR(ov02k10->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) ret = ov02k10_configure_regulators(ov02k10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) mutex_init(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) sd = &ov02k10->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) v4l2_i2c_subdev_init(sd, client, &ov02k10_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) ret = ov02k10_initialize_controls(ov02k10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) ret = __ov02k10_power_on(ov02k10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ret = ov02k10_check_sensor_id(ov02k10, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) sd->internal_ops = &ov02k10_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) ov02k10->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) ret = media_entity_pads_init(&sd->entity, 1, &ov02k10->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) if (strcmp(ov02k10->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) ov02k10->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) OV02K10_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) add_sysfs_interfaces(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) __ov02k10_power_off(ov02k10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) v4l2_ctrl_handler_free(&ov02k10->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) mutex_destroy(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) static int ov02k10_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) struct ov02k10 *ov02k10 = to_ov02k10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) v4l2_ctrl_handler_free(&ov02k10->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) mutex_destroy(&ov02k10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) __ov02k10_power_off(ov02k10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) static const struct of_device_id ov02k10_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) { .compatible = "ovti,ov02k10" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) MODULE_DEVICE_TABLE(of, ov02k10_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) static const struct i2c_device_id ov02k10_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) { "ovti,ov02k10", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) static struct i2c_driver ov02k10_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .name = OV02K10_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .pm = &ov02k10_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .of_match_table = of_match_ptr(ov02k10_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .probe = &ov02k10_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .remove = &ov02k10_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .id_table = ov02k10_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) module_i2c_driver(ov02k10_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) return i2c_add_driver(&ov02k10_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) i2c_del_driver(&ov02k10_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) MODULE_DESCRIPTION("OmniVision ov02k10 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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