^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * os04a10 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 support conversion gain switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X02 add debug interface for conversion gain switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X03 support enum sensor fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X04 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * V0.0X01.0X05 support get dcg ratio from sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "../platform/rockchip/isp/rkisp_tb_helper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MIPI_FREQ_360M 360000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MIPI_FREQ_648M 648000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MIPI_FREQ_720M 720000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PIXEL_RATE_WITH_360M (MIPI_FREQ_360M * 2 / 10 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PIXEL_RATE_WITH_648M (MIPI_FREQ_648M * 2 / 10 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PIXEL_RATE_WITH_720M (MIPI_FREQ_720M * 2 / 10 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OS04A10_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CHIP_ID 0x530441
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OS04A10_REG_CHIP_ID 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OS04A10_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OS04A10_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OS04A10_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OS04A10_EXPOSURE_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OS04A10_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OS04A10_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OS04A10_REG_EXP_LONG_H 0x3501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OS04A10_REG_EXP_MID_H 0x3541
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OS04A10_REG_EXP_VS_H 0x3581
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OS04A10_REG_HCG_SWITCH 0x376C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OS04A10_REG_AGAIN_LONG_H 0x3508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OS04A10_REG_AGAIN_MID_H 0x3548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OS04A10_REG_AGAIN_VS_H 0x3588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OS04A10_REG_DGAIN_LONG_H 0x350A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OS04A10_REG_DGAIN_MID_H 0x354A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OS04A10_REG_DGAIN_VS_H 0x358A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OS04A10_GAIN_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OS04A10_GAIN_MAX 0xF7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OS04A10_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OS04A10_GAIN_DEFAULT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OS04A10_GROUP_UPDATE_ADDRESS 0x3208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OS04A10_GROUP_UPDATE_START_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OS04A10_GROUP_UPDATE_END_DATA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OS04A10_GROUP_UPDATE_END_LAUNCH 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OS04A10_SOFTWARE_RESET_REG 0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OS04A10_FETCH_MSB_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF) /* 8 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OS04A10_FETCH_LSB_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 8 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OS04A10_FETCH_LSB_GAIN(VAL) (((VAL) << 4) & 0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OS04A10_FETCH_MSB_GAIN(VAL) (((VAL) >> 4) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OS04A10_REG_TEST_PATTERN 0x5080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OS04A10_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OS04A10_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OS04A10_REG_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OS04A10_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OS04A10_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OS04A10_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OS04A10_NAME "os04a10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const char * const os04a10_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OS04A10_NUM_SUPPLIES ARRAY_SIZE(os04a10_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OS04A10_FLIP_REG 0x3820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MIRROR_BIT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FLIP_BIT_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct os04a10_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct regval *global_reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 link_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct os04a10 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct regulator_bulk_data supplies[OS04A10_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct v4l2_ctrl *h_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct v4l2_ctrl *v_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) const struct os04a10_mode *supported_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const struct os04a10_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) bool long_hcg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) bool middle_hcg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bool short_hcg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bool is_thunderboot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) bool is_thunderboot_ng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) bool is_first_streamoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u8 flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 dcg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct v4l2_fwnode_endpoint bus_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define to_os04a10(sd) container_of(sd, struct os04a10, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct regval os04a10_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x0109, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x0104, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x0102, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x0306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x0307, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x030a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x0322, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x0323, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x0324, 0x00},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x4d04, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x4d05, 0x3d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x4d09, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x5080, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x50c0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x5100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x5200, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x5201, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x5202, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x5203, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x5780, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x5786, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x5792, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x5793, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x5857, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x5858, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x5859, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x58d7, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x58d8, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x58d9, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const struct regval os04a10_linear10bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x0305, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x0308, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x0317, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x0325, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x032e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x3605, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x3606, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x362d, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x3662, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x3667, 0xd4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x3671, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x3703, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x3706, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x370a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x370b, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x3719, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x371b, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x3756, 0x9d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x3757, 0x9d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x376c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x37cc, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x37d1, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x37d2, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x37d3, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x37d4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x37d5, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x37d6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x37d7, 0xf7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x3803, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x3805, 0x8f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x3807, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x380b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x380c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x380d, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x380e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x380f, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x381c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x3820, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3833, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x384c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x384d, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x3c5a, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x4004, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x4001, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x4005, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x400a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x400b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x402e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x402f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x4031, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x4032, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x4288, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x430b, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x430c, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x4507, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x480e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x4813, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x4837, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x484b, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x5000, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x5001, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x5782, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x5783, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x5788, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x5789, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const struct regval os04a10_linear12bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x0305, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x0308, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x0317, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x0325, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x032e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x3605, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x3606, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x362d, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x3662, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x3667, 0xd4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x3671, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x3703, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x3706, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x370a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x370b, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x3719, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x371b, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x3756, 0xe7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x3757, 0xe7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x376c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x37cc, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x37d1, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x37d2, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x37d3, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x37d4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x37d5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x37d6, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x37d7, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x3803, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x3805, 0x8f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x3807, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x380b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x380c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x380d, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x380e, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x380f, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x381c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x3820, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x3833, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x384c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x384d, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x3c5a, 0xe5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x4001, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x4004, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x4005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x400a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x400b, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x402e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x402f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x4031, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x4032, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x4288, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x430b, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x430c, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x4507, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x480e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x4813, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x4837, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x484b, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x5000, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x5001, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x5782, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x5783, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x5788, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x5789, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static const struct regval os04a10_hdr10bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x0305, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x0308, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x0317, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x0325, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x032e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x3605, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x3606, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x362d, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x3662, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x3667, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x3671, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x3703, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x3706, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x370a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x370b, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x3719, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x371b, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x3756, 0x9d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x3757, 0x9d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x376c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x37cc, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x37d1, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x37d2, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x37d3, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x37d4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x37d5, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x37d6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x37d7, 0xf7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x3803, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x3805, 0x8f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x3807, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x380b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x380c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x380d, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x380e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x380f, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) //{0x380e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) //{0x380f, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0x381c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x3820, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x3833, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x384c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x384d, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x3c5a, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x4001, 0xef},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x4004, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x4005, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x400a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x400b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x402e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x402f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x4031, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x4032, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x4288, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x430b, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x430c, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x4507, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x480e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x4813, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x4837, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x484b, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x5000, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {0x5001, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {0x5782, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {0x5783, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {0x5788, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {0x5789, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static const struct regval os04a10_hdr12bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0x0305, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {0x0308, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {0x0317, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {0x0325, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {0x032e, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {0x3605, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {0x3606, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {0x362d, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {0x3662, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {0x3667, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {0x3671, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {0x3703, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x3706, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x370a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x370b, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x3719, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x371b, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {0x3756, 0xe7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {0x3757, 0xe7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {0x376c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {0x37cc, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {0x37d1, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {0x37d2, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {0x37d3, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {0x37d4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {0x37d5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {0x37d6, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {0x37d7, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {0x3803, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {0x3805, 0x8f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {0x3807, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {0x380b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {0x380c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {0x380d, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {0x380e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {0x380f, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {0x381c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {0x3820, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {0x3833, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {0x384c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {0x384d, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {0x3c5a, 0xe5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {0x4001, 0xef},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {0x4004, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {0x4005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {0x400a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {0x400b, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {0x402e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {0x402f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {0x4031, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {0x4032, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {0x4288, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {0x430b, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {0x430c, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {0x4507, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {0x480e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {0x4813, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {0x4837, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {0x484b, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {0x5000, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {0x5001, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {0x5782, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {0x5783, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {0x5788, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {0x5789, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static const struct regval os04a10_hdr12bit_2560x1440_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {0x0305, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {0x0308, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {0x0317, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {0x0325, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {0x032e, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {0x3605, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {0x3606, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {0x362d, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {0x3662, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {0x3667, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {0x3671, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {0x3703, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {0x3706, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {0x370a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {0x370b, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {0x3719, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {0x371b, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {0x3756, 0xe7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0x3757, 0xe7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0x376c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0x37cc, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0x37d1, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {0x37d2, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {0x37d3, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {0x37d4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {0x37d5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {0x37d6, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {0x37d7, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {0x3801, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {0x3803, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {0x3805, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {0x3807, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {0x3809, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {0x380b, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0x380c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {0x380d, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {0x380e, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {0x380f, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {0x381c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {0x3820, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {0x3833, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {0x384c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {0x384d, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {0x3c5a, 0xe5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {0x4001, 0xef},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {0x4004, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {0x4005, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {0x400a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {0x400b, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {0x402e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {0x402f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {0x4031, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {0x4032, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {0x4288, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {0x430b, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {0x430c, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {0x4507, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {0x480e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {0x4813, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {0x4837, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {0x484b, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {0x5000, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {0x5001, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {0x5782, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {0x5783, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {0x5788, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {0x5789, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static const struct regval os04a10_global_regs_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {0x0109, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {0x0104, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {0x0102, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {0x0306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {0x0307, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {0x0308, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {0x030a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {0x0317, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {0x0322, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {0x0323, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {0x0324, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {0x0327, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {0x0329, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {0x032c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {0x032d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {0x032e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {0x300f, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {0x3012, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {0x3026, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {0x3027, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {0x302d, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {0x3104, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {0x3106, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {0x3400, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {0x3408, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {0x340c, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {0x340d, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {0x3425, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {0x3426, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {0x3427, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {0x3428, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {0x3429, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {0x342a, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {0x342b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {0x3501, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {0x3504, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {0x3508, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {0x3509, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {0x350a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {0x3544, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {0x3548, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {0x3549, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {0x3584, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {0x3588, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {0x3589, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {0x3601, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {0x3604, 0xe3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {0x3605, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {0x3606, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {0x3608, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {0x360a, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {0x360b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {0x360e, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {0x360f, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {0x3610, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {0x3611, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {0x3612, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {0x3613, 0xbd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {0x3614, 0x9b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {0x362a, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {0x362b, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {0x362c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {0x362d, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {0x362e, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {0x362f, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {0x3630, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {0x3631, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {0x3638, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {0x3643, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {0x3644, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {0x3645, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {0x3646, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {0x3647, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {0x3648, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {0x3649, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {0x364a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {0x364c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {0x364d, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {0x364e, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {0x364f, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {0x3650, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {0x3651, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {0x365a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {0x365b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {0x365c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {0x365d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {0x3661, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {0x3662, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {0x3663, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {0x3665, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {0x3668, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {0x366c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {0x366d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {0x366e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {0x366f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {0x3673, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {0x3681, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {0x3700, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {0x3701, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {0x3702, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {0x3703, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {0x3705, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {0x3706, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {0x3707, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {0x3708, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {0x3709, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {0x370a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {0x370b, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {0x3714, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {0x3719, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {0x371b, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {0x371c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {0x371d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {0x373f, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {0x3740, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {0x3741, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {0x3742, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {0x3743, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {0x3756, 0x9d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {0x3757, 0x9d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {0x3762, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {0x3673, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {0x3681, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {0x3700, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {0x3701, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {0x3702, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {0x3703, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {0x3705, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {0x3706, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {0x3707, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {0x3708, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {0x3709, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {0x370a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {0x370b, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {0x3714, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {0x3719, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {0x371b, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {0x371c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {0x371d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {0x373f, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {0x3740, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {0x3741, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {0x3742, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {0x3743, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {0x3756, 0x9d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {0x3757, 0x9d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {0x3762, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {0x3776, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {0x3777, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {0x3779, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {0x377c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {0x3784, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {0x3785, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {0x3790, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {0x3793, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {0x3794, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {0x3796, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {0x3797, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {0x379c, 0x4d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {0x37a1, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {0x37bb, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {0x37be, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {0x37bf, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {0x37c0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {0x37c4, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {0x37c5, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {0x37c6, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {0x37ca, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {0x37cc, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {0x37cd, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {0x37cf, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {0x37d0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {0x37d1, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {0x37d2, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {0x37d3, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {0x37d4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {0x37d5, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {0x37d6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {0x37d7, 0xf7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {0x37d8, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {0x37dc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {0x37dd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {0x37da, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {0x37db, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {0x3803, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {0x3804, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {0x3805, 0x8f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {0x3806, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {0x3807, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {0x3808, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {0x380a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {0x380b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {0x380e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {0x380f, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {0x3811, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {0x3813, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {0x3814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {0x3815, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {0x3816, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {0x3817, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {0x3822, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {0x3823, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {0x3826, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {0x3827, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {0x384c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {0x384d, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {0x3858, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {0x3865, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {0x3866, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {0x3867, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {0x3868, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {0x3900, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {0x3940, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {0x3980, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {0x3c01, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {0x3c05, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {0x3c0f, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {0x3c12, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {0x3c19, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {0x3c21, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {0x3c3a, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {0x3c3b, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {0x3c3d, 0xc6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {0x3c5a, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {0x3c5d, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {0x3c5e, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {0x3d8c, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {0x3d8d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {0x4000, 0xf9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {0x4004, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {0x4005, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {0x4008, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {0x4009, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {0x400a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {0x400b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {0x400e, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {0x402e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {0x402f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {0x4030, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {0x4031, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {0x4032, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {0x4033, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {0x4050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {0x4051, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {0x4011, 0xbb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {0x410f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {0x4289, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {0x428a, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {0x430b, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {0x430c, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {0x430d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {0x430e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {0x4314, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {0x4500, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {0x4501, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {0x4503, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {0x4504, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {0x4506, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {0x4601, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {0x4603, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {0x460a, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {0x460c, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {0x4640, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {0x4646, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {0x4647, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {0x4648, 0x99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {0x4649, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {0x464d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {0x4654, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {0x4655, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {0x4800, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {0x4810, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {0x4811, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {0x481f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {0x4d00, 0x4d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {0x4d01, 0x9d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {0x4d02, 0xb9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {0x4d03, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {0x4d04, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {0x4d05, 0x3d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {0x4d09, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {0x5000, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {0x5080, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {0x50c0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {0x5100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {0x5200, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {0x5201, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {0x5202, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {0x5203, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {0x5780, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {0x5782, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {0x5783, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {0x5786, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {0x5788, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {0x5789, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {0x5792, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {0x5793, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {0x5857, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {0x5858, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {0x5859, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {0x58d7, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {0x58d8, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {0x58d9, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static const struct regval os04a10_linear10bit_2688x1520_regs_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {0x0305, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {0x0325, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {0x3667, 0xd4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {0x3671, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {0x376c, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {0x380c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {0x380d, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {0x381c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {0x3820, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {0x3833, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {0x3c55, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {0x4001, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {0x4288, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {0x4507, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {0x480e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {0x4813, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {0x4837, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {0x484b, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {0x5001, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static const struct regval os04a10_hdr10bit_2688x1520_regs_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {0x0305, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {0x0325, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {0x3667, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {0x3671, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) {0x376c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {0x380c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {0x380d, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {0x381c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {0x3820, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {0x3833, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {0x3c55, 0xcb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {0x4001, 0xef},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {0x4288, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {0x4507, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {0x480e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {0x4813, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) {0x4837, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {0x484b, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {0x4883, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {0x4884, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {0x4885, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {0x5001, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * The width and height must be configured to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * the same as the current output resolution of the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * The input width of the isp needs to be 16 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * The input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * If the width or height does not meet the alignment rules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * you can configure the cropping parameters with the following function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * crop out the appropriate resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * struct v4l2_subdev_pad_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * .get_selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static const struct os04a10_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .height = 1520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .denominator = 302834,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .exp_def = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .hts_def = 0x02dc * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .vts_def = 0x0cb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .global_reg_list = os04a10_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .reg_list = os04a10_linear10bit_2688x1520_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .height = 1520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .denominator = 302834,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /*.denominator = 151417,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .exp_def = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .hts_def = 0x02dc * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .vts_def = 0x0658,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /*.vts_def = 0x0cb0,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .global_reg_list = os04a10_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .reg_list = os04a10_hdr10bit_2688x1520_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .height = 1520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .denominator = 300372,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .exp_def = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .hts_def = 0x05c4 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .vts_def = 0x0984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .global_reg_list = os04a10_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .reg_list = os04a10_linear12bit_2688x1520_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .link_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .bpp = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .height = 1520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .denominator = 225000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .exp_def = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .hts_def = 0x05c4 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .vts_def = 0x0658,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .global_reg_list = os04a10_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .reg_list = os04a10_hdr12bit_2688x1520_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .link_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .bpp = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .width = 2560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .height = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .exp_def = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .hts_def = 0x05a0 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .vts_def = 0x05dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .global_reg_list = os04a10_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .reg_list = os04a10_hdr12bit_2560x1440_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .link_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .bpp = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static const struct os04a10_mode supported_modes_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .height = 1520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .denominator = 302834,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .exp_def = 0x0640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .hts_def = 0x0894,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .vts_def = 0x0658,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .global_reg_list = os04a10_global_regs_2lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .reg_list = os04a10_linear10bit_2688x1520_regs_2lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .height = 1520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .denominator = 302834,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /*.denominator = 151417,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .exp_def = 0x0640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .hts_def = 0x02dc * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .vts_def = 0x0658,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /*.vts_def = 0x0cb0,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .global_reg_list = os04a10_global_regs_2lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .reg_list = os04a10_hdr10bit_2688x1520_regs_2lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .link_freq_idx = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) MIPI_FREQ_360M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) MIPI_FREQ_648M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) MIPI_FREQ_720M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static const char * const os04a10_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static int __os04a10_power_on(struct os04a10 *os04a10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static int os04a10_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static int os04a10_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ret |= os04a10_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) OS04A10_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static int os04a10_read_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static int os04a10_get_reso_dist(const struct os04a10_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static const struct os04a10_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) os04a10_find_best_fit(struct os04a10 *os04a10, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) for (i = 0; i < os04a10->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) dist = os04a10_get_reso_dist(&os04a10->supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) (os04a10->supported_modes[i].bus_fmt == framefmt->code)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return &os04a10->supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) static int os04a10_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) const struct os04a10_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) mutex_lock(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) mode = os04a10_find_best_fit(os04a10, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) mutex_unlock(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) os04a10->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) __v4l2_ctrl_modify_range(os04a10->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) __v4l2_ctrl_modify_range(os04a10->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) OS04A10_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) dst_link_freq = mode->link_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) mode->bpp * 2 * lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) __v4l2_ctrl_s_ctrl_int64(os04a10->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) __v4l2_ctrl_s_ctrl(os04a10->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) mutex_unlock(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static int os04a10_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) const struct os04a10_mode *mode = os04a10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) mutex_lock(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) mutex_unlock(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) mutex_unlock(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static int os04a10_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) code->code = os04a10->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static int os04a10_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (fse->index >= os04a10->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (fse->code != os04a10->supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) fse->min_width = os04a10->supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) fse->max_width = os04a10->supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) fse->max_height = os04a10->supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) fse->min_height = os04a10->supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) static int os04a10_enable_test_pattern(struct os04a10 *os04a10, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) val = ((pattern - 1) << 2) | OS04A10_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) val = OS04A10_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) ret = os04a10_write_reg(os04a10->client, OS04A10_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) OS04A10_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ret |= os04a10_write_reg(os04a10->client, OS04A10_REG_TEST_PATTERN + 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) OS04A10_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static int os04a10_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) const struct os04a10_mode *mode = os04a10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) mutex_lock(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) mutex_unlock(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static int os04a10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) const struct os04a10_mode *mode = os04a10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) val = 1 << (lanes - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) val = 1 << (lanes - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) static void os04a10_get_module_inf(struct os04a10 *os04a10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) strscpy(inf->base.sensor, OS04A10_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) strscpy(inf->base.module, os04a10->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) strscpy(inf->base.lens, os04a10->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static int os04a10_set_hdrae(struct os04a10 *os04a10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) u32 l_a_gain, m_a_gain, s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) u32 l_d_gain = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) u32 m_d_gain = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) u32 s_d_gain = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) u8 l_cg_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) u8 m_cg_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) u8 s_cg_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) u32 gain_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) u8 is_need_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (!os04a10->has_init_exp && !os04a10->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) os04a10->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) os04a10->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (os04a10->init_hdrae_exp.short_exp_reg >= 0x90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) dev_err(&os04a10->client->dev, "short exposure must less than 0x90 before start stream!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) dev_dbg(&os04a10->client->dev, "os04a10 don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) l_a_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) m_a_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) s_a_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) l_cg_mode = ae->long_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) m_cg_mode = ae->middle_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) s_cg_mode = ae->short_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) dev_dbg(&os04a10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) l_exp_time, l_a_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) m_exp_time, m_a_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) s_exp_time, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if (os04a10->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) //2 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) l_a_gain = m_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) l_cg_mode = m_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) m_a_gain = s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) m_exp_time = s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) m_cg_mode = s_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) ret = os04a10_read_reg(os04a10->client, OS04A10_REG_HCG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) OS04A10_REG_VALUE_08BIT, &gain_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (os04a10->long_hcg && l_cg_mode == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) gain_switch |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) os04a10->long_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) is_need_switch++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) } else if (!os04a10->long_hcg && l_cg_mode == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) gain_switch &= 0xef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) os04a10->long_hcg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) is_need_switch++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (os04a10->middle_hcg && m_cg_mode == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) gain_switch |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) os04a10->middle_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) is_need_switch++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) } else if (!os04a10->middle_hcg && m_cg_mode == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) gain_switch &= 0xdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) os04a10->middle_hcg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) is_need_switch++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (l_a_gain > 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) l_d_gain = l_a_gain * 1024 / 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) l_a_gain = 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (m_a_gain > 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) m_d_gain = m_a_gain * 1024 / 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) m_a_gain = 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (os04a10->cur_mode->hdr_mode == HDR_X3 && s_a_gain > 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) s_d_gain = s_a_gain * 1024 / 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) s_a_gain = 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) OS04A10_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) OS04A10_GROUP_UPDATE_START_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) OS04A10_REG_AGAIN_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) OS04A10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) (l_a_gain << 4) & 0x1ff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) OS04A10_REG_DGAIN_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) OS04A10_REG_VALUE_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) (l_d_gain << 6) & 0xfffc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) OS04A10_REG_EXP_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) OS04A10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) l_exp_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) OS04A10_REG_AGAIN_MID_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) OS04A10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) (m_a_gain << 4) & 0x1ff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) OS04A10_REG_DGAIN_MID_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) OS04A10_REG_VALUE_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) (m_d_gain << 6) & 0xfffc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) OS04A10_REG_EXP_MID_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) OS04A10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) m_exp_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (os04a10->cur_mode->hdr_mode == HDR_X3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) //3 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) OS04A10_REG_AGAIN_VS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) OS04A10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) (s_a_gain << 4) & 0x1ff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) OS04A10_REG_EXP_VS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) OS04A10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) s_exp_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) OS04A10_REG_DGAIN_VS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) OS04A10_REG_VALUE_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) (s_d_gain << 6) & 0xfffc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (os04a10->short_hcg && s_cg_mode == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) gain_switch |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) os04a10->short_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) is_need_switch++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) } else if (!os04a10->short_hcg && s_cg_mode == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) gain_switch &= 0xbf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) os04a10->short_hcg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) is_need_switch++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) if (is_need_switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) OS04A10_REG_HCG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) gain_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) OS04A10_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) OS04A10_GROUP_UPDATE_END_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) OS04A10_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) OS04A10_GROUP_UPDATE_END_LAUNCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static int os04a10_set_conversion_gain(struct os04a10 *os04a10, u32 *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) struct i2c_client *client = os04a10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) u32 cur_cg = *cg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) s32 is_need_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) dev_dbg(&os04a10->client->dev, "set conversion gain %d\n", cur_cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) if (os04a10->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) os04a10->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) os04a10->is_thunderboot_ng = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) __os04a10_power_on(os04a10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) ret = os04a10_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) OS04A10_REG_HCG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (os04a10->long_hcg && cur_cg == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) val |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) is_need_change++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) os04a10->long_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) } else if (!os04a10->long_hcg && cur_cg == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) val &= 0xef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) is_need_change++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) os04a10->long_hcg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) ret |= os04a10_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) OS04A10_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) OS04A10_GROUP_UPDATE_START_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (is_need_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) ret |= os04a10_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) OS04A10_REG_HCG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ret |= os04a10_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) OS04A10_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) OS04A10_GROUP_UPDATE_END_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) ret |= os04a10_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) OS04A10_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) OS04A10_GROUP_UPDATE_END_LAUNCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) //ag: echo 0 > /sys/devices/platform/ff510000.i2c/i2c-1/1-0036-1/cam_s_cg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) static ssize_t set_conversion_gain_status(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) ret = kstrtoint(buf, 0, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) if (!ret && status >= 0 && status < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) os04a10_set_conversion_gain(os04a10, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) dev_err(dev, "input 0 for LCG, 1 for HCG, cur %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) static struct device_attribute attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) __ATTR(cam_s_cg, S_IWUSR, NULL, set_conversion_gain_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) static int add_sysfs_interfaces(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) for (i = 0; i < ARRAY_SIZE(attributes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) if (device_create_file(dev, attributes + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) goto undo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) undo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) for (i--; i >= 0 ; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) device_remove_file(dev, attributes + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) dev_err(dev, "%s: failed to create sysfs interface\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) static long os04a10_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) struct rkmodule_hdr_cfg *hdr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct rkmodule_dcg_ratio *dcg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) const struct os04a10_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) return os04a10_set_hdrae(os04a10, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) w = os04a10->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) h = os04a10->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) for (i = 0; i < os04a10->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (w == os04a10->supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) h == os04a10->supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) os04a10->supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) os04a10->cur_mode = &os04a10->supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (i == os04a10->cfg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) dev_err(&os04a10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) hdr_cfg->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) mode = os04a10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) w = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) h = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) __v4l2_ctrl_modify_range(os04a10->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) __v4l2_ctrl_modify_range(os04a10->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) OS04A10_VTS_MAX - os04a10->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) dst_link_freq = mode->link_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) mode->bpp * 2 * lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) __v4l2_ctrl_s_ctrl_int64(os04a10->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) __v4l2_ctrl_s_ctrl(os04a10->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) dev_info(&os04a10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) "sensor mode: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) os04a10->cur_mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) os04a10_get_module_inf(os04a10, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) hdr_cfg->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) hdr_cfg->hdr_mode = os04a10->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ret = os04a10_set_conversion_gain(os04a10, (u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) ret = os04a10_write_reg(os04a10->client, OS04A10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) OS04A10_REG_VALUE_08BIT, OS04A10_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ret = os04a10_write_reg(os04a10->client, OS04A10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) OS04A10_REG_VALUE_08BIT, OS04A10_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) case RKMODULE_GET_DCG_RATIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if (os04a10->dcg_ratio == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) dcg = (struct rkmodule_dcg_ratio *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) dcg->integer = (os04a10->dcg_ratio >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) dcg->decimal = os04a10->dcg_ratio & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) dcg->div_coeff = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) dev_info(&os04a10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) "get dcg ratio integer %d, decimal %d div_coeff %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) dcg->integer, dcg->decimal, dcg->div_coeff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static long os04a10_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) struct rkmodule_dcg_ratio *dcg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) u32 cg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) ret = os04a10_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ret = os04a10_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) if (copy_from_user(hdr, up, sizeof(*hdr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) ret = os04a10_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) if (copy_from_user(hdrae, up, sizeof(*hdrae)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) ret = os04a10_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) if (copy_from_user(&cg, up, sizeof(cg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) ret = os04a10_ioctl(sd, cmd, &cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (copy_from_user(&stream, up, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) ret = os04a10_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) case RKMODULE_GET_DCG_RATIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) dcg = kzalloc(sizeof(*dcg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) if (!dcg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) ret = os04a10_ioctl(sd, cmd, dcg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) ret = copy_to_user(up, dcg, sizeof(*dcg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) kfree(dcg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) static int os04a10_init_conversion_gain(struct os04a10 *os04a10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) struct i2c_client *client = os04a10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) ret = os04a10_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) OS04A10_REG_HCG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) val &= ~0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) if (!os04a10->long_hcg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) val |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) if (!os04a10->middle_hcg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) val |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) if (!os04a10->short_hcg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) val |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) ret |= os04a10_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) OS04A10_REG_HCG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) static int __os04a10_start_stream(struct os04a10 *os04a10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) if (!os04a10->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) ret = os04a10_write_array(os04a10->client, os04a10->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) ret = os04a10_init_conversion_gain(os04a10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) ret = __v4l2_ctrl_handler_setup(&os04a10->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (os04a10->has_init_exp && os04a10->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) ret = os04a10_ioctl(&os04a10->subdev, PREISP_CMD_SET_HDRAE_EXP, &os04a10->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) dev_err(&os04a10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) return os04a10_write_reg(os04a10->client, OS04A10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) OS04A10_REG_VALUE_08BIT, OS04A10_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) static int __os04a10_stop_stream(struct os04a10 *os04a10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) os04a10->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) if (os04a10->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) os04a10->is_first_streamoff = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) return os04a10_write_reg(os04a10->client, OS04A10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) OS04A10_REG_VALUE_08BIT, OS04A10_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) static int os04a10_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) struct i2c_client *client = os04a10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) mutex_lock(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) if (on == os04a10->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) if (os04a10->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) os04a10->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) __os04a10_power_on(os04a10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) ret = __os04a10_start_stream(os04a10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) __os04a10_stop_stream(os04a10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) os04a10->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) mutex_unlock(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) static int os04a10_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) struct i2c_client *client = os04a10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) mutex_lock(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) if (os04a10->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) if (!os04a10->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) OS04A10_SOFTWARE_RESET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) ret |= os04a10_write_array(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) os04a10->cur_mode->global_reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) dev_err(&os04a10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) os04a10->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) os04a10->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) mutex_unlock(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) static inline u32 os04a10_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) return DIV_ROUND_UP(cycles, OS04A10_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) static int __os04a10_power_on(struct os04a10 *os04a10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) struct device *dev = &os04a10->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) if (os04a10->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) if (!IS_ERR_OR_NULL(os04a10->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) ret = pinctrl_select_state(os04a10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) os04a10->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) ret = clk_set_rate(os04a10->xvclk, OS04A10_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) if (clk_get_rate(os04a10->xvclk) != OS04A10_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) ret = clk_prepare_enable(os04a10->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) if (!IS_ERR(os04a10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) gpiod_direction_output(os04a10->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) ret = regulator_bulk_enable(OS04A10_NUM_SUPPLIES, os04a10->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) usleep_range(25000, 30000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) if (!IS_ERR(os04a10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) gpiod_direction_output(os04a10->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (!IS_ERR(os04a10->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) gpiod_direction_output(os04a10->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) * There is no need to wait for the delay of RC circuit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) * if the reset signal is directly controlled by GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) if (!IS_ERR(os04a10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) usleep_range(6000, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) usleep_range(12000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) delay_us = os04a10_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) clk_disable_unprepare(os04a10->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) static void __os04a10_power_off(struct os04a10 *os04a10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) struct device *dev = &os04a10->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) if (os04a10->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) if (os04a10->is_first_streamoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) os04a10->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) os04a10->is_first_streamoff = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (!IS_ERR(os04a10->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) gpiod_direction_output(os04a10->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) clk_disable_unprepare(os04a10->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) if (!IS_ERR(os04a10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) gpiod_direction_output(os04a10->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) if (!IS_ERR_OR_NULL(os04a10->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) ret = pinctrl_select_state(os04a10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) os04a10->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) if (os04a10->is_thunderboot_ng) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) os04a10->is_thunderboot_ng = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) regulator_bulk_disable(OS04A10_NUM_SUPPLIES, os04a10->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) usleep_range(30000, 31000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) static int os04a10_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) return __os04a10_power_on(os04a10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) static int os04a10_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) __os04a10_power_off(os04a10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) static int os04a10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) const struct os04a10_mode *def_mode = &os04a10->supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) mutex_lock(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) mutex_unlock(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) static int os04a10_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) if (fie->index >= os04a10->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) fie->code = os04a10->supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) fie->width = os04a10->supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) fie->height = os04a10->supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) fie->interval = os04a10->supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) fie->reserved[0] = os04a10->supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) static const struct dev_pm_ops os04a10_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) SET_RUNTIME_PM_OPS(os04a10_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) os04a10_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) static const struct v4l2_subdev_internal_ops os04a10_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .open = os04a10_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) static const struct v4l2_subdev_core_ops os04a10_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .s_power = os04a10_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .ioctl = os04a10_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .compat_ioctl32 = os04a10_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) static const struct v4l2_subdev_video_ops os04a10_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .s_stream = os04a10_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .g_frame_interval = os04a10_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) static const struct v4l2_subdev_pad_ops os04a10_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .enum_mbus_code = os04a10_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .enum_frame_size = os04a10_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .enum_frame_interval = os04a10_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .get_fmt = os04a10_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .set_fmt = os04a10_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .get_mbus_config = os04a10_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) static const struct v4l2_subdev_ops os04a10_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .core = &os04a10_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .video = &os04a10_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .pad = &os04a10_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) static int os04a10_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) struct os04a10 *os04a10 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) struct os04a10, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) struct i2c_client *client = os04a10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) u32 again, dgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) max = os04a10->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) __v4l2_ctrl_modify_range(os04a10->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) os04a10->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) os04a10->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) os04a10->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) ret = os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) OS04A10_REG_EXP_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) OS04A10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) dev_dbg(&client->dev, "set exposure 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) if (ctrl->val > 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) dgain = ctrl->val * 1024 / 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) again = 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) dgain = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) again = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) ret = os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) OS04A10_REG_AGAIN_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) OS04A10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) (again << 4) & 0x1ff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) ret |= os04a10_write_reg(os04a10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) OS04A10_REG_DGAIN_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) OS04A10_REG_VALUE_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) (dgain << 6) & 0xfffc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) dev_dbg(&client->dev, "set analog gain 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) ret = os04a10_write_reg(os04a10->client, OS04A10_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) OS04A10_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) ctrl->val + os04a10->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) dev_dbg(&client->dev, "set vblank 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) ret = os04a10_enable_test_pattern(os04a10, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) ret = os04a10_read_reg(os04a10->client, OS04A10_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) val |= MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) val &= ~MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) ret |= os04a10_write_reg(os04a10->client, OS04A10_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) os04a10->flip = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) ret = os04a10_read_reg(os04a10->client, OS04A10_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) val |= FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) val &= ~FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) ret |= os04a10_write_reg(os04a10->client, OS04A10_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) OS04A10_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) os04a10->flip = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) static const struct v4l2_ctrl_ops os04a10_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .s_ctrl = os04a10_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) static int os04a10_initialize_controls(struct os04a10 *os04a10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) const struct os04a10_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) u8 lanes = os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) handler = &os04a10->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) mode = os04a10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) handler->lock = &os04a10->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) os04a10->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) ARRAY_SIZE(link_freq_menu_items) - 1, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) dst_link_freq = mode->link_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) mode->bpp * 2 * lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) os04a10->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) 0, PIXEL_RATE_WITH_648M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) __v4l2_ctrl_s_ctrl(os04a10->link_freq, dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) os04a10->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) if (os04a10->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) os04a10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) os04a10->vblank = v4l2_ctrl_new_std(handler, &os04a10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) OS04A10_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) os04a10->exposure = v4l2_ctrl_new_std(handler, &os04a10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) V4L2_CID_EXPOSURE, OS04A10_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) exposure_max, OS04A10_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) os04a10->anal_gain = v4l2_ctrl_new_std(handler, &os04a10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) V4L2_CID_ANALOGUE_GAIN, OS04A10_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) OS04A10_GAIN_MAX, OS04A10_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) OS04A10_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) os04a10->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) &os04a10_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) ARRAY_SIZE(os04a10_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) 0, 0, os04a10_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) os04a10->h_flip = v4l2_ctrl_new_std(handler, &os04a10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) os04a10->v_flip = v4l2_ctrl_new_std(handler, &os04a10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) os04a10->flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) dev_err(&os04a10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) os04a10->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) os04a10->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) os04a10->long_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) os04a10->middle_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) os04a10->short_hcg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) if (!os04a10->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) os04a10->is_thunderboot_ng = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) static int os04a10_check_sensor_id(struct os04a10 *os04a10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) struct device *dev = &os04a10->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) if (os04a10->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) ret = os04a10_read_reg(client, OS04A10_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) OS04A10_REG_VALUE_24BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) static int os04a10_configure_regulators(struct os04a10 *os04a10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) for (i = 0; i < OS04A10_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) os04a10->supplies[i].supply = os04a10_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) return devm_regulator_bulk_get(&os04a10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) OS04A10_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) os04a10->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) static int os04a10_get_dcg_ratio(struct os04a10 *os04a10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) struct device *dev = &os04a10->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) if (os04a10->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) ret = os04a10_read_reg(os04a10->client, 0x77fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) OS04A10_REG_VALUE_16BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) ret = os04a10_write_reg(os04a10->client, OS04A10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) OS04A10_REG_VALUE_08BIT, OS04A10_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) ret |= os04a10_read_reg(os04a10->client, 0x77fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) OS04A10_REG_VALUE_16BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) ret |= os04a10_write_reg(os04a10->client, OS04A10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) OS04A10_REG_VALUE_08BIT, OS04A10_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) if (ret != 0 || val == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) os04a10->dcg_ratio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) dev_err(dev, "get dcg ratio fail, ret %d, dcg ratio %d\n", ret, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) os04a10->dcg_ratio = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) dev_info(dev, "get dcg ratio reg val 0x%04x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) static int os04a10_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) struct os04a10 *os04a10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) os04a10 = devm_kzalloc(dev, sizeof(*os04a10), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) if (!os04a10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) &os04a10->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) &os04a10->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) &os04a10->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) &os04a10->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) os04a10->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) hdr_mode = NO_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) dev_warn(dev, " Get hdr mode failed! no hdr default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) &os04a10->bus_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) dev_err(dev, "Failed to get bus config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) if (os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) os04a10->supported_modes = supported_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) os04a10->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) dev_info(dev, "detect os04a10 lane %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) os04a10->supported_modes = supported_modes_2lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) os04a10->cfg_num = ARRAY_SIZE(supported_modes_2lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) dev_info(dev, "detect os04a10 lane %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) os04a10->bus_cfg.bus.mipi_csi2.num_data_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) for (i = 0; i < os04a10->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) os04a10->cur_mode = &os04a10->supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) os04a10->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) os04a10->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) if (IS_ERR(os04a10->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) os04a10->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) if (IS_ERR(os04a10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) os04a10->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) if (IS_ERR(os04a10->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) os04a10->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) if (!IS_ERR(os04a10->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) os04a10->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) pinctrl_lookup_state(os04a10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) if (IS_ERR(os04a10->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) os04a10->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) pinctrl_lookup_state(os04a10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) if (IS_ERR(os04a10->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) ret = os04a10_configure_regulators(os04a10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) mutex_init(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) sd = &os04a10->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) v4l2_i2c_subdev_init(sd, client, &os04a10_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) ret = os04a10_initialize_controls(os04a10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) ret = __os04a10_power_on(os04a10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) ret = os04a10_check_sensor_id(os04a10, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) ret = os04a10_get_dcg_ratio(os04a10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) dev_warn(dev, "get dcg ratio failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) sd->internal_ops = &os04a10_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) os04a10->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) ret = media_entity_pads_init(&sd->entity, 1, &os04a10->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) if (strcmp(os04a10->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) os04a10->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) OS04A10_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) add_sysfs_interfaces(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) __os04a10_power_off(os04a10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) v4l2_ctrl_handler_free(&os04a10->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) mutex_destroy(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) static int os04a10_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) struct os04a10 *os04a10 = to_os04a10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) v4l2_ctrl_handler_free(&os04a10->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) mutex_destroy(&os04a10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) __os04a10_power_off(os04a10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) static const struct of_device_id os04a10_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) { .compatible = "ovti,os04a10" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) MODULE_DEVICE_TABLE(of, os04a10_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) static const struct i2c_device_id os04a10_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) { "ovti,os04a10", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) static struct i2c_driver os04a10_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) .name = OS04A10_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) .pm = &os04a10_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) .of_match_table = of_match_ptr(os04a10_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) .probe = &os04a10_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) .remove = &os04a10_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) .id_table = os04a10_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) module_i2c_driver(os04a10_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) return i2c_add_driver(&os04a10_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) i2c_del_driver(&os04a10_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) MODULE_DESCRIPTION("OmniVision os04a10 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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