^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * os03b10 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) //define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "../platform/rockchip/isp/rkisp_tb_helper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OS03B10_CHIP_ID 0x5303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OS03B10_REG_CHIP_ID_H 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OS03B10_REG_CHIP_ID_L 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OS03B10_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MIPI_FREQ_270M 270000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OS03B10_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PIXEL_RATE_WITH_270M (MIPI_FREQ_270M * OS03B10_LANES * 2 / BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OS03B10_REG_PAGE_SELECT 0xfd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OS03B10_REG_EXP_H 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OS03B10_REG_EXP_L 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OS03B10_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OS03B10_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OS03B10_REG_AGAIN 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OS03B10_REG_DGAIN_H 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OS03B10_REG_DGAIN_L 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OS03B10_GAIN_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OS03B10_GAIN_MAX 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OS03B10_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OS03B10_GAIN_DEFAULT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OS03B10_REG_HTS_H 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OS03B10_REG_HTS_L 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OS03B10_REG_VTS_H 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OS03B10_REG_VTS_L 0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OS03B10_REG_VBLANK_H 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OS03B10_REG_VBLANK_L 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OS03B10_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OS03B10_REG_RESTART 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OS03B10_REG_CTRL_MODE 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OS03B10_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OS03B10_MODE_STREAMING 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OS03B10_REG_SOFTWARE_RESET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OS03B10_SOFTWARE_RESET_VAL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OS03B10_FLIP_REG 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MIRROR_BIT_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define FLIP_BIT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OS03B10_REG_BAYER_ORDER 0x5e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OS03B10_FETCH_EXP_H(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OS03B10_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OS03B10_FETCH_AGAIN(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OS03B10_FETCH_DGAIN_H(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OS03B10_FETCH_DGAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OS03B10_NAME "os03b10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define REG_DELAY 0xEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define REG_NULL 0xEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const char * const OS03B10_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OS03B10_NUM_SUPPLIES ARRAY_SIZE(OS03B10_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct os03b10_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct os03b10 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct regulator_bulk_data supplies[OS03B10_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const struct os03b10_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define to_os03b10(sd) container_of(sd, struct os03b10, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct regval os03b10_linear10bit_2304x1296_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0xfd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x20, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0xfd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x36, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0xfd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x2e, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x2f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x41, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x36, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0xfd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0xfd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0xfd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0xfd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {REG_DELAY, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0xfd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0xfd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x44, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x38, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x45, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x04, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x24, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x18, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x1a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x19, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x1b, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x2e, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x2f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x30, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3c, 0xca},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0xfd, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x01, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x51, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x52, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x57, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x5a, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x66, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x6e, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x71, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x73, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0xb8, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0xd0, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0xd2, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0xd3, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0xbd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0xd7, 0xbe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0xd8, 0xef},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0xe8, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0xe9, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0xea, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0xeb, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0xfd, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x00, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x03, 0xcd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x06, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x07, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x08, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x09, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x0a, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x0b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x0f, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x1d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x1e, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x1f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x20, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0xbc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0xfd, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x05, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0xfd, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x5e, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x34, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0xf0, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0xf1, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0xf2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0xf3, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0xfa, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0xfb, 0x6b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0xf6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0xf7, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0xfc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0xfe, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0xff, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0xc4, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0xc5, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0xc6, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0xc7, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0xce, 0x7c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x8f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x91, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x92, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x94, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x95, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x98, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x9d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x9e, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0xa4, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0xa5, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0xa6, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x01, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x14, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * The width and height must be configured to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * the same as the current output resolution of the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * The input width of the isp needs to be 16 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * The input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * If the width or height does not meet the alignment rules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * you can configure the cropping parameters with the following function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * crop out the appropriate resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * struct v4l2_subdev_pad_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * .get_selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct os03b10_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .width = 2304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .height = 1296,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .exp_def = 0x044c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .hts_def = 0x054e * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .vts_def = 0x052d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .reg_list = os03b10_linear10bit_2304x1296_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MIPI_FREQ_270M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* sensor register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int os03b10_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int os03b10_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = os03b10_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (regs[i].addr == REG_DELAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) usleep_range(5 * 1000, 6 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(&client->dev, "%s failed !\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* sensor register read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int os03b10_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "os03b10 read reg(0x%x val:0x%x) failed !\n", reg, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int os03b10_get_reso_dist(const struct os03b10_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct os03b10_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) os03b10_find_best_fit(struct os03b10 *os03b10, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) for (i = 0; i < os03b10->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dist = os03b10_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) (supported_modes[i].bus_fmt == framefmt->code)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int os03b10_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct os03b10 *os03b10 = to_os03b10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) const struct os03b10_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mutex_lock(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) mode = os03b10_find_best_fit(os03b10, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mutex_unlock(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) os03b10->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) __v4l2_ctrl_modify_range(os03b10->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) __v4l2_ctrl_modify_range(os03b10->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) OS03B10_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dst_pixel_rate = PIXEL_RATE_WITH_270M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) __v4l2_ctrl_s_ctrl_int64(os03b10->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) __v4l2_ctrl_s_ctrl(os03b10->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mutex_unlock(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int os03b10_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct os03b10 *os03b10 = to_os03b10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) const struct os03b10_mode *mode = os03b10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mutex_lock(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) mutex_unlock(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mutex_unlock(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int os03b10_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct os03b10 *os03b10 = to_os03b10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) code->code = os03b10->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int os03b10_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct os03b10 *os03b10 = to_os03b10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (fse->index >= os03b10->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int os03b10_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct os03b10 *os03b10 = to_os03b10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) const struct os03b10_mode *mode = os03b10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mutex_lock(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mutex_unlock(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int os03b10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct os03b10 *os03b10 = to_os03b10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) const struct os03b10_mode *mode = os03b10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) val = 1 << (OS03B10_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static void os03b10_get_module_inf(struct os03b10 *os03b10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) strscpy(inf->base.sensor, OS03B10_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) strscpy(inf->base.module, os03b10->module_name, sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) strscpy(inf->base.lens, os03b10->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static long os03b10_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct os03b10 *os03b10 = to_os03b10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct rkmodule_hdr_cfg *hdr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) os03b10_get_module_inf(os03b10, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (hdr_cfg->hdr_mode != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) hdr_cfg->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) hdr_cfg->hdr_mode = os03b10->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ret = os03b10_write_reg(os03b10->client, OS03B10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) OS03B10_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret = os03b10_write_reg(os03b10->client, OS03B10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) OS03B10_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static long os03b10_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = os03b10_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret = os03b10_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (copy_from_user(hdr, up, sizeof(*hdr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = os03b10_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (copy_from_user(&stream, up, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = os03b10_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int __os03b10_start_stream(struct os03b10 *os03b10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ret |= os03b10_write_array(os03b10->client, os03b10->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dev_err(&os03b10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) "write array failed in start stream\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ret = __v4l2_ctrl_handler_setup(&os03b10->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (os03b10->has_init_exp && os03b10->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret = os03b10_ioctl(&os03b10->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) &os03b10->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_err(&os03b10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ret |= os03b10_write_reg(os03b10->client, OS03B10_REG_PAGE_SELECT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret |= os03b10_write_reg(os03b10->client, OS03B10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) OS03B10_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static int __os03b10_stop_stream(struct os03b10 *os03b10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) os03b10->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return os03b10_write_reg(os03b10->client, OS03B10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) OS03B10_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static int os03b10_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct os03b10 *os03b10 = to_os03b10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct i2c_client *client = os03b10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) mutex_lock(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (on == os03b10->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ret = __os03b10_start_stream(os03b10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) __os03b10_stop_stream(os03b10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) os03b10->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mutex_unlock(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int os03b10_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct os03b10 *os03b10 = to_os03b10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct i2c_client *client = os03b10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) mutex_lock(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (os03b10->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) OS03B10_REG_SOFTWARE_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) OS03B10_SOFTWARE_RESET_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) os03b10->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) os03b10->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) mutex_unlock(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static int __os03b10_power_on(struct os03b10 *os03b10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct device *dev = &os03b10->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (!IS_ERR_OR_NULL(os03b10->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ret = pinctrl_select_state(os03b10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) os03b10->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = clk_set_rate(os03b10->xvclk, OS03B10_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (clk_get_rate(os03b10->xvclk) != OS03B10_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = clk_prepare_enable(os03b10->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (!IS_ERR(os03b10->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) gpiod_direction_output(os03b10->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (!IS_ERR(os03b10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) gpiod_direction_output(os03b10->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ret = regulator_bulk_enable(OS03B10_NUM_SUPPLIES, os03b10->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* From spec: delay from power stable to pwdn off: 5ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (!IS_ERR(os03b10->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) gpiod_direction_output(os03b10->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* From spec: delay from pwdn off to reset off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) usleep_range(4000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!IS_ERR(os03b10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) gpiod_direction_output(os03b10->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* From spec: 5ms for SCCB initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) usleep_range(9000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) clk_disable_unprepare(os03b10->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static void __os03b10_power_off(struct os03b10 *os03b10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct device *dev = &os03b10->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (!IS_ERR(os03b10->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) gpiod_direction_output(os03b10->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) clk_disable_unprepare(os03b10->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (!IS_ERR(os03b10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) gpiod_direction_output(os03b10->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (!IS_ERR_OR_NULL(os03b10->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ret = pinctrl_select_state(os03b10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) os03b10->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) regulator_bulk_disable(OS03B10_NUM_SUPPLIES, os03b10->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int os03b10_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct os03b10 *os03b10 = to_os03b10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return __os03b10_power_on(os03b10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static int os03b10_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct os03b10 *os03b10 = to_os03b10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) __os03b10_power_off(os03b10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static int os03b10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct os03b10 *os03b10 = to_os03b10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) const struct os03b10_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) mutex_lock(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) mutex_unlock(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static int os03b10_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct os03b10 *os03b10 = to_os03b10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (fie->index >= os03b10->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static const struct dev_pm_ops os03b10_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) SET_RUNTIME_PM_OPS(os03b10_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) os03b10_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static const struct v4l2_subdev_internal_ops os03b10_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .open = os03b10_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static const struct v4l2_subdev_core_ops os03b10_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .s_power = os03b10_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .ioctl = os03b10_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .compat_ioctl32 = os03b10_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static const struct v4l2_subdev_video_ops os03b10_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .s_stream = os03b10_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .g_frame_interval = os03b10_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static const struct v4l2_subdev_pad_ops os03b10_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .enum_mbus_code = os03b10_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .enum_frame_size = os03b10_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .enum_frame_interval = os03b10_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .get_fmt = os03b10_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .set_fmt = os03b10_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .get_mbus_config = os03b10_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static const struct v4l2_subdev_ops os03b10_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .core = &os03b10_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .video = &os03b10_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .pad = &os03b10_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static void os03b10_get_gain_reg(u32 total_gain, u32 *again, u32 *dgain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u32 step = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (total_gain < 256) {/* 1x gain ~ 16x gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) *again = total_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) *dgain = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) } else if (total_gain < 512) {/* 16x gain ~ 32x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) step = (total_gain - 256) * 0x40 / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) *again = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) *dgain = 0x40 + step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) } else if (total_gain < 1024) {/* 32x gain ~ 64x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) step = (total_gain - 512) * 0x80 / 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) *again = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) *dgain = 0x80 + step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) } else if (total_gain < 2048) {/* 64x gain ~ 128x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) step = (total_gain - 1024) * 0x100 / 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) *again = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) *dgain = 0x100 + step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) } else if (total_gain < 4096) {/* 128x gain ~ 256x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) step = (total_gain - 2048) * 0x200 / 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) *again = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) *dgain = 0x200 + step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) } else if (total_gain <= 8192) {/* 256x gain ~ 512x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) step = (total_gain - 4096) * 0x400 / 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) *again = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) *dgain = (0x400 + step) > 0x7ff ? 0x7ff : (0x400 + step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static int os03b10_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct os03b10 *os03b10 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct os03b10, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct i2c_client *client = os03b10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) u32 again = 0, dgain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) max = os03b10->cur_mode->height + ctrl->val - 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) __v4l2_ctrl_modify_range(os03b10->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) os03b10->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) os03b10->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) os03b10->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ret = os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) OS03B10_REG_PAGE_SELECT, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) OS03B10_REG_EXP_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) OS03B10_FETCH_EXP_H(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) OS03B10_REG_EXP_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) OS03B10_FETCH_EXP_L(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) OS03B10_REG_RESTART, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) os03b10_get_gain_reg(ctrl->val, &again, &dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ret = os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) OS03B10_REG_PAGE_SELECT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) OS03B10_REG_AGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) OS03B10_FETCH_AGAIN(again));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) OS03B10_REG_DGAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) OS03B10_FETCH_DGAIN_H(dgain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) OS03B10_REG_DGAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) OS03B10_FETCH_DGAIN_L(dgain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) OS03B10_REG_RESTART, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dev_dbg(&client->dev, "set gain 0x%x, again 0x%x, dgain 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ctrl->val, again, dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ret = os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) OS03B10_REG_PAGE_SELECT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) OS03B10_REG_VBLANK_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) (ctrl->val >> 8) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) OS03B10_REG_VBLANK_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ctrl->val & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) OS03B10_REG_RESTART, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) os03b10->flip |= MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) os03b10->flip &= ~MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ret = os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) OS03B10_REG_PAGE_SELECT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) OS03B10_FLIP_REG, os03b10->flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) OS03B10_REG_PAGE_SELECT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) OS03B10_REG_BAYER_ORDER, 0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) OS03B10_REG_PAGE_SELECT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) OS03B10_REG_RESTART, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) dev_dbg(&client->dev, "set hflip 0x%x\n", os03b10->flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) os03b10->flip |= FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) os03b10->flip &= ~FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ret = os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) OS03B10_REG_PAGE_SELECT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) OS03B10_FLIP_REG, os03b10->flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) OS03B10_REG_PAGE_SELECT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) OS03B10_REG_BAYER_ORDER, 0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) OS03B10_REG_PAGE_SELECT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ret |= os03b10_write_reg(os03b10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) OS03B10_REG_RESTART, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) dev_dbg(&client->dev, "set vflip 0x%x\n", os03b10->flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static const struct v4l2_ctrl_ops os03b10_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .s_ctrl = os03b10_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static int os03b10_initialize_controls(struct os03b10 *os03b10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) const struct os03b10_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) handler = &os03b10->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) mode = os03b10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) handler->lock = &os03b10->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) os03b10->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (os03b10->cur_mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) dst_pixel_rate = PIXEL_RATE_WITH_270M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) os03b10->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) 0, PIXEL_RATE_WITH_270M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) __v4l2_ctrl_s_ctrl(os03b10->link_freq, dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) os03b10->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (os03b10->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) os03b10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) vblank_def = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) os03b10->vblank = v4l2_ctrl_new_std(handler, &os03b10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) OS03B10_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) exposure_max = mode->vts_def - 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) os03b10->exposure = v4l2_ctrl_new_std(handler, &os03b10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) V4L2_CID_EXPOSURE, OS03B10_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) exposure_max, OS03B10_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) os03b10->anal_gain = v4l2_ctrl_new_std(handler, &os03b10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) V4L2_CID_ANALOGUE_GAIN, OS03B10_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) OS03B10_GAIN_MAX, OS03B10_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) OS03B10_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) v4l2_ctrl_new_std(handler, &os03b10_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) v4l2_ctrl_new_std(handler, &os03b10_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) os03b10->flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) dev_err(&os03b10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) os03b10->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) os03b10->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static int os03b10_check_sensor_id(struct os03b10 *os03b10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct device *dev = &os03b10->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) u8 id_h = 0, id_l = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ret = os03b10_read_reg(client, OS03B10_REG_CHIP_ID_H, &id_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ret |= os03b10_read_reg(client, OS03B10_REG_CHIP_ID_L, &id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) id = SENSOR_ID(id_h, id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (id != OS03B10_CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dev_info(dev, "Detected OV%06x sensor\n", OS03B10_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static int os03b10_configure_regulators(struct os03b10 *os03b10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) for (i = 0; i < OS03B10_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) os03b10->supplies[i].supply = OS03B10_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return devm_regulator_bulk_get(&os03b10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) OS03B10_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) os03b10->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static int os03b10_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct os03b10 *os03b10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) os03b10 = devm_kzalloc(dev, sizeof(*os03b10), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (!os03b10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) &os03b10->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) &os03b10->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) &os03b10->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) &os03b10->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) hdr_mode = NO_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dev_warn(dev, " Get hdr mode failed! no hdr default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) os03b10->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) for (i = 0; i < os03b10->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) os03b10->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) os03b10->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) os03b10->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (IS_ERR(os03b10->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) os03b10->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (IS_ERR(os03b10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) os03b10->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (IS_ERR(os03b10->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) os03b10->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (!IS_ERR(os03b10->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) os03b10->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) pinctrl_lookup_state(os03b10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (IS_ERR(os03b10->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) os03b10->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) pinctrl_lookup_state(os03b10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (IS_ERR(os03b10->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) ret = os03b10_configure_regulators(os03b10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) mutex_init(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) sd = &os03b10->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) v4l2_i2c_subdev_init(sd, client, &os03b10_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) ret = os03b10_initialize_controls(os03b10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ret = __os03b10_power_on(os03b10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ret = os03b10_check_sensor_id(os03b10, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) sd->internal_ops = &os03b10_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) os03b10->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ret = media_entity_pads_init(&sd->entity, 1, &os03b10->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (strcmp(os03b10->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) os03b10->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) OS03B10_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) __os03b10_power_off(os03b10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) v4l2_ctrl_handler_free(&os03b10->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) mutex_destroy(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static int os03b10_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) struct os03b10 *os03b10 = to_os03b10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) v4l2_ctrl_handler_free(&os03b10->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) mutex_destroy(&os03b10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) __os03b10_power_off(os03b10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static const struct of_device_id os03b10_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) { .compatible = "ovti,os03b10" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) MODULE_DEVICE_TABLE(of, os03b10_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static const struct i2c_device_id os03b10_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) { "ovti,os03b10", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static struct i2c_driver os03b10_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .name = OS03B10_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .pm = &os03b10_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .of_match_table = of_match_ptr(os03b10_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .probe = &os03b10_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .remove = &os03b10_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .id_table = os03b10_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return i2c_add_driver(&os03b10_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) i2c_del_driver(&os03b10_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) MODULE_DESCRIPTION("OmniVision os03b10 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags