^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * os02g10 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 update init setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X02 fix set flip/mirror failed bug and fix wrong vts_def value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "../platform/rockchip/isp/rkisp_tb_helper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OS02G10_CHIP_ID 0x5602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OS02G10_REG_CHIP_ID_H 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OS02G10_REG_CHIP_ID_L 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OS02G10_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MIPI_FREQ_360M 360000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OS02G10_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PIXEL_RATE_WITH_360M (MIPI_FREQ_360M * OS02G10_LANES * 2 / BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OS02G10_REG_PAGE_SELECT 0xfd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OS02G10_REG_EXP_H 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OS02G10_REG_EXP_L 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OS02G10_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OS02G10_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OS02G10_REG_AGAIN 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OS02G10_REG_DGAIN_H 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OS02G10_REG_DGAIN_L 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OS02G10_GAIN_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OS02G10_GAIN_MAX 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OS02G10_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OS02G10_GAIN_DEFAULT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OS02G10_REG_HTS_H 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OS02G10_REG_HTS_L 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OS02G10_REG_VTS_H 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OS02G10_REG_VTS_L 0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OS02G10_REG_VBLANK_H 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OS02G10_REG_VBLANK_L 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OS02G10_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OS02G10_REG_RESTART 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OS02G10_REG_CTRL_MODE 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OS02G10_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OS02G10_MODE_STREAMING 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OS02G10_REG_SOFTWARE_RESET 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OS02G10_SOFTWARE_RESET_VAL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OS02G10_FLIP_REG 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MIRROR_BIT_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define FLIP_BIT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OS02G10_REG_BAYER_ORDER 0x5e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OS02G10_NAME "os02g10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define REG_NULL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const char * const OS02G10_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OS02G10_NUM_SUPPLIES ARRAY_SIZE(OS02G10_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct os02g10_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct os02g10 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct regulator_bulk_data supplies[OS02G10_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const struct os02g10_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define to_os02g10(sd) container_of(sd, struct os02g10, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct regval os02g10_linear10bit_1920x1080_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0xfd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0xfd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x30, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x35, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x38, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x41, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x44, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x03, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x04, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x24, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x19, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x1a, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x1b, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x1c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x1d, 0x75},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x1e, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x22, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x25, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x26, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x3c, 0xca},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3d, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x40, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x43, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x46, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x47, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x49, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x50, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x51, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x52, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x53, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x57, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x59, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x5a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x5d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x6a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x6b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x6e, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x71, 0xbe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x72, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x73, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x74, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x79, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x7a, 0xb2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x7b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x8f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x91, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x92, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x9d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x9e, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0xb8, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0xb9, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0xba, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0xbb, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0xbc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0xc0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0xc1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0xc2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0xc3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0xc4, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0xc5, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0xc6, 0x6b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0xc7, 0x6b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0xcc, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0xcd, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0xd0, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0xd2, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0xd3, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0xd4, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0xd5, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0xd6, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0xe8, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0xf0, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0xf1, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0xf2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0xf3, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0xf4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0xfa, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0xfb, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0xfc, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0xfd, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x03, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x00, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x04, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x05, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x06, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x07, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x08, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x09, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x0b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x0d, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x0f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0xfd, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x34, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x5e, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0xa1, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0xa3, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0xa5, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0xa7, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0xa1, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x94, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x95, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x96, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x98, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x9c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0xb1, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0xfd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * The width and height must be configured to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * the same as the current output resolution of the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * The input width of the isp needs to be 16 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * The input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * If the width or height does not meet the alignment rules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * you can configure the cropping parameters with the following function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * crop out the appropriate resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * struct v4l2_subdev_pad_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * .get_selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct os02g10_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .exp_def = 0x044c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .hts_def = 0x043a * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .vts_def = 0x0516,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .reg_list = os02g10_linear10bit_1920x1080_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MIPI_FREQ_360M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* sensor register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int os02g10_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dev_err(&client->dev, "write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int os02g10_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) while (regs[i].addr != REG_NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = os02g10_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_err(&client->dev, "%s failed !\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* sensor register read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int os02g10_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "os02g10 read reg(0x%x val:0x%x) failed !\n", reg, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int os02g10_get_reso_dist(const struct os02g10_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct os02g10_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) os02g10_find_best_fit(struct os02g10 *os02g10, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) for (i = 0; i < os02g10->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dist = os02g10_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) (supported_modes[i].bus_fmt == framefmt->code)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int os02g10_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct os02g10 *os02g10 = to_os02g10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) const struct os02g10_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) mutex_lock(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mode = os02g10_find_best_fit(os02g10, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mutex_unlock(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) os02g10->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) __v4l2_ctrl_modify_range(os02g10->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) __v4l2_ctrl_modify_range(os02g10->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) OS02G10_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dst_pixel_rate = PIXEL_RATE_WITH_360M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) __v4l2_ctrl_s_ctrl_int64(os02g10->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) __v4l2_ctrl_s_ctrl(os02g10->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) mutex_unlock(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int os02g10_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct os02g10 *os02g10 = to_os02g10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) const struct os02g10_mode *mode = os02g10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mutex_lock(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) mutex_unlock(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) mutex_unlock(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int os02g10_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct os02g10 *os02g10 = to_os02g10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) code->code = os02g10->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int os02g10_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct os02g10 *os02g10 = to_os02g10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (fse->index >= os02g10->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int os02g10_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct os02g10 *os02g10 = to_os02g10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) const struct os02g10_mode *mode = os02g10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) mutex_lock(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mutex_unlock(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int os02g10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct os02g10 *os02g10 = to_os02g10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) const struct os02g10_mode *mode = os02g10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) val = 1 << (OS02G10_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static void os02g10_get_module_inf(struct os02g10 *os02g10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) strscpy(inf->base.sensor, OS02G10_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) strscpy(inf->base.module, os02g10->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) strscpy(inf->base.lens, os02g10->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static long os02g10_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct os02g10 *os02g10 = to_os02g10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct rkmodule_hdr_cfg *hdr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) os02g10_get_module_inf(os02g10, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (hdr_cfg->hdr_mode != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) hdr_cfg->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) hdr_cfg->hdr_mode = os02g10->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ret = os02g10_write_reg(os02g10->client, OS02G10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) OS02G10_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ret = os02g10_write_reg(os02g10->client, OS02G10_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) OS02G10_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static long os02g10_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ret = os02g10_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret = os02g10_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (copy_from_user(hdr, up, sizeof(*hdr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ret = os02g10_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (copy_from_user(&stream, up, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = os02g10_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int __os02g10_start_stream(struct os02g10 *os02g10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret |= os02g10_write_reg(os02g10->client, 0xfd, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ret |= os02g10_write_reg(os02g10->client, 0x36, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret |= os02g10_write_reg(os02g10->client, 0xfd, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret |= os02g10_write_reg(os02g10->client, 0x36, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ret |= os02g10_write_reg(os02g10->client, 0xfd, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret |= os02g10_write_array(os02g10->client, os02g10->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ret = __v4l2_ctrl_handler_setup(&os02g10->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (os02g10->has_init_exp && os02g10->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = os02g10_ioctl(&os02g10->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) &os02g10->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev_err(&os02g10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return os02g10_write_reg(os02g10->client, OS02G10_REG_CTRL_MODE, OS02G10_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int __os02g10_stop_stream(struct os02g10 *os02g10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) os02g10->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return os02g10_write_reg(os02g10->client, OS02G10_REG_CTRL_MODE, OS02G10_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int os02g10_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct os02g10 *os02g10 = to_os02g10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct i2c_client *client = os02g10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) mutex_lock(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (on == os02g10->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = __os02g10_start_stream(os02g10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) __os02g10_stop_stream(os02g10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) os02g10->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) mutex_unlock(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static int os02g10_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct os02g10 *os02g10 = to_os02g10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct i2c_client *client = os02g10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) mutex_lock(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (os02g10->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) OS02G10_REG_SOFTWARE_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) OS02G10_SOFTWARE_RESET_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) os02g10->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) os02g10->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) mutex_unlock(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int __os02g10_power_on(struct os02g10 *os02g10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct device *dev = &os02g10->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!IS_ERR_OR_NULL(os02g10->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ret = pinctrl_select_state(os02g10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) os02g10->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = clk_set_rate(os02g10->xvclk, OS02G10_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (clk_get_rate(os02g10->xvclk) != OS02G10_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ret = clk_prepare_enable(os02g10->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (!IS_ERR(os02g10->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) gpiod_direction_output(os02g10->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (!IS_ERR(os02g10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) gpiod_direction_output(os02g10->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ret = regulator_bulk_enable(OS02G10_NUM_SUPPLIES, os02g10->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* From spec: delay from power stable to pwdn off: 5ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!IS_ERR(os02g10->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) gpiod_direction_output(os02g10->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* From spec: delay from pwdn off to reset off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) usleep_range(4000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!IS_ERR(os02g10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) gpiod_direction_output(os02g10->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* From spec: 5ms for SCCB initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) usleep_range(9000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) clk_disable_unprepare(os02g10->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static void __os02g10_power_off(struct os02g10 *os02g10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct device *dev = &os02g10->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (!IS_ERR(os02g10->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) gpiod_direction_output(os02g10->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) clk_disable_unprepare(os02g10->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (!IS_ERR(os02g10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) gpiod_direction_output(os02g10->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (!IS_ERR_OR_NULL(os02g10->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ret = pinctrl_select_state(os02g10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) os02g10->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) regulator_bulk_disable(OS02G10_NUM_SUPPLIES, os02g10->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static int os02g10_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct os02g10 *os02g10 = to_os02g10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return __os02g10_power_on(os02g10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static int os02g10_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct os02g10 *os02g10 = to_os02g10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) __os02g10_power_off(os02g10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static int os02g10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct os02g10 *os02g10 = to_os02g10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) const struct os02g10_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mutex_lock(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) mutex_unlock(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static int os02g10_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct os02g10 *os02g10 = to_os02g10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (fie->index >= os02g10->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const struct dev_pm_ops os02g10_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) SET_RUNTIME_PM_OPS(os02g10_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) os02g10_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static const struct v4l2_subdev_internal_ops os02g10_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .open = os02g10_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static const struct v4l2_subdev_core_ops os02g10_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .s_power = os02g10_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .ioctl = os02g10_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .compat_ioctl32 = os02g10_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static const struct v4l2_subdev_video_ops os02g10_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .s_stream = os02g10_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .g_frame_interval = os02g10_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static const struct v4l2_subdev_pad_ops os02g10_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .enum_mbus_code = os02g10_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .enum_frame_size = os02g10_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .enum_frame_interval = os02g10_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .get_fmt = os02g10_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .set_fmt = os02g10_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .get_mbus_config = os02g10_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static const struct v4l2_subdev_ops os02g10_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .core = &os02g10_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .video = &os02g10_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .pad = &os02g10_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static void os02g10_get_gain_reg(u32 total_gain, u32* again, u32* dgain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) u32 step = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (total_gain < 256) { /* 1x gain ~ 16x gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) *again = total_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) *dgain = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) } else if (total_gain < 512) { /* 16x gain ~ 32x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) step = (total_gain - 256) * 0x40 / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) *again = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) *dgain = 0x40 + step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) } else if (total_gain < 1024) { /* 32x gain ~ 64x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) step = (total_gain - 512) * 0x80 / 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) *again = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) *dgain = 0x80 + step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) } else if (total_gain < 2048) { /* 64x gain ~ 128x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) step = (total_gain - 1024) * 0x100 / 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) *again = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) *dgain = 0x100 + step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) } else if (total_gain < 4096) { /* 128x gain ~ 256x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) step = (total_gain - 2048) * 0x200 / 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) *again = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) *dgain = 0x200 + step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) } else if (total_gain <= 8192) { /* 256x gain ~ 512x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) step = (total_gain - 4096) * 0x400 / 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) *again = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) *dgain = (0x400 + step) > 0x7ff ? 0x7ff : (0x400 + step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static int os02g10_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct os02g10 *os02g10 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct os02g10, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct i2c_client *client = os02g10->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) u32 again = 0, dgain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) max = os02g10->cur_mode->height + ctrl->val - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) __v4l2_ctrl_modify_range(os02g10->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) os02g10->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) os02g10->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) os02g10->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ret = os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) OS02G10_REG_PAGE_SELECT, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) OS02G10_REG_EXP_H, (ctrl->val >> 8) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) OS02G10_REG_EXP_L, ctrl->val & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) OS02G10_REG_RESTART, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) os02g10_get_gain_reg(ctrl->val, &again, &dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ret = os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) OS02G10_REG_PAGE_SELECT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) OS02G10_REG_AGAIN, again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) OS02G10_REG_DGAIN_H, dgain >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) OS02G10_REG_DGAIN_L, (dgain & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) OS02G10_REG_RESTART, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dev_dbg(&client->dev, "set gain 0x%x, again = %#x(%u), dgain = %#x(%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ctrl->val, again, again, dgain, dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ret = os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) OS02G10_REG_PAGE_SELECT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) OS02G10_REG_VBLANK_H, (ctrl->val >> 8) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) OS02G10_REG_VBLANK_L, ctrl->val & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) OS02G10_REG_RESTART, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) os02g10->flip |= MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) os02g10->flip &= ~MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ret = os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) OS02G10_REG_PAGE_SELECT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) OS02G10_FLIP_REG, os02g10->flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) OS02G10_REG_PAGE_SELECT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) OS02G10_REG_BAYER_ORDER, 0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) OS02G10_REG_PAGE_SELECT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) OS02G10_REG_RESTART, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) dev_dbg(&client->dev, "set hflip 0x%x\n", os02g10->flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) os02g10->flip |= FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) os02g10->flip &= ~FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ret = os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) OS02G10_REG_PAGE_SELECT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) OS02G10_FLIP_REG, os02g10->flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) OS02G10_REG_PAGE_SELECT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) OS02G10_REG_BAYER_ORDER, 0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) OS02G10_REG_PAGE_SELECT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ret |= os02g10_write_reg(os02g10->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) OS02G10_REG_RESTART, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) dev_dbg(&client->dev, "set vflip 0x%x\n", os02g10->flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static const struct v4l2_ctrl_ops os02g10_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .s_ctrl = os02g10_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static int os02g10_initialize_controls(struct os02g10 *os02g10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) const struct os02g10_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) handler = &os02g10->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) mode = os02g10->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) handler->lock = &os02g10->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) os02g10->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (os02g10->cur_mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) dst_pixel_rate = PIXEL_RATE_WITH_360M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) os02g10->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) 0, PIXEL_RATE_WITH_360M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) __v4l2_ctrl_s_ctrl(os02g10->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) os02g10->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (os02g10->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) os02g10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) os02g10->vblank = v4l2_ctrl_new_std(handler, &os02g10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) OS02G10_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) exposure_max = mode->vts_def - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) os02g10->exposure = v4l2_ctrl_new_std(handler, &os02g10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) V4L2_CID_EXPOSURE, OS02G10_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) exposure_max, OS02G10_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) os02g10->anal_gain = v4l2_ctrl_new_std(handler, &os02g10_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) V4L2_CID_ANALOGUE_GAIN, OS02G10_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) OS02G10_GAIN_MAX, OS02G10_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) OS02G10_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) v4l2_ctrl_new_std(handler, &os02g10_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) v4l2_ctrl_new_std(handler, &os02g10_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) os02g10->flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) dev_err(&os02g10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) os02g10->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) os02g10->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static int os02g10_check_sensor_id(struct os02g10 *os02g10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct device *dev = &os02g10->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) u8 id_h = 0, id_l = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ret = os02g10_read_reg(client, OS02G10_REG_CHIP_ID_H, &id_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ret |= os02g10_read_reg(client, OS02G10_REG_CHIP_ID_L, &id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) id = SENSOR_ID(id_h, id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (id != OS02G10_CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) dev_info(dev, "Detected OV%06x sensor\n", OS02G10_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static int os02g10_configure_regulators(struct os02g10 *os02g10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) for (i = 0; i < OS02G10_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) os02g10->supplies[i].supply = OS02G10_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return devm_regulator_bulk_get(&os02g10->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) OS02G10_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) os02g10->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static int os02g10_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct os02g10 *os02g10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) os02g10 = devm_kzalloc(dev, sizeof(*os02g10), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (!os02g10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) &os02g10->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) &os02g10->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) &os02g10->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) &os02g10->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) hdr_mode = NO_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dev_warn(dev, " Get hdr mode failed! no hdr default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) os02g10->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) for (i = 0; i < os02g10->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) os02g10->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) os02g10->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) os02g10->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (IS_ERR(os02g10->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) os02g10->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (IS_ERR(os02g10->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) os02g10->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (IS_ERR(os02g10->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) os02g10->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (!IS_ERR(os02g10->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) os02g10->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) pinctrl_lookup_state(os02g10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (IS_ERR(os02g10->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) os02g10->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) pinctrl_lookup_state(os02g10->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (IS_ERR(os02g10->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ret = os02g10_configure_regulators(os02g10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) mutex_init(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) sd = &os02g10->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) v4l2_i2c_subdev_init(sd, client, &os02g10_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ret = os02g10_initialize_controls(os02g10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) ret = __os02g10_power_on(os02g10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ret = os02g10_check_sensor_id(os02g10, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) sd->internal_ops = &os02g10_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) os02g10->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ret = media_entity_pads_init(&sd->entity, 1, &os02g10->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (strcmp(os02g10->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) os02g10->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) OS02G10_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) __os02g10_power_off(os02g10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) v4l2_ctrl_handler_free(&os02g10->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) mutex_destroy(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static int os02g10_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) struct os02g10 *os02g10 = to_os02g10(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) v4l2_ctrl_handler_free(&os02g10->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) mutex_destroy(&os02g10->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) __os02g10_power_off(os02g10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static const struct of_device_id os02g10_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) { .compatible = "ovti,os02g10" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) MODULE_DEVICE_TABLE(of, os02g10_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static const struct i2c_device_id os02g10_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) { "ovti,os02g10", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static struct i2c_driver os02g10_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .name = OS02G10_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .pm = &os02g10_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .of_match_table = of_match_ptr(os02g10_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .probe = &os02g10_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .remove = &os02g10_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .id_table = os02g10_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) module_i2c_driver(os02g10_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return i2c_add_driver(&os02g10_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) i2c_del_driver(&os02g10_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) MODULE_DESCRIPTION("OmniVision os02g10 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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