^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * nvp6188 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 1. add get virtual channel fmt ioctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2. add get virtual channel hotplug status ioctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 3. add virtual channel hotplug status event report to vicap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * 4. fixup variables are reused when multiple devices use the same driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * V0.0X01.0X02 add quick stream support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NVP6188_XVCLK_FREQ 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define NVP6188_LINK_FREQ_1458M (1458000000UL >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NVP6188_LINK_FREQ_756M (756000000UL >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NVP6188_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define NVP6188_BITS_PER_SAMPLE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define NVP6188_NAME "nvp6188"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define _MIPI_PORT0_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) //#define _MIPI_PORT1_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define POWER_ALWAY_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifdef _MIPI_PORT0_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define _MAR_BANK_ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define _MTX_BANK_ 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define _MAR_BANK_ 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define _MTX_BANK_ 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define NVP_RESO_960H_NSTC_VALUE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define NVP_RESO_960H_PAL_VALUE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define NVP_RESO_720P_NSTC_VALUE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define NVP_RESO_720P_PAL_VALUE 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define NVP_RESO_1080P_NSTC_VALUE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define NVP_RESO_1080P_PAL_VALUE 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define NVP_RESO_960P_NSTC_VALUE 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define NVP_RESO_960P_PAL_VALUE 0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum nvp6188_support_reso {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) NVP_RESO_UNKOWN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) NVP_RESO_960H_PAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) NVP_RESO_720P_PAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) NVP_RESO_960P_PAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) NVP_RESO_1080P_PAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) NVP_RESO_960H_NSTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) NVP_RESO_720P_NSTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) NVP_RESO_960P_NSTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) NVP_RESO_1080P_NSTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Audio output port formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) enum nvp6188_audfmts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) AUDFMT_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) AUDFMT_I2S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) AUDFMT_DSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) AUDFMT_SSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct nvp6188_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const struct regval *global_reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 channel_reso[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct nvp6188_audio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) enum nvp6188_audfmts audfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int mclk_fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct nvp6188 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct gpio_desc *vi_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct nvp6188_mode cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct nvp6188_audio *audio_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct nvp6188_audio *audio_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct task_struct *detect_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct input_dev* input_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned char detect_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned char last_detect_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u8 is_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define to_nvp6188(sd) container_of(sd, struct nvp6188, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int nvp6188_audio_init(struct nvp6188 *nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) // detect_status: bit 0~3 means channels plugin status : 1 no exist 0: exist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static ssize_t show_hotplug_status(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) char *buf) //cat命令时,将会调用该函数
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return sprintf(buf, "%d\n", nvp6188->detect_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static DEVICE_ATTR(hotplug_status, S_IRUSR, show_hotplug_status, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct attribute *dev_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) &dev_attr_hotplug_status.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct attribute_group dev_attr_grp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .attrs = dev_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static __maybe_unused const struct regval common_setting_756M_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { 0xff, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { 0x80, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { 0x00, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { 0x01, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { 0x02, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { 0x03, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { 0x22, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { 0x23, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { 0x26, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { 0x27, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 0x2a, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 0x2b, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 0x2e, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { 0x2f, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { 0xff, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { 0x98, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { 0xed, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { 0xff, 0x05+0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { 0x00, 0xd0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { 0x01, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { 0x47, 0xee },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { 0x50, 0xc6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { 0x57, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { 0x58, 0x77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { 0x5b, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { 0x5c, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { 0xB8, 0xB8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { 0xff, 0x05+1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { 0x00, 0xd0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { 0x01, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 0x47, 0xee },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 0x50, 0xc6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { 0x57, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { 0x58, 0x77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 0x5b, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 0x5c, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 0xB8, 0xB8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 0xff, 0x05+2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 0x00, 0xd0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 0x01, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { 0x47, 0xee },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 0x50, 0xc6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { 0x57, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 0x58, 0x77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { 0x5b, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 0x5c, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 0xB8, 0xB8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { 0xff, 0x05+3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { 0x00, 0xd0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { 0x01, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { 0x47, 0xee },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { 0x50, 0xc6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { 0x57, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { 0x58, 0x77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 0x5b, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 0x5c, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 0xB8, 0xB8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { 0xff, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { 0x50, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { 0x51, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { 0x52, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { 0x53, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { 0x54, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { 0x55, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { 0x56, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { 0x57, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { 0x58, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { 0x59, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { 0x5a, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { 0x5b, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { 0x5c, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { 0x5d, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { 0x5e, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { 0x5f, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { 0xff, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { 0x25, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { 0x27, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { 0x30, 0xac },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { 0x31, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { 0x32, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { 0x33, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { 0x34, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { 0x35, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { 0x36, 0xc3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { 0x37, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { 0x38, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { 0x39, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { 0x3a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { 0x3b, 0xb2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { 0xa5, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { 0xa7, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { 0xb0, 0xac },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { 0xb1, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { 0xb2, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { 0xb3, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { 0xb4, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { 0xb5, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { 0xb6, 0xc3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { 0xb7, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { 0xb8, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { 0xb9, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { 0xba, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { 0xbb, 0xb2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { 0xff, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { 0x25, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { 0x27, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { 0x30, 0xac },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { 0x31, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { 0x32, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { 0x33, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 0x34, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 0x35, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 0x36, 0xc3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { 0x37, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 0x38, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { 0x39, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 0x3a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 0x3b, 0xb2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 0xa5, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { 0xa7, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { 0xb0, 0xac },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { 0xb1, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { 0xb2, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 0xb3, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 0xb4, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { 0xb5, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { 0xb6, 0xc3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { 0xb7, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { 0xb8, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 0xb9, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 0xba, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 0xbb, 0xb2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 0xff, 0x13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { 0x05, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { 0x31, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { 0x07, 0x47 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { 0x12, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { 0x1e, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { 0x1f, 0x27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { 0x2e, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { 0x2f, 0xc8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { 0x31, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { 0x32, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { 0x33, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { 0x72, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { 0x7a, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { 0xff, _MAR_BANK_ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { 0x10, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { 0x11, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { 0x30, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { 0x32, 0x92 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { 0x34, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { 0x36, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { 0x38, 0x58 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { 0x3c, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { 0x3d, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { 0x3e, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { 0x45, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { 0x46, 0x49 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { 0xff, _MTX_BANK_ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { 0xe9, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { 0x03, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { 0x01, 0xe0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { 0x00, 0x7d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { 0x01, 0xe0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { 0x02, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { 0x20, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { 0x20, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { 0x04, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { 0x45, 0xc4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { 0x46, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { 0x47, 0x1b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { 0x48, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { 0x65, 0xc4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { 0x66, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { 0x67, 0x1b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { 0x68, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { 0x85, 0xc4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { 0x86, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { 0x87, 0x1b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { 0x88, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { 0xa5, 0xc4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { 0xa6, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { 0xa7, 0x1b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { 0xa8, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { 0xc5, 0xc4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { 0xc6, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { 0xc7, 0x1b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { 0xc8, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { 0xeb, 0x8d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { 0xff, _MAR_BANK_ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { 0x00, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { 0x40, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { 0x40, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { 0xff, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { 0x97, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) { 0x97, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { 0xff, 0x00 }, //test pattern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { 0x78, 0xba },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { 0x79, 0xac },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { 0xff, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { 0x2c, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { 0x6a, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { 0xff, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { 0x2c, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { 0x6a, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { 0xff, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { 0x2c, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { 0x6a, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { 0xff, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { 0x2c, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { 0x6a, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static __maybe_unused const struct regval common_setting_1458M_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { 0xff, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { 0x80, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { 0x00, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { 0x01, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { 0x02, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { 0x03, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { 0x22, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { 0x23, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { 0x26, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { 0x27, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { 0x2a, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { 0x2b, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { 0x2e, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { 0x2f, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { 0xff, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) { 0x98, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) { 0xed, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) { 0xff, 0x05+0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { 0x00, 0xd0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { 0x01, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { 0x47, 0xee },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { 0x50, 0xc6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { 0x57, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { 0x58, 0x77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { 0x5b, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { 0x5c, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { 0xB8, 0xB8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { 0xff, 0x05+1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { 0x00, 0xd0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { 0x01, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { 0x47, 0xee },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) { 0x50, 0xc6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { 0x57, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { 0x58, 0x77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { 0x5b, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { 0x5c, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { 0xB8, 0xB8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { 0xff, 0x05+2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { 0x00, 0xd0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { 0x01, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { 0x47, 0xee },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { 0x50, 0xc6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { 0x57, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { 0x58, 0x77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { 0x5b, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { 0x5c, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { 0xB8, 0xB8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { 0xff, 0x05+3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { 0x00, 0xd0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { 0x01, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { 0x47, 0xee },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { 0x50, 0xc6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { 0x57, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { 0x58, 0x77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { 0x5b, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { 0x5c, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) { 0xB8, 0xB8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { 0xff, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { 0x50, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { 0x51, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { 0x52, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { 0x53, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { 0x54, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { 0x55, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { 0x56, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { 0x57, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { 0x58, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { 0x59, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { 0x5a, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { 0x5b, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) { 0x5c, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { 0x5d, 0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { 0x5e, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { 0x5f, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { 0xff, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { 0x25, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { 0x27, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) { 0x30, 0xac },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { 0x31, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) { 0x32, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) { 0x33, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) { 0x34, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) { 0x35, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) { 0x36, 0xc3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) { 0x37, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) { 0x38, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) { 0x39, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) { 0x3a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) { 0x3b, 0xb2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) { 0xa5, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) { 0xa7, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { 0xb0, 0xac },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { 0xb1, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) { 0xb2, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) { 0xb3, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) { 0xb4, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) { 0xb5, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) { 0xb6, 0xc3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { 0xb7, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) { 0xb8, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) { 0xb9, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { 0xba, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) { 0xbb, 0xb2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) { 0xff, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) { 0x25, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { 0x27, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { 0x30, 0xac },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { 0x31, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { 0x32, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { 0x33, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { 0x34, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { 0x35, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { 0x36, 0xc3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { 0x37, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) { 0x38, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { 0x39, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) { 0x3a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) { 0x3b, 0xb2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) { 0xa5, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { 0xa7, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) { 0xb0, 0xac },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) { 0xb1, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) { 0xb2, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) { 0xb3, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) { 0xb4, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) { 0xb5, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) { 0xb6, 0xc3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) { 0xb7, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) { 0xb8, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) { 0xb9, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) { 0xba, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) { 0xbb, 0xb2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { 0xff, 0x13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) { 0x05, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) { 0x31, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) { 0x07, 0x47 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { 0x12, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { 0x1e, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) { 0x1f, 0x27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { 0x2e, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { 0x2f, 0xc8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) { 0x31, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) { 0x32, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { 0x33, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { 0x72, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { 0x7a, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) { 0xff, _MAR_BANK_ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) { 0x10, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) { 0x11, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) { 0x30, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) { 0x32, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) { 0x34, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { 0x36, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { 0x38, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { 0x3c, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { 0x3d, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { 0x3e, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { 0x45, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { 0x46, 0x49 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) { 0xff, _MTX_BANK_ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { 0xe9, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { 0x03, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) { 0x01, 0xe4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { 0x00, 0x7d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { 0x01, 0xe0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) { 0x02, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { 0x20, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { 0x20, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { 0x04, 0x6c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) { 0x45, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { 0x46, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) { 0x47, 0x36 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { 0x48, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { 0x65, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) { 0x66, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) { 0x67, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { 0x68, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) { 0x85, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { 0x86, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) { 0x87, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { 0x88, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) { 0xa5, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) { 0xa6, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) { 0xa7, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) { 0xa8, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) { 0xc5, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) { 0xc6, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) { 0xc7, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { 0xc8, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) { 0xeb, 0x8d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) { 0xff, _MAR_BANK_ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) { 0x00, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) { 0x40, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) { 0x40, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) { 0xff, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { 0x97, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { 0x97, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { 0xff, 0x00 }, //test pattern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) { 0x78, 0xba },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) { 0x79, 0xac },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) { 0xff, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) { 0x2c, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) { 0x6a, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) { 0xff, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) { 0x2c, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) { 0x6a, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) { 0xff, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) { 0x2c, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) { 0x6a, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) { 0xff, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) { 0x2c, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) { 0x6a, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static __maybe_unused const struct regval auto_detect_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) { 0xFF, 0x13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) { 0x30, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) { 0x70, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) { 0xFF, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) { 0x00, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) { 0x01, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) { 0x02, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) { 0x03, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) { 0x00, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { 0x01, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) { 0x02, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) { 0x03, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static struct nvp6188_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .global_reg_list = common_setting_1458M_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .bpp = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .height = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .global_reg_list = common_setting_1458M_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .bpp = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .width = 960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .global_reg_list = common_setting_1458M_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .bpp = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static const s64 link_freq_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) NVP6188_LINK_FREQ_1458M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) NVP6188_LINK_FREQ_756M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* sensor register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int nvp6188_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) usleep_range(300, 400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "nvp6188 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static int nvp6188_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) const struct regval *regs, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) while (i < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ret = nvp6188_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dev_err(&client->dev, "%s failed !\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* sensor register read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static int nvp6188_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dev_err(&client->dev, "nvp6188 read reg(0x%x) failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static unsigned char nv6188_read_vfc(struct nvp6188 *nvp6188, unsigned char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) unsigned char ch_vfc = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) nvp6188_write_reg(client, 0xff, 0x05 + ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) nvp6188_read_reg(client, 0xf0, &ch_vfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return ch_vfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static __maybe_unused int nvp6188_read_all_vfc(struct nvp6188 *nvp6188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u8 *ch_vfc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) int check_cnt = 0, ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ret = nvp6188_write_array(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) auto_detect_regs, ARRAY_SIZE(auto_detect_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev_err(&client->dev, "write auto_detect_regs faild %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) while ((check_cnt++) < 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) for (ch = 0; ch < 4; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ch_vfc[ch] = nv6188_read_vfc(nvp6188, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ch_vfc[0] != 0xff || ch_vfc[1] != 0xff ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ch_vfc[2] != 0xff || ch_vfc[3] != 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (ch == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dev_dbg(&client->dev, "try check cnt %d",check_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) usleep_range(20 * 1000, 40 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dev_err(&client->dev, "read vfc faild %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_dbg(&client->dev, "read vfc 0x%2x 0x%2x 0x%2x 0x%2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ch_vfc[0], ch_vfc[1], ch_vfc[2], ch_vfc[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static __maybe_unused int nvp6188_auto_detect_fmt(struct nvp6188 *nvp6188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) int ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) unsigned char ch_vfc[4] = { 0xff, 0xff, 0xff, 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) unsigned char val_13x70 = 0, val_13x71 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (nvp6188_read_all_vfc(nvp6188, ch_vfc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) for (ch = 0; ch < 4; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) nvp6188_write_reg(client, 0xFF, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) nvp6188_read_reg(client, 0x70, &val_13x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) val_13x70 |= (0x01 << ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) nvp6188_write_reg(client, 0x70, val_13x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) nvp6188_read_reg(client, 0x71, &val_13x71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) val_13x71 |= (0x01 << ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) nvp6188_write_reg(client, 0x71, val_13x71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) switch(ch_vfc[ch]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) case NVP_RESO_960H_NSTC_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dev_dbg(&client->dev, "channel %d det 960h nstc", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) nvp6188->cur_mode.channel_reso[ch] = NVP_RESO_960H_NSTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) case NVP_RESO_960H_PAL_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev_dbg(&client->dev, "channel %d det 960h pal", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) nvp6188->cur_mode.channel_reso[ch] = NVP_RESO_960H_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) case NVP_RESO_720P_NSTC_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_dbg(&client->dev, "channel %d det 720p nstc", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) nvp6188->cur_mode.channel_reso[ch] = NVP_RESO_720P_NSTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) case NVP_RESO_720P_PAL_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dev_dbg(&client->dev, "channel %d det 720p pal", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) nvp6188->cur_mode.channel_reso[ch] = NVP_RESO_720P_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) case NVP_RESO_1080P_NSTC_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dev_dbg(&client->dev, "channel %d det 1080p nstc", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) nvp6188->cur_mode.channel_reso[ch] = NVP_RESO_1080P_NSTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) case NVP_RESO_1080P_PAL_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev_dbg(&client->dev, "channel %d det 1080p pal", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) nvp6188->cur_mode.channel_reso[ch] = NVP_RESO_1080P_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) case NVP_RESO_960P_NSTC_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dev_dbg(&client->dev, "channel %d det 960p nstc", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) nvp6188->cur_mode.channel_reso[ch] = NVP_RESO_960P_NSTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) case NVP_RESO_960P_PAL_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dev_dbg(&client->dev, "channel %d det 960p pal", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) nvp6188->cur_mode.channel_reso[ch] = NVP_RESO_960P_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dev_err(&client->dev, "channel %d not detect, def 1080p pal\n", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) nvp6188->cur_mode.channel_reso[ch] = NVP_RESO_1080P_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static __maybe_unused int nvp6188_auto_detect_hotplug(struct nvp6188 *nvp6188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) nvp6188_write_reg(client, 0xff, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) nvp6188_read_reg(client, 0xa8, &nvp6188->detect_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) nvp6188->detect_status = ~nvp6188->detect_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static int nvp6188_get_reso_dist(const struct nvp6188_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static struct nvp6188_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) nvp6188_find_best_fit(struct nvp6188 *nvp6188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) for (i = 0; i < nvp6188->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) dist = nvp6188_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) supported_modes[i].bus_fmt == framefmt->code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static int nvp6188_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct nvp6188_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) mutex_lock(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) mode = nvp6188_find_best_fit(nvp6188, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) memcpy(&nvp6188->cur_mode, mode, sizeof(struct nvp6188_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) fmt->format.colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) mutex_unlock(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) __v4l2_ctrl_s_ctrl(nvp6188->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * NVP6188_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) __v4l2_ctrl_s_ctrl_int64(nvp6188->pixel_rate, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dev_err(&nvp6188->client->dev, "mipi_freq_idx %d\n", mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) dev_err(&nvp6188->client->dev, "pixel_rate %lld\n", pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) mutex_unlock(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int nvp6188_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) const struct nvp6188_mode *mode = &nvp6188->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) mutex_lock(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) mutex_unlock(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (fmt->pad < PAD_MAX && fmt->pad >= PAD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) mutex_unlock(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dev_dbg(&client->dev, "%s: %x %dx%d vc %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) __func__, fmt->format.code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) fmt->format.width, fmt->format.height, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static int nvp6188_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) code->code = nvp6188->cur_mode.bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static int nvp6188_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (fse->index >= nvp6188->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static int nvp6188_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) const struct nvp6188_mode *mode = &nvp6188->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) mutex_lock(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) mutex_unlock(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static int nvp6188_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static int nvp6188_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct v4l2_mbus_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) cfg->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) cfg->flags = V4L2_MBUS_CSI2_4_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) V4L2_MBUS_CSI2_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static void nvp6188_get_module_inf(struct nvp6188 *nvp6188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) strlcpy(inf->base.sensor, NVP6188_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) strlcpy(inf->base.module, nvp6188->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) strlcpy(inf->base.lens, nvp6188->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static void nvp6188_get_vc_fmt_inf(struct nvp6188 *nvp6188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct rkmodule_vc_fmt_info *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) int ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) unsigned char ch_vfc[4] = { 0xff, 0xff, 0xff, 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) nvp6188_read_all_vfc(nvp6188, ch_vfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) dev_dbg(&nvp6188->client->dev, "nvp6188_get_vc_fmt_inf 0x%2x 0x%2x 0x%2x 0x%2x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ch_vfc[0], ch_vfc[1], ch_vfc[2], ch_vfc[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) for (ch = 0; ch < 4; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) switch(ch_vfc[ch]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) case NVP_RESO_960H_NSTC_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) inf->width[ch] = 960;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) inf->height[ch] = 576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) inf->fps[ch] = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) case NVP_RESO_960H_PAL_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) inf->width[ch] = 960;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) inf->height[ch] = 576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) inf->fps[ch] = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) case NVP_RESO_960P_PAL_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) inf->width[ch] = 1280;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) inf->height[ch] = 960;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) inf->fps[ch] = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) case NVP_RESO_960P_NSTC_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) inf->width[ch] = 1280;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) inf->height[ch] = 960;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) inf->fps[ch] = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) case NVP_RESO_720P_PAL_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) inf->width[ch] = 1280;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) inf->height[ch] = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) inf->fps[ch] = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) case NVP_RESO_720P_NSTC_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) inf->width[ch] = 1280;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) inf->height[ch] = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) inf->fps[ch] = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) case NVP_RESO_1080P_NSTC_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) inf->width[ch] = 1920;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) inf->height[ch] = 1080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) inf->fps[ch] = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) case NVP_RESO_1080P_PAL_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) inf->width[ch] = 1920;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) inf->height[ch] = 1080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) inf->fps[ch] = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static void nvp6188_get_vc_hotplug_inf(struct nvp6188 *nvp6188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct rkmodule_vc_hotplug_info *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) nvp6188_auto_detect_hotplug(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) inf->detect_status = nvp6188->detect_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static void nvp6188_get_vicap_rst_inf(struct nvp6188 *nvp6188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct rkmodule_vicap_reset_info *rst_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) rst_info->is_reset = nvp6188->is_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) rst_info->src = RKCIF_RESET_SRC_ERR_HOTPLUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static void nvp6188_set_vicap_rst_inf(struct nvp6188 *nvp6188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) struct rkmodule_vicap_reset_info rst_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) nvp6188->is_reset = rst_info.is_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static void nvp6188_set_streaming(struct nvp6188 *nvp6188, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) dev_info(&client->dev, "%s: on: %d\n", __func__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) nvp6188_write_reg(client, 0xff, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) nvp6188_write_reg(client, 0xff, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) nvp6188_write_reg(client, 0xff, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) nvp6188_write_reg(client, 0xff, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static long nvp6188_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) nvp6188_get_module_inf(nvp6188, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) case RKMODULE_GET_VC_FMT_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) nvp6188_get_vc_fmt_inf(nvp6188, (struct rkmodule_vc_fmt_info *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) case RKMODULE_GET_VC_HOTPLUG_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) nvp6188_get_vc_hotplug_inf(nvp6188, (struct rkmodule_vc_hotplug_info *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) case RKMODULE_GET_VICAP_RST_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) nvp6188_get_vicap_rst_inf(nvp6188, (struct rkmodule_vicap_reset_info *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) case RKMODULE_SET_VICAP_RST_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) nvp6188_set_vicap_rst_inf(nvp6188, *(struct rkmodule_vicap_reset_info *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) case RKMODULE_GET_START_STREAM_SEQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) *(int *)arg = RKMODULE_START_STREAM_FRONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) nvp6188_set_streaming(nvp6188, !!stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static long nvp6188_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct rkmodule_vc_fmt_info *vc_fmt_inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) struct rkmodule_vc_hotplug_info *vc_hp_inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) struct rkmodule_vicap_reset_info *vicap_rst_inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) int *seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) ret = nvp6188_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ret = nvp6188_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) case RKMODULE_GET_VC_FMT_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) vc_fmt_inf = kzalloc(sizeof(*vc_fmt_inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (!vc_fmt_inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ret = nvp6188_ioctl(sd, cmd, vc_fmt_inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) ret = copy_to_user(up, vc_fmt_inf, sizeof(*vc_fmt_inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) kfree(vc_fmt_inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) case RKMODULE_GET_VC_HOTPLUG_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) vc_hp_inf = kzalloc(sizeof(*vc_hp_inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (!vc_hp_inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) ret = nvp6188_ioctl(sd, cmd, vc_hp_inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ret = copy_to_user(up, vc_hp_inf, sizeof(*vc_hp_inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) kfree(vc_hp_inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) case RKMODULE_GET_VICAP_RST_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) vicap_rst_inf = kzalloc(sizeof(*vicap_rst_inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (!vicap_rst_inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) ret = nvp6188_ioctl(sd, cmd, vicap_rst_inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ret = copy_to_user(up, vicap_rst_inf, sizeof(*vicap_rst_inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) kfree(vicap_rst_inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) case RKMODULE_SET_VICAP_RST_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) vicap_rst_inf = kzalloc(sizeof(*vicap_rst_inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (!vicap_rst_inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ret = copy_from_user(vicap_rst_inf, up, sizeof(*vicap_rst_inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ret = nvp6188_ioctl(sd, cmd, vicap_rst_inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) kfree(vicap_rst_inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) case RKMODULE_GET_START_STREAM_SEQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) seq = kzalloc(sizeof(*seq), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (!seq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ret = nvp6188_ioctl(sd, cmd, seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ret = copy_to_user(up, seq, sizeof(*seq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) kfree(seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) //each channel setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) 960x480i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ch : 0 ~ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ntpal: 1:25p, 0:30p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) static __maybe_unused void nv6188_set_chn_960h(struct nvp6188 *nvp6188, u8 ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) u8 ntpal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) unsigned char val_0x54 = 0, val_20x01 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) dev_err(&client->dev, "nv6188_set_chn_960h ch %d ntpal %d", ch, ntpal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) nvp6188_write_reg(client, 0xff, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) nvp6188_write_reg(client, 0x08 + ch, ntpal ? 0xdd : 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) nvp6188_write_reg(client, 0x18 + ch, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) nvp6188_write_reg(client, 0x22 + ch * 4, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) nvp6188_write_reg(client, 0x23 + ch * 4, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) nvp6188_write_reg(client, 0x30 + ch, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) nvp6188_write_reg(client, 0x34 + ch, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) nvp6188_read_reg(client, 0x54, &val_0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (ntpal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) val_0x54 &= ~(0x10 << ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) val_0x54 |= (0x10 << ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) nvp6188_write_reg(client, 0x54, val_0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) nvp6188_write_reg(client, 0x58 + ch, ntpal ? 0x80 : 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) nvp6188_write_reg(client, 0x5c + ch, ntpal ? 0xbe : 0xbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) nvp6188_write_reg(client, 0x64 + ch, ntpal ? 0xa0 : 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) nvp6188_write_reg(client, 0x81 + ch, ntpal ? 0xf0 : 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) nvp6188_write_reg(client, 0x85 + ch, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) nvp6188_write_reg(client, 0x89 + ch, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) nvp6188_write_reg(client, ch + 0x8e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) nvp6188_write_reg(client, 0xa0 + ch, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) nvp6188_write_reg(client, 0xff, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) nvp6188_write_reg(client, 0x84 + ch, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) nvp6188_write_reg(client, 0x88 + ch, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) nvp6188_write_reg(client, 0x8c + ch, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) nvp6188_write_reg(client, 0xa0 + ch, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) nvp6188_write_reg(client, 0xed, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) nvp6188_write_reg(client, 0xff, 0x05 + ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) nvp6188_write_reg(client, 0x01, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) nvp6188_write_reg(client, 0x05, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) nvp6188_write_reg(client, 0x08, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) nvp6188_write_reg(client, 0x25, 0xdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) nvp6188_write_reg(client, 0x28, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) nvp6188_write_reg(client, 0x2f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) nvp6188_write_reg(client, 0x30, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) nvp6188_write_reg(client, 0x31, 0x43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) nvp6188_write_reg(client, 0x32, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) nvp6188_write_reg(client, 0x47, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) nvp6188_write_reg(client, 0x50, 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) nvp6188_write_reg(client, 0x57, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) nvp6188_write_reg(client, 0x58, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) nvp6188_write_reg(client, 0x5b, 0x43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) nvp6188_write_reg(client, 0x5c, 0x78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) nvp6188_write_reg(client, 0x5f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) nvp6188_write_reg(client, 0x62, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) nvp6188_write_reg(client, 0x7b, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) nvp6188_write_reg(client, 0x7c, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) nvp6188_write_reg(client, 0x7d, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) nvp6188_write_reg(client, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) nvp6188_write_reg(client, 0x90, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) nvp6188_write_reg(client, 0xa9, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) nvp6188_write_reg(client, 0xb5, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) nvp6188_write_reg(client, 0xb8, 0xb9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) nvp6188_write_reg(client, 0xb9, 0x72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) nvp6188_write_reg(client, 0xd1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) nvp6188_write_reg(client, 0xd5, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) nvp6188_write_reg(client, 0xff, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) nvp6188_write_reg(client, 0x96 + ch * 0x20, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) nvp6188_write_reg(client, 0x98 + ch * 0x20, ntpal ? 0xc0 : 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) nvp6188_write_reg(client, ch * 0x20 + 0x9e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) nvp6188_write_reg(client, 0xff, _MAR_BANK_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) nvp6188_read_reg(client, 0x01, &val_20x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) val_20x01 &= (~(0x03 << (ch * 2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) val_20x01 |= (0x02 << (ch * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) nvp6188_write_reg(client, 0x01, val_20x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) nvp6188_write_reg(client, 0x12 + ch * 2, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) nvp6188_write_reg(client, 0x13 + ch * 2, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) //each channel setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) 1280x720p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) ch : 0 ~ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) ntpal: 1:25p, 0:30p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static __maybe_unused void nv6188_set_chn_720p(struct nvp6188 *nvp6188, u8 ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) u8 ntpal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) unsigned char val_0x54 = 0, val_20x01 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) dev_err(&client->dev, "nv6188_set_chn_720p ch %d ntpal %d", ch, ntpal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) nvp6188_write_reg(client, 0xff, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) nvp6188_write_reg(client, 0x08 + ch, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) nvp6188_write_reg(client, 0x18 + ch, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) nvp6188_write_reg(client, 0x30 + ch, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) nvp6188_write_reg(client, 0x34 + ch, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) nvp6188_read_reg(client, 0x54, &val_0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) val_0x54 &= ~(0x10 << ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) nvp6188_write_reg(client, 0x54, val_0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) nvp6188_write_reg(client, 0x58 + ch, ntpal ? 0x80 : 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) nvp6188_write_reg(client, 0x5c + ch, ntpal ? 0x00 : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) nvp6188_write_reg(client, 0x64 + ch, ntpal ? 0x01 : 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) nvp6188_write_reg(client, 0x81 + ch, ntpal ? 0x0d : 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) nvp6188_write_reg(client, 0x85 + ch, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) nvp6188_write_reg(client, 0x89 + ch, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) nvp6188_write_reg(client, ch + 0x8e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) nvp6188_write_reg(client, 0xa0 + ch, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) nvp6188_write_reg(client, 0xff, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) nvp6188_write_reg(client, 0x84 + ch, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) nvp6188_write_reg(client, 0x88 + ch, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) nvp6188_write_reg(client, 0x8c + ch, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) nvp6188_write_reg(client, 0xa0 + ch, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) nvp6188_write_reg(client, 0xff, 0x05 + ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) nvp6188_write_reg(client, 0x01, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) nvp6188_write_reg(client, 0x05, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) nvp6188_write_reg(client, 0x08, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) nvp6188_write_reg(client, 0x25, 0xdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) nvp6188_write_reg(client, 0x28, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) nvp6188_write_reg(client, 0x2f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) nvp6188_write_reg(client, 0x30, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) nvp6188_write_reg(client, 0x31, 0x43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) nvp6188_write_reg(client, 0x32, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) nvp6188_write_reg(client, 0x47, 0xee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) nvp6188_write_reg(client, 0x50, 0xc6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) nvp6188_write_reg(client, 0x57, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) nvp6188_write_reg(client, 0x58, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) nvp6188_write_reg(client, 0x5b, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) nvp6188_write_reg(client, 0x5c, 0x7C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) nvp6188_write_reg(client, 0x5f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) nvp6188_write_reg(client, 0x62, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) nvp6188_write_reg(client, 0x7b, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) nvp6188_write_reg(client, 0x7c, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) nvp6188_write_reg(client, 0x7d, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) nvp6188_write_reg(client, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) nvp6188_write_reg(client, 0x90, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) nvp6188_write_reg(client, 0xa9, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) nvp6188_write_reg(client, 0xb5, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) nvp6188_write_reg(client, 0xb8, 0x39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) nvp6188_write_reg(client, 0xb9, 0x72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) nvp6188_write_reg(client, 0xd1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) nvp6188_write_reg(client, 0xd5, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) nvp6188_write_reg(client, 0xff, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) nvp6188_write_reg(client, 0x96 + ch * 0x20, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) nvp6188_write_reg(client, 0x98 + ch * 0x20, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) nvp6188_write_reg(client, ch * 0x20 + 0x9e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) nvp6188_write_reg(client, 0xff, _MAR_BANK_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) nvp6188_read_reg(client, 0x01, &val_20x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) val_20x01 &= (~(0x03 << (ch * 2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) val_20x01 |= (0x01 << (ch * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) nvp6188_write_reg(client, 0x01, val_20x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) nvp6188_write_reg(client, 0x12 + ch * 2, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) nvp6188_write_reg(client, 0x13 + ch * 2, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) //each channel setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) 1920x1080p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ch : 0 ~ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) ntpal: 1:25p, 0:30p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static __maybe_unused void nv6188_set_chn_1080p(struct nvp6188 *nvp6188, u8 ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) u8 ntpal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) unsigned char val_0x54 = 0, val_20x01 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) dev_err(&client->dev, "nv6188_set_chn_1080p ch %d ntpal %d", ch, ntpal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) nvp6188_write_reg(client, 0xff, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) nvp6188_write_reg(client, 0x08 + ch, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) nvp6188_write_reg(client, 0x18 + ch, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) nvp6188_write_reg(client, 0x30 + ch, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) nvp6188_write_reg(client, 0x34 + ch, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) nvp6188_read_reg(client, 0x54, &val_0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) val_0x54 &= ~(0x10 << ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) nvp6188_write_reg(client, 0x54, val_0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) nvp6188_write_reg(client, 0x58 + ch, ntpal ? 0x80 : 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) nvp6188_write_reg(client, 0x5c + ch, ntpal ? 0x00 : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) nvp6188_write_reg(client, 0x64 + ch, ntpal ? 0x01 : 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) nvp6188_write_reg(client, 0x81 + ch, ntpal ? 0x03 : 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) nvp6188_write_reg(client, 0x85 + ch, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) nvp6188_write_reg(client, 0x89 + ch, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) nvp6188_write_reg(client, ch + 0x8e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) nvp6188_write_reg(client, 0xa0 + ch, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) nvp6188_write_reg(client, 0xff, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) nvp6188_write_reg(client, 0x84 + ch, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) nvp6188_write_reg(client, 0x88 + ch, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) nvp6188_write_reg(client, 0x8c + ch, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) nvp6188_write_reg(client, 0xa0 + ch, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) nvp6188_write_reg(client, 0xff, 0x05 + ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) nvp6188_write_reg(client, 0x01, 0x22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) nvp6188_write_reg(client, 0x05, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) nvp6188_write_reg(client, 0x08, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) nvp6188_write_reg(client, 0x25, 0xdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) nvp6188_write_reg(client, 0x28, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) nvp6188_write_reg(client, 0x2f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) nvp6188_write_reg(client, 0x30, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) nvp6188_write_reg(client, 0x31, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) nvp6188_write_reg(client, 0x32, 0xa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) nvp6188_write_reg(client, 0x47, 0xee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) nvp6188_write_reg(client, 0x50, 0xc6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) nvp6188_write_reg(client, 0x57, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) nvp6188_write_reg(client, 0x58, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) nvp6188_write_reg(client, 0x5b, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) nvp6188_write_reg(client, 0x5c, 0x7C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) nvp6188_write_reg(client, 0x5f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) nvp6188_write_reg(client, 0x62, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) nvp6188_write_reg(client, 0x7b, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) nvp6188_write_reg(client, 0x7c, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) nvp6188_write_reg(client, 0x7d, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) nvp6188_write_reg(client, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) nvp6188_write_reg(client, 0x90, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) nvp6188_write_reg(client, 0xa9, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) nvp6188_write_reg(client, 0xb5, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) nvp6188_write_reg(client, 0xb8, 0x39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) nvp6188_write_reg(client, 0xb9, 0x72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) nvp6188_write_reg(client, 0xd1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) nvp6188_write_reg(client, 0xd5, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) nvp6188_write_reg(client, 0xff, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) nvp6188_write_reg(client, 0x96 + ch * 0x20, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) nvp6188_write_reg(client, 0x98 + ch * 0x20, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) nvp6188_write_reg(client, ch * 0x20 + 0x9e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) nvp6188_write_reg(client, 0xff, _MAR_BANK_);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) nvp6188_read_reg(client, 0x01, &val_20x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) val_20x01 &= (~(0x03 << (ch * 2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) nvp6188_write_reg(client, 0x01, val_20x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) nvp6188_write_reg(client, 0x12 + ch * 2, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) nvp6188_write_reg(client, 0x13 + ch * 2, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static __maybe_unused void nvp6188_manual_mode(struct nvp6188 *nvp6188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) int i, reso;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) for (i = 3; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) reso = nvp6188->cur_mode.channel_reso[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) switch (reso) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) case NVP_RESO_960H_PAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) nv6188_set_chn_960h(nvp6188, i, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) case NVP_RESO_720P_PAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) nv6188_set_chn_720p(nvp6188, i, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) case NVP_RESO_1080P_PAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) nv6188_set_chn_1080p(nvp6188, i, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) case NVP_RESO_960H_NSTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) nv6188_set_chn_960h(nvp6188, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) case NVP_RESO_720P_NSTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) nv6188_set_chn_720p(nvp6188, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) case NVP_RESO_1080P_NSTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) nv6188_set_chn_1080p(nvp6188, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) nv6188_set_chn_1080p(nvp6188, i, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static int detect_thread_function(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) struct nvp6188 *nvp6188 = (struct nvp6188 *) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) unsigned char bits = 0, ch, val_13x70 = 0, val_13x71 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) int need_reset_wait = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (nvp6188->power_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) nvp6188_auto_detect_hotplug(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) nvp6188->last_detect_status = nvp6188->detect_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) nvp6188->is_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) while (!kthread_should_stop()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (nvp6188->power_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) nvp6188_auto_detect_hotplug(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (nvp6188->last_detect_status != nvp6188->detect_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) bits = nvp6188->last_detect_status ^ nvp6188->detect_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) for (ch = 0; ch < 4; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (bits & (1 << ch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) dev_err(&client->dev, "nvp6188 detect ch %d change\n", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) nvp6188_write_reg(client, 0xFF, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) nvp6188_read_reg(client, 0x70, &val_13x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) val_13x70 |= (0x01 << ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) nvp6188_write_reg(client, 0x70, val_13x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) nvp6188_read_reg(client, 0x71, &val_13x71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) val_13x71 |= (0x01 << ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) nvp6188_write_reg(client, 0x71, val_13x71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) nvp6188->last_detect_status = nvp6188->detect_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) input_event(nvp6188->input_dev, EV_MSC, MSC_RAW, nvp6188->detect_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) input_sync(nvp6188->input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) need_reset_wait = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (need_reset_wait > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) need_reset_wait--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) } else if (need_reset_wait == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) need_reset_wait = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) nvp6188->is_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) dev_err(&client->dev, "trigger reset time up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) set_current_state(TASK_INTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) schedule_timeout(msecs_to_jiffies(200));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) static int __maybe_unused detect_thread_start(struct nvp6188 *nvp6188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) nvp6188->detect_thread = kthread_create(detect_thread_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) nvp6188, "nvp6188_kthread");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) if (IS_ERR(nvp6188->detect_thread)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) dev_err(&client->dev, "kthread_create nvp6188_kthread failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) ret = PTR_ERR(nvp6188->detect_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) nvp6188->detect_thread = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) wake_up_process(nvp6188->detect_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static int __maybe_unused detect_thread_stop(struct nvp6188 *nvp6188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (nvp6188->detect_thread)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) kthread_stop(nvp6188->detect_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) nvp6188->detect_thread = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) static int __nvp6188_start_stream(struct nvp6188 *nvp6188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) int array_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (nvp6188->cur_mode.global_reg_list == common_setting_1458M_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) array_size = ARRAY_SIZE(common_setting_1458M_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) } else if (nvp6188->cur_mode.global_reg_list == common_setting_756M_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) array_size = ARRAY_SIZE(common_setting_756M_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) ret = nvp6188_write_array(nvp6188->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) nvp6188->cur_mode.global_reg_list, array_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) dev_err(&client->dev, "__nvp6188_start_stream global_reg_list faild");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) nvp6188_auto_detect_fmt(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) nvp6188_manual_mode(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) nvp6188_audio_init(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) detect_thread_start(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) static int __nvp6188_stop_stream(struct nvp6188 *nvp6188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) nvp6188_write_reg(client, 0xff, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) nvp6188_write_reg(client, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) nvp6188_write_reg(client, 0x40, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) nvp6188_write_reg(client, 0x40, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) detect_thread_stop(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) static int nvp6188_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) dev_dbg(&client->dev, "s_stream: %d. %dx%d\n", on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) nvp6188->cur_mode.width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) nvp6188->cur_mode.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) mutex_lock(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) if (nvp6188->streaming == on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) __nvp6188_start_stream(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) __nvp6188_stop_stream(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) nvp6188->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) mutex_unlock(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static int nvp6188_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) mutex_lock(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (nvp6188->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) dev_dbg(&client->dev, "%s: on %d\n", __func__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) nvp6188->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) nvp6188->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) mutex_unlock(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) static int __nvp6188_power_on(struct nvp6188 *nvp6188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) struct device *dev = &nvp6188->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) dev_dbg(dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (!IS_ERR_OR_NULL(nvp6188->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ret = pinctrl_select_state(nvp6188->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) nvp6188->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) dev_err(dev, "could not set pins. ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) #if POWER_ALWAY_ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) if (!IS_ERR(nvp6188->power_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) gpiod_set_value_cansleep(nvp6188->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) usleep_range(25 * 1000, 30 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) usleep_range(1500, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) ret = clk_set_rate(nvp6188->xvclk, NVP6188_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) dev_warn(dev, "Failed to set xvclk rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (clk_get_rate(nvp6188->xvclk) != NVP6188_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) dev_warn(dev, "xvclk mismatched\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) ret = clk_prepare_enable(nvp6188->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) if (!IS_ERR(nvp6188->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) gpiod_set_value_cansleep(nvp6188->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) usleep_range(10 * 1000, 20 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) gpiod_set_value_cansleep(nvp6188->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) usleep_range(10 * 1000, 20 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) usleep_range(10 * 1000, 20 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) if (!IS_ERR(nvp6188->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) gpiod_set_value_cansleep(nvp6188->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (!IS_ERR_OR_NULL(nvp6188->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) pinctrl_select_state(nvp6188->pinctrl, nvp6188->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static void __nvp6188_power_off(struct nvp6188 *nvp6188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) struct device *dev = &nvp6188->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) dev_dbg(dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) if (!IS_ERR(nvp6188->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) gpiod_set_value_cansleep(nvp6188->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) clk_disable_unprepare(nvp6188->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (!IS_ERR_OR_NULL(nvp6188->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) ret = pinctrl_select_state(nvp6188->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) nvp6188->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) #if POWER_ALWAY_ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (!IS_ERR(nvp6188->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) gpiod_set_value_cansleep(nvp6188->power_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) static int nvp6188_initialize_controls(struct nvp6188 *nvp6188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) const struct nvp6188_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) u64 pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) handler = &nvp6188->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) mode = &nvp6188->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) ret = v4l2_ctrl_handler_init(handler, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) handler->lock = &nvp6188->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) nvp6188->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) ARRAY_SIZE(link_freq_items) - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) link_freq_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) __v4l2_ctrl_s_ctrl(nvp6188->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * NVP6188_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) nvp6188->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) V4L2_CID_PIXEL_RATE, 0, pixel_rate, 1, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) dev_err(&nvp6188->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) dev_err(&nvp6188->client->dev, "mipi_freq_idx %d\n", mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) dev_err(&nvp6188->client->dev, "pixel_rate %lld\n", pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) dev_err(&nvp6188->client->dev, "link_freq %lld\n", link_freq_items[mode->mipi_freq_idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) nvp6188->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static int nvp6188_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) return __nvp6188_power_on(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) static int nvp6188_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) __nvp6188_power_off(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) static int nvp6188_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) const struct nvp6188_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) dev_dbg(&nvp6188->client->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) mutex_lock(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) mutex_unlock(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) static const struct v4l2_subdev_internal_ops nvp6188_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .open = nvp6188_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) static const struct v4l2_subdev_video_ops nvp6188_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .s_stream = nvp6188_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .g_frame_interval = nvp6188_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) static const struct v4l2_subdev_pad_ops nvp6188_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .enum_mbus_code = nvp6188_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .enum_frame_size = nvp6188_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .enum_frame_interval = nvp6188_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .get_fmt = nvp6188_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .set_fmt = nvp6188_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .get_mbus_config = nvp6188_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) static const struct v4l2_subdev_core_ops nvp6188_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .s_power = nvp6188_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .ioctl = nvp6188_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .compat_ioctl32 = nvp6188_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) static const struct v4l2_subdev_ops nvp6188_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .core = &nvp6188_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .video = &nvp6188_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .pad = &nvp6188_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) * Audio Codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) static unsigned int nvp6188_codec_read(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) struct v4l2_subdev *sd = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) ret = nvp6188_read_reg(client, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) dev_err(&client->dev, "%s failed: (%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) static int nvp6188_codec_write(struct snd_soc_component *component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) struct v4l2_subdev *sd = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) ret = nvp6188_write_reg(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) dev_err(&client->dev, "%s failed: (%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) static int nvp6188_pcm_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) static void nvp6188_pcm_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static int nvp6188_pcm_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) struct v4l2_subdev *sd = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) u8 val_rm = 0, val_pb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) nvp6188_write_reg(client, 0xff, 0x01); /* Switch to bank1 for audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) nvp6188_read_reg(client, 0x07, &val_rm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) nvp6188_read_reg(client, 0x13, &val_pb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) /* set master/slave audio interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) case SND_SOC_DAIFMT_CBM_CFM: /* MASTER MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) val_rm |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) val_pb |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) case SND_SOC_DAIFMT_CBS_CFS: /* SLAVE MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) val_rm &= (~0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) val_pb &= (~0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) /* interface format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) case SND_SOC_DAIFMT_I2S: /* I2S MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) val_rm &= (~0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) val_pb &= (~0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) case SND_SOC_DAIFMT_DSP_A: /* DSP MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) val_rm |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) val_pb |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) case SND_SOC_DAIFMT_DSP_B: /* SSP MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) val_rm |= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) val_pb |= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) /* clock inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) case SND_SOC_DAIFMT_NB_NF: /* Inverted Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) val_rm &= (~0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) val_pb &= (~0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) case SND_SOC_DAIFMT_IB_NF: /* Non-inverted Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) val_rm |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) val_pb |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) nvp6188_write_reg(client, 0x07, val_rm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) nvp6188_write_reg(client, 0x13, val_pb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) static int nvp6188_pcm_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) struct v4l2_subdev *sd = snd_soc_dai_get_drvdata(dai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) nvp6188_write_reg(client, 0xff, 0x01); /* Switch to bank1 for audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) /* Configure formats for Playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) nvp6188_read_reg(client, 0x13, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) case SNDRV_PCM_FORMAT_S8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) val |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) val &= (~0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) switch (params_rate(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) val &= (~0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) val |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) /* TODO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) if (nvp6188->audio_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) switch (nvp6188->audio_out->mclk_fs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) val = ((val & (~0x30)) | 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) case 384:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) val = ((val & (~0x30)) | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) case 320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) val = ((val & (~0x30)) | 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) dev_err(&client->dev, "Invalid audio_out mclk_fs: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) nvp6188->audio_out->mclk_fs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) nvp6188_write_reg(client, 0x13, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) /* Configure formats for Capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) nvp6188_read_reg(client, 0x07, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) switch (params_format(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) case SNDRV_PCM_FORMAT_S8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) val |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) val &= (~0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) switch (params_rate(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) case 8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) val &= (~0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) case 16000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) val |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) /* TODO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) if (nvp6188->audio_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) switch (nvp6188->audio_in->mclk_fs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) val = ((val & (~0x30)) | 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) case 384:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) val = ((val & (~0x30)) | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) case 320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) val = ((val & (~0x30)) | 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) dev_err(&client->dev, "Invalid audio_in mclk_fs: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) nvp6188->audio_in->mclk_fs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) nvp6188_write_reg(client, 0x07, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) nvp6188_read_reg(client, 0x08, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) switch (params_channels(params)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) val = (val & (~0x03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) val = (val & (~0x03)) | 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) dev_err(&client->dev, "Not supported channels: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) params_channels(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) nvp6188_write_reg(client, 0x08, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) static int nvp6188_pcm_mute(struct snd_soc_dai *dai, int mute, int stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) static const struct snd_soc_dai_ops nvp6188_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .startup = nvp6188_pcm_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .shutdown = nvp6188_pcm_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .set_fmt = nvp6188_pcm_set_dai_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .hw_params = nvp6188_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .mute_stream = nvp6188_pcm_mute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) static struct snd_soc_dai_driver nvp6188_audio_dai = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .name = "nvp6188",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .playback = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .stream_name = "Playback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .channels_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) SNDRV_PCM_RATE_32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .capture = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .stream_name = "Capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .channels_max = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) SNDRV_PCM_RATE_32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .ops = &nvp6188_dai_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) static int nvp6188_codec_probe(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) static void nvp6188_codec_remove(struct snd_soc_component *component)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) * Control Functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) /* nvp6188 tlv kcontrol calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) static int nvp6188_codec_tlv_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) struct v4l2_subdev *sd = snd_soc_component_get_drvdata(component);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) nvp6188_write_reg(client, 0xff, 0x01); /* Switch to bank1 for audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) return snd_soc_get_volsw(kcontrol, ucontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) static int nvp6188_codec_tlv_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) return snd_soc_put_volsw(kcontrol, ucontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) static const DECLARE_TLV_DB_SCALE(nvp6188_codec_aiao_gains_tlv, 0, 125, 1875);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) * KControls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) static const struct snd_kcontrol_new nvp6188_codec_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) /* AIGAINs and MIGAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) SOC_SINGLE_EXT_TLV("AIGain_01", 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) nvp6188_codec_tlv_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) nvp6188_codec_tlv_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) nvp6188_codec_aiao_gains_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) SOC_SINGLE_EXT_TLV("AIGain_02", 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) nvp6188_codec_tlv_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) nvp6188_codec_tlv_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) nvp6188_codec_aiao_gains_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) SOC_SINGLE_EXT_TLV("AIGain_03", 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) nvp6188_codec_tlv_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) nvp6188_codec_tlv_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) nvp6188_codec_aiao_gains_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) SOC_SINGLE_EXT_TLV("AIGain_04", 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) nvp6188_codec_tlv_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) nvp6188_codec_tlv_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) nvp6188_codec_aiao_gains_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) SOC_SINGLE_EXT_TLV("MIGain", 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) nvp6188_codec_tlv_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) nvp6188_codec_tlv_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) nvp6188_codec_aiao_gains_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) /* AOGAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) SOC_SINGLE_EXT_TLV("AOGain", 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) nvp6188_codec_tlv_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) nvp6188_codec_tlv_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) nvp6188_codec_aiao_gains_tlv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) static struct snd_soc_component_driver nvp6188_codec_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .probe = nvp6188_codec_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .remove = nvp6188_codec_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .read = nvp6188_codec_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .write = nvp6188_codec_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .controls = nvp6188_codec_controls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .num_controls = ARRAY_SIZE(nvp6188_codec_controls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .idle_bias_on = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .use_pmdown_time = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .endianness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .non_legacy_dai_naming = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) static int check_chip_id(struct i2c_client *client){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) unsigned char chip_id = 0, chip_revid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) nvp6188_write_reg(client, 0xFF, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) nvp6188_read_reg(client, 0xF4, &chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) nvp6188_write_reg(client, 0xFF, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) nvp6188_read_reg(client, 0xF5, &chip_revid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) dev_err(dev, "chip_id : 0x%2x chip_revid : 0x%2x \n", chip_id, chip_revid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) if (chip_id != 0xd0 && chip_id != 0xd3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) static int nvp6188_audio_init(struct nvp6188 *nvp6188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) struct i2c_client *client = nvp6188->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) if (!nvp6188->audio_in && !nvp6188->audio_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) /* Switch to bank1 for audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) nvp6188_write_reg(client, 0xff, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) nvp6188_write_reg(client, 0x94, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) /* Single chip operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) nvp6188_write_reg(client, 0x06, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) /* MSB/u-law/linear PCM/Speaker data/4ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) nvp6188_write_reg(client, 0x08, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) /* Channels mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) nvp6188_write_reg(client, 0x0a, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) nvp6188_write_reg(client, 0x0b, 0x98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) nvp6188_write_reg(client, 0x0f, 0x31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) /* AOGAIN 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) nvp6188_write_reg(client, 0x22, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) /* First stage playback audio*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) nvp6188_write_reg(client, 0x23, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) /* Slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) nvp6188_write_reg(client, 0x39, 0x82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) nvp6188_write_reg(client, 0x01, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) nvp6188_write_reg(client, 0x02, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) nvp6188_write_reg(client, 0x03, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) nvp6188_write_reg(client, 0x04, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) nvp6188_write_reg(client, 0x05, 0x09);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) nvp6188_write_reg(client, 0x31, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) nvp6188_write_reg(client, 0x47, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) nvp6188_write_reg(client, 0x49, 0x88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) nvp6188_write_reg(client, 0x44, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) nvp6188_write_reg(client, 0x32, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) /* Filter on / 16K Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) nvp6188_write_reg(client, 0x00, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) nvp6188_write_reg(client, 0x46, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) nvp6188_write_reg(client, 0x48, 0xD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) nvp6188_write_reg(client, 0x94, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) nvp6188_write_reg(client, 0x38, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) nvp6188_write_reg(client, 0x38, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) static int nvp6188_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) struct nvp6188 *nvp6188;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) const char *str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) __maybe_unused char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) nvp6188 = devm_kzalloc(dev, sizeof(*nvp6188), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) if (!nvp6188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) &nvp6188->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) &nvp6188->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) &nvp6188->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) &nvp6188->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) dev_err(dev, "could not get %s!\n", RKMODULE_CAMERA_LENS_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) nvp6188->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) nvp6188->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) memcpy(&nvp6188->cur_mode, &supported_modes[0], sizeof(struct nvp6188_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) nvp6188->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) if (IS_ERR(nvp6188->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) nvp6188->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) if (IS_ERR(nvp6188->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) nvp6188->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) if (IS_ERR(nvp6188->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) dev_warn(dev, "Failed to get power-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) nvp6188->vi_gpio = devm_gpiod_get(dev, "vi", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) if (IS_ERR(nvp6188->vi_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) dev_warn(dev, "Failed to get vi-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) nvp6188->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) if (!IS_ERR(nvp6188->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) nvp6188->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) pinctrl_lookup_state(nvp6188->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) if (IS_ERR(nvp6188->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) dev_info(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) nvp6188->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) pinctrl_lookup_state(nvp6188->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) if (IS_ERR(nvp6188->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) dev_info(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) dev_info(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) mutex_init(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) sd = &nvp6188->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) v4l2_i2c_subdev_init(sd, client, &nvp6188_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) ret = nvp6188_initialize_controls(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) dev_err(dev, "Failed to initialize controls nvp6188\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) ret = __nvp6188_power_on(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) dev_err(dev, "Failed to power on nvp6188\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) ret = check_chip_id(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) dev_err(dev, "Failed to check senosr id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) sd->internal_ops = &nvp6188_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) nvp6188->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) ret = media_entity_pads_init(&sd->entity, 1, &nvp6188->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) if (strcmp(nvp6188->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) nvp6188->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) NVP6188_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) /* Parse audio parts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) nvp6188->audio_in = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) if (!of_property_read_string(node, "rockchip,audio-in-format", &str)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) struct nvp6188_audio *audio_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) nvp6188->audio_in = devm_kzalloc(dev, sizeof(struct nvp6188_audio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) if (!nvp6188->audio_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) dev_err(dev, "alloc audio_in failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) audio_stream = nvp6188->audio_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) if (strcmp(str, "i2s") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) audio_stream->audfmt = AUDFMT_I2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) else if (strcmp(str, "dsp") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) audio_stream->audfmt = AUDFMT_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) else if (strcmp(str, "ssp") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) audio_stream->audfmt = AUDFMT_SSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) dev_err(dev, "rockchip,audio-in-format invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) if (!of_property_read_u32(node, "rockchip,audio-in-mclk-fs", &v)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) switch (v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) case 384:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) case 320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) "rockchip,audio-in-mclk-fs invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) audio_stream->mclk_fs = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) nvp6188->audio_out = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) if (!of_property_read_string(node, "rockchip,audio-out-format", &str)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) struct nvp6188_audio *audio_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) nvp6188->audio_out = devm_kzalloc(dev, sizeof(struct nvp6188_audio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) if (!nvp6188->audio_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) dev_err(dev, "alloc audio_out failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) audio_stream = nvp6188->audio_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) if (strcmp(str, "i2s") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) audio_stream->audfmt = AUDFMT_I2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) else if (strcmp(str, "dsp") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) audio_stream->audfmt = AUDFMT_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) else if (strcmp(str, "ssp") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) audio_stream->audfmt = AUDFMT_SSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) dev_err(dev, "rockchip,audio-out-format invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) if (!of_property_read_u32(node, "rockchip,audio-out-mclk-fs", &v)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) switch (v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) case 384:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) case 320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) "rockchip,audio-out-mclk-fs invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) audio_stream->mclk_fs = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) /* Register audio DAIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) if (nvp6188->audio_in || nvp6188->audio_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) ret = devm_snd_soc_register_component(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) &nvp6188_codec_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) &nvp6188_audio_dai, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) dev_err(dev, "register audio codec failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) dev_info(dev, "registered audio codec\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) nvp6188_audio_init(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) if (sysfs_create_group(&dev->kobj, &dev_attr_grp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) nvp6188->input_dev = devm_input_allocate_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) if (nvp6188->input_dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) dev_err(dev, "failed to allocate nvp6188 input device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) nvp6188->input_dev->name = "nvp6188_input_event";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) set_bit(EV_MSC, nvp6188->input_dev->evbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) set_bit(MSC_RAW, nvp6188->input_dev->mscbit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) ret = input_register_device(nvp6188->input_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) pr_err("%s: failed to register nvp6188 input device\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) __nvp6188_power_off(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) v4l2_ctrl_handler_free(&nvp6188->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) mutex_destroy(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) static int nvp6188_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) struct nvp6188 *nvp6188 = to_nvp6188(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) v4l2_ctrl_handler_free(&nvp6188->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) mutex_destroy(&nvp6188->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) __nvp6188_power_off(nvp6188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) static const struct dev_pm_ops nvp6188_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) SET_RUNTIME_PM_OPS(nvp6188_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) nvp6188_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) static const struct of_device_id nvp6188_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) { .compatible = "nvp6188" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) MODULE_DEVICE_TABLE(of, nvp6188_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) static const struct i2c_device_id nvp6188_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) { "nvp6188", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) static struct i2c_driver nvp6188_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) .name = NVP6188_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) .pm = &nvp6188_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) .of_match_table = of_match_ptr(nvp6188_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) .probe = &nvp6188_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) .remove = &nvp6188_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) .id_table = nvp6188_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) return i2c_add_driver(&nvp6188_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) i2c_del_driver(&nvp6188_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) MODULE_AUTHOR("Vicent Chi <vicent.chi@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) MODULE_AUTHOR("Xing Zheng <zhengxing@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) MODULE_DESCRIPTION("nvp6188 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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