^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for SiliconFile NOON010PC30 CIF (1/11") Image Sensor with ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 - 2011 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Initial register configuration based on a driver authored by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * HeungJun Kim <riverful.kim@samsung.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <media/i2c/noon010pc30.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MODULE_PARM_DESC(debug, "Enable module debug trace. Set to 1 to enable.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MODULE_NAME "NOON010PC30"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Register offsets within a page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * b15..b8 - page id, b7..b0 - register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define POWER_CTRL_REG 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PAGEMODE_REG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DEVICE_ID_REG 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NOON010PC30_ID 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VDO_CTL_REG(n) (0x0010 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SYNC_CTL_REG 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Window size and position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WIN_ROWH_REG 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define WIN_ROWL_REG 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define WIN_COLH_REG 0x0015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define WIN_COLL_REG 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define WIN_HEIGHTH_REG 0x0017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define WIN_HEIGHTL_REG 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WIN_WIDTHH_REG 0x0019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define WIN_WIDTHL_REG 0x001A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HBLANKH_REG 0x001B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HBLANKL_REG 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VSYNCH_REG 0x001D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VSYNCL_REG 0x001E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* VSYNC control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VS_CTL_REG(n) (0x00A1 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* page 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ISP_CTL_REG(n) (0x0110 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define YOFS_REG 0x0119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DARK_YOFS_REG 0x011A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SAT_CTL_REG 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BSAT_REG 0x0121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RSAT_REG 0x0122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Color correction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CMC_CTL_REG 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CMC_OFSGH_REG 0x0133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CMC_OFSGL_REG 0x0135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CMC_SIGN_REG 0x0136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CMC_GOFS_REG 0x0137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CMC_COEF_REG(n) (0x0138 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CMC_OFS_REG(n) (0x0141 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Gamma correction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GMA_CTL_REG 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GMA_COEF_REG(n) (0x0161 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Lens Shading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LENS_CTRL_REG 0x01D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LENS_XCEN_REG 0x01D1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LENS_YCEN_REG 0x01D2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LENS_RC_REG 0x01D3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LENS_GC_REG 0x01D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LENS_BC_REG 0x01D5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define L_AGON_REG 0x01D6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define L_AGOFF_REG 0x01D7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Page 3 - Auto Exposure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AE_CTL_REG(n) (0x0310 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AE_CTL9_REG 0x032C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AE_CTL10_REG 0x032D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AE_YLVL_REG 0x031C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AE_YTH_REG(n) (0x031D + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AE_WGT_REG 0x0326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define EXP_TIMEH_REG 0x0333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define EXP_TIMEM_REG 0x0334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define EXP_TIMEL_REG 0x0335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define EXP_MMINH_REG 0x0336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define EXP_MMINL_REG 0x0337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define EXP_MMAXH_REG 0x0338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define EXP_MMAXM_REG 0x0339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define EXP_MMAXL_REG 0x033A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Page 4 - Auto White Balance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AWB_CTL_REG(n) (0x0410 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AWB_ENABE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AWB_WGHT_REG 0x0419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BGAIN_PAR_REG(n) (0x044F + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Manual white balance, when AWB_CTL2[0]=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MWB_RGAIN_REG 0x0466
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MWB_BGAIN_REG 0x0467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* The token to mark an array end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define REG_TERM 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct noon010_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum v4l2_colorspace colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u16 ispctl1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct noon010_frmsize {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u16 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int vid_ctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const char * const noon010_supply_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "vdd_core", "vddio", "vdda"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define NOON010_NUM_SUPPLIES ARRAY_SIZE(noon010_supply_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct noon010_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct regulator_bulk_data supply[NOON010_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 gpio_nreset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 gpio_nstby;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Protects the struct members below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct noon010_format *curr_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) const struct noon010_frmsize *curr_win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int apply_new_cfg:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int streaming:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int hflip:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int vflip:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int power:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 i2c_reg_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct i2c_regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Supported resolutions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct noon010_frmsize noon010_sizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .width = 352,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .height = 288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .vid_ctl1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .width = 176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .height = 144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .vid_ctl1 = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .width = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .height = 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .vid_ctl1 = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Supported pixel formats. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct noon010_format noon010_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .code = MEDIA_BUS_FMT_YUYV8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .ispctl1_reg = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .code = MEDIA_BUS_FMT_YVYU8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .ispctl1_reg = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .code = MEDIA_BUS_FMT_VYUY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .ispctl1_reg = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .code = MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .ispctl1_reg = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .ispctl1_reg = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct i2c_regval noon010_base_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { WIN_COLL_REG, 0x06 }, { HBLANKL_REG, 0x7C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Color corection and saturation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { ISP_CTL_REG(0), 0x30 }, { ISP_CTL_REG(2), 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { YOFS_REG, 0x80 }, { DARK_YOFS_REG, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { SAT_CTL_REG, 0x1F }, { BSAT_REG, 0x90 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { CMC_CTL_REG, 0x0F }, { CMC_OFSGH_REG, 0x3C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { CMC_OFSGL_REG, 0x2C }, { CMC_SIGN_REG, 0x3F },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { CMC_COEF_REG(0), 0x79 }, { CMC_OFS_REG(0), 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { CMC_COEF_REG(1), 0x39 }, { CMC_OFS_REG(1), 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { CMC_COEF_REG(2), 0x00 }, { CMC_OFS_REG(2), 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { CMC_COEF_REG(3), 0x11 }, { CMC_OFS_REG(3), 0x8B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { CMC_COEF_REG(4), 0x65 }, { CMC_OFS_REG(4), 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { CMC_COEF_REG(5), 0x14 }, { CMC_OFS_REG(5), 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { CMC_COEF_REG(6), 0x01 }, { CMC_OFS_REG(6), 0x9C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { CMC_COEF_REG(7), 0x33 }, { CMC_OFS_REG(7), 0x89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { CMC_COEF_REG(8), 0x74 }, { CMC_OFS_REG(8), 0x25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Automatic white balance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { AWB_CTL_REG(0), 0x78 }, { AWB_CTL_REG(1), 0x2E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { AWB_CTL_REG(2), 0x20 }, { AWB_CTL_REG(3), 0x85 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Auto exposure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { AE_CTL_REG(0), 0xDC }, { AE_CTL_REG(1), 0x81 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { AE_CTL_REG(2), 0x30 }, { AE_CTL_REG(3), 0xA5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { AE_CTL_REG(4), 0x40 }, { AE_CTL_REG(5), 0x51 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { AE_CTL_REG(6), 0x33 }, { AE_CTL_REG(7), 0x7E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { AE_CTL9_REG, 0x00 }, { AE_CTL10_REG, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { AE_YLVL_REG, 0x44 }, { AE_YTH_REG(0), 0x34 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { AE_YTH_REG(1), 0x30 }, { AE_WGT_REG, 0xD5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Lens shading compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { LENS_CTRL_REG, 0x01 }, { LENS_XCEN_REG, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { LENS_YCEN_REG, 0x70 }, { LENS_RC_REG, 0x53 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { LENS_GC_REG, 0x40 }, { LENS_BC_REG, 0x3E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { REG_TERM, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static inline struct noon010_info *to_noon010(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return container_of(sd, struct noon010_info, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return &container_of(ctrl->handler, struct noon010_info, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline int set_i2c_page(struct noon010_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct i2c_client *client, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 page = reg >> 8 & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (info->i2c_reg_page != page && (reg & 0xFF) != 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = i2c_smbus_write_byte_data(client, PAGEMODE_REG, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) info->i2c_reg_page = page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int cam_i2c_read(struct v4l2_subdev *sd, u32 reg_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct noon010_info *info = to_noon010(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int ret = set_i2c_page(info, client, reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return i2c_smbus_read_byte_data(client, reg_addr & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int cam_i2c_write(struct v4l2_subdev *sd, u32 reg_addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct noon010_info *info = to_noon010(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int ret = set_i2c_page(info, client, reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return i2c_smbus_write_byte_data(client, reg_addr & 0xFF, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static inline int noon010_bulk_write_reg(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) const struct i2c_regval *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) while (msg->addr != REG_TERM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int ret = cam_i2c_write(sd, msg->addr, msg->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Device reset and sleep mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int noon010_power_ctrl(struct v4l2_subdev *sd, bool reset, bool sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct noon010_info *info = to_noon010(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u8 reg = sleep ? 0xF1 : 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = cam_i2c_write(sd, POWER_CTRL_REG, reg | 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ret = cam_i2c_write(sd, POWER_CTRL_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (reset && !ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) info->i2c_reg_page = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Automatic white balance control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int noon010_enable_autowhitebalance(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = cam_i2c_write(sd, AWB_CTL_REG(1), on ? 0x2E : 0x2F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = cam_i2c_write(sd, AWB_CTL_REG(0), on ? 0xFB : 0x7B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Called with struct noon010_info.lock mutex held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int noon010_set_flip(struct v4l2_subdev *sd, int hflip, int vflip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct noon010_info *info = to_noon010(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int reg, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) reg = cam_i2c_read(sd, VDO_CTL_REG(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) reg &= 0x7C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (hflip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) reg |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (vflip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) reg |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = cam_i2c_write(sd, VDO_CTL_REG(1), reg | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) info->hflip = hflip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) info->vflip = vflip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Configure resolution and color format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int noon010_set_params(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct noon010_info *info = to_noon010(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int ret = cam_i2c_write(sd, VDO_CTL_REG(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) info->curr_win->vid_ctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return cam_i2c_write(sd, ISP_CTL_REG(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) info->curr_fmt->ispctl1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Find nearest matching image pixel size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int noon010_try_frame_size(struct v4l2_mbus_framefmt *mf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) const struct noon010_frmsize **size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned int min_err = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int i = ARRAY_SIZE(noon010_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) const struct noon010_frmsize *fsize = &noon010_sizes[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *match = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int err = abs(fsize->width - mf->width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) + abs(fsize->height - mf->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (err < min_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) match = fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) fsize++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mf->width = match->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mf->height = match->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) *size = match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Called with info.lock mutex held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int power_enable(struct noon010_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (info->power) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) v4l2_info(&info->sd, "%s: sensor is already on\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (gpio_is_valid(info->gpio_nstby))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) gpio_set_value(info->gpio_nstby, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (gpio_is_valid(info->gpio_nreset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) gpio_set_value(info->gpio_nreset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = regulator_bulk_enable(NOON010_NUM_SUPPLIES, info->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (gpio_is_valid(info->gpio_nreset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) gpio_set_value(info->gpio_nreset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (gpio_is_valid(info->gpio_nstby)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) gpio_set_value(info->gpio_nstby, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (gpio_is_valid(info->gpio_nreset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) gpio_set_value(info->gpio_nreset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) gpio_set_value(info->gpio_nreset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) info->power = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) v4l2_dbg(1, debug, &info->sd, "%s: sensor is on\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Called with info.lock mutex held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int power_disable(struct noon010_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!info->power) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) v4l2_info(&info->sd, "%s: sensor is already off\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = regulator_bulk_disable(NOON010_NUM_SUPPLIES, info->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (gpio_is_valid(info->gpio_nstby))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) gpio_set_value(info->gpio_nstby, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (gpio_is_valid(info->gpio_nreset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) gpio_set_value(info->gpio_nreset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) info->power = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) v4l2_dbg(1, debug, &info->sd, "%s: sensor is off\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static int noon010_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct noon010_info *info = to_noon010(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) v4l2_dbg(1, debug, sd, "%s: ctrl_id: %d, value: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * If the device is not powered up by the host driver do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * not apply any controls to H/W at this time. Instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * the controls will be restored right after power-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!info->power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case V4L2_CID_AUTO_WHITE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = noon010_enable_autowhitebalance(sd, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case V4L2_CID_BLUE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret = cam_i2c_write(sd, MWB_BGAIN_REG, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case V4L2_CID_RED_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = cam_i2c_write(sd, MWB_RGAIN_REG, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int noon010_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (code->index >= ARRAY_SIZE(noon010_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) code->code = noon010_formats[code->index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int noon010_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct noon010_info *info = to_noon010(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct v4l2_mbus_framefmt *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) mf = v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) fmt->format = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mf = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mf->width = info->curr_win->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mf->height = info->curr_win->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) mf->code = info->curr_fmt->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) mf->colorspace = info->curr_fmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Return nearest media bus frame format. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const struct noon010_format *noon010_try_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct v4l2_mbus_framefmt *mf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int i = ARRAY_SIZE(noon010_formats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) while (--i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (mf->code == noon010_formats[i].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mf->code = noon010_formats[i].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return &noon010_formats[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int noon010_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct noon010_info *info = to_noon010(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) const struct noon010_frmsize *size = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) const struct noon010_format *nf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct v4l2_mbus_framefmt *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) nf = noon010_try_fmt(sd, &fmt->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) noon010_try_frame_size(&fmt->format, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) fmt->format.colorspace = V4L2_COLORSPACE_JPEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mf = v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) *mf = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!info->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) info->apply_new_cfg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) info->curr_fmt = nf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) info->curr_win = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Called with struct noon010_info.lock mutex held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int noon010_base_config(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int ret = noon010_bulk_write_reg(sd, noon010_base_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ret = noon010_set_params(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = noon010_set_flip(sd, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int noon010_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct noon010_info *info = to_noon010(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ret = power_enable(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ret = noon010_base_config(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) noon010_power_ctrl(sd, false, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ret = power_disable(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Restore the controls state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (!ret && on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ret = v4l2_ctrl_handler_setup(&info->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int noon010_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct noon010_info *info = to_noon010(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (!info->streaming != !on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = noon010_power_ctrl(sd, false, !on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) info->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (!ret && on && info->apply_new_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = noon010_set_params(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) info->apply_new_cfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int noon010_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct noon010_info *info = to_noon010(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) v4l2_ctrl_handler_log_status(&info->hdl, sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static int noon010_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct v4l2_mbus_framefmt *mf = v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) mf->width = noon010_sizes[0].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) mf->height = noon010_sizes[0].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) mf->code = noon010_formats[0].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) mf->colorspace = V4L2_COLORSPACE_JPEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static const struct v4l2_subdev_internal_ops noon010_subdev_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .open = noon010_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const struct v4l2_ctrl_ops noon010_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .s_ctrl = noon010_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static const struct v4l2_subdev_core_ops noon010_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .s_power = noon010_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .log_status = noon010_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static const struct v4l2_subdev_pad_ops noon010_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .enum_mbus_code = noon010_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .get_fmt = noon010_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .set_fmt = noon010_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static const struct v4l2_subdev_video_ops noon010_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .s_stream = noon010_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static const struct v4l2_subdev_ops noon010_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .core = &noon010_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .pad = &noon010_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .video = &noon010_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* Return 0 if NOON010PC30L sensor type was detected or -ENODEV otherwise. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static int noon010_detect(struct i2c_client *client, struct noon010_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = power_enable(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = i2c_smbus_read_byte_data(client, DEVICE_ID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dev_err(&client->dev, "I2C read failed: 0x%X\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) power_disable(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ret == NOON010PC30_ID ? 0 : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static int noon010_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct noon010_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) const struct noon010pc30_platform_data *pdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dev_err(&client->dev, "No platform data!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) mutex_init(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) sd = &info->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) v4l2_i2c_subdev_init(sd, client, &noon010_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Static name; NEVER use in new drivers! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) strscpy(sd->name, MODULE_NAME, sizeof(sd->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) sd->internal_ops = &noon010_subdev_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) v4l2_ctrl_handler_init(&info->hdl, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) v4l2_ctrl_new_std(&info->hdl, &noon010_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) v4l2_ctrl_new_std(&info->hdl, &noon010_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) V4L2_CID_RED_BALANCE, 0, 127, 1, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) v4l2_ctrl_new_std(&info->hdl, &noon010_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) V4L2_CID_BLUE_BALANCE, 0, 127, 1, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) sd->ctrl_handler = &info->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = info->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) goto np_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) info->i2c_reg_page = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) info->gpio_nreset = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) info->gpio_nstby = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) info->curr_fmt = &noon010_formats[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) info->curr_win = &noon010_sizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (gpio_is_valid(pdata->gpio_nreset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = devm_gpio_request_one(&client->dev, pdata->gpio_nreset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) GPIOF_OUT_INIT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) "NOON010PC30 NRST");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev_err(&client->dev, "GPIO request error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) goto np_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) info->gpio_nreset = pdata->gpio_nreset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) gpio_export(info->gpio_nreset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (gpio_is_valid(pdata->gpio_nstby)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = devm_gpio_request_one(&client->dev, pdata->gpio_nstby,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) GPIOF_OUT_INIT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "NOON010PC30 NSTBY");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_err(&client->dev, "GPIO request error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) goto np_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) info->gpio_nstby = pdata->gpio_nstby;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) gpio_export(info->gpio_nstby, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) for (i = 0; i < NOON010_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) info->supply[i].supply = noon010_supply_name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = devm_regulator_bulk_get(&client->dev, NOON010_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) info->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) goto np_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) info->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ret = media_entity_pads_init(&sd->entity, 1, &info->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) goto np_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ret = noon010_detect(client, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) np_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) v4l2_ctrl_handler_free(&info->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int noon010_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct noon010_info *info = to_noon010(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) v4l2_ctrl_handler_free(&info->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static const struct i2c_device_id noon010_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) { MODULE_NAME, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) MODULE_DEVICE_TABLE(i2c, noon010_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static struct i2c_driver noon010_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .name = MODULE_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .probe = noon010_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .remove = noon010_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .id_table = noon010_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) module_i2c_driver(noon010_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) MODULE_DESCRIPTION("Siliconfile NOON010PC30 camera driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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