^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * V4L2 sensor driver for Aptina MT9V111 image sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2018 Jacopo Mondi <jacopo@jmondi.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on mt9v032 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Based on mt9v011 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 2009 Mauro Carvalho Chehab <mchehab@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-image-sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * MT9V111 is a 1/4-Inch CMOS digital image sensor with an integrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Image Flow Processing (IFP) engine and a sensor core loosely based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * MT9V011.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * The IFP can produce several output image formats from the sensor core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * output. This driver currently supports only YUYV format permutations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * The driver allows manual frame rate control through s_frame_interval subdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * operation or V4L2_CID_V/HBLANK controls, but it is known that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * auto-exposure algorithm might modify the programmed frame rate. While the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * driver initially programs the sensor with auto-exposure and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * auto-white-balancing enabled, it is possible to disable them and more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * precisely control the frame rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * While it seems possible to instruct the auto-exposure control algorithm to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * respect a programmed frame rate when adjusting the pixel integration time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * registers controlling this feature are not documented in the public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * available sensor manual used to develop this driver (09005aef80e90084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * MT9V111_1.fm - Rev. G 1/05 EN).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MT9V111_CHIP_ID_HIGH 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MT9V111_CHIP_ID_LOW 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MT9V111_R01_ADDR_SPACE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MT9V111_R01_IFP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MT9V111_R01_CORE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MT9V111_IFP_R06_OPMODE_CTRL 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MT9V111_IFP_R06_OPMODE_CTRL_AWB_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MT9V111_IFP_R06_OPMODE_CTRL_AE_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MT9V111_IFP_R07_IFP_RESET 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MT9V111_IFP_R07_IFP_RESET_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MT9V111_IFP_R08_OUTFMT_CTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MT9V111_IFP_R08_OUTFMT_CTRL_FLICKER BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MT9V111_IFP_R08_OUTFMT_CTRL_PCLK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MT9V111_IFP_R3A_OUTFMT_CTRL2 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MT9V111_IFP_R3A_OUTFMT_CTRL2_SWAP_CBCR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MT9V111_IFP_R3A_OUTFMT_CTRL2_SWAP_YC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MT9V111_IFP_R3A_OUTFMT_CTRL2_SWAP_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MT9V111_IFP_RA5_HPAN 0xa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MT9V111_IFP_RA6_HZOOM 0xa6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MT9V111_IFP_RA7_HOUT 0xa7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MT9V111_IFP_RA8_VPAN 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MT9V111_IFP_RA9_VZOOM 0xa9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MT9V111_IFP_RAA_VOUT 0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MT9V111_IFP_DECIMATION_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MT9V111_IFP_DECIMATION_FREEZE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MT9V111_CORE_R03_WIN_HEIGHT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MT9V111_CORE_R03_WIN_V_OFFS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MT9V111_CORE_R04_WIN_WIDTH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MT9V111_CORE_R04_WIN_H_OFFS 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MT9V111_CORE_R05_HBLANK 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MT9V111_CORE_R05_MIN_HBLANK 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MT9V111_CORE_R05_MAX_HBLANK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MT9V111_CORE_R05_DEF_HBLANK 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MT9V111_CORE_R06_VBLANK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MT9V111_CORE_R06_MIN_VBLANK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MT9V111_CORE_R06_MAX_VBLANK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MT9V111_CORE_R06_DEF_VBLANK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MT9V111_CORE_R07_OUT_CTRL 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MT9V111_CORE_R07_OUT_CTRL_SAMPLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MT9V111_CORE_R09_PIXEL_INT 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MT9V111_CORE_R09_PIXEL_INT_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MT9V111_CORE_R0D_CORE_RESET 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MT9V111_CORE_R0D_CORE_RESET_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MT9V111_CORE_RFF_CHIP_VER 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MT9V111_PIXEL_ARRAY_WIDTH 640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MT9V111_PIXEL_ARRAY_HEIGHT 480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MT9V111_MAX_CLKIN 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* The default sensor configuration at startup time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct v4l2_mbus_framefmt mt9v111_def_fmt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .code = MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .field = V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .ycbcr_enc = V4L2_YCBCR_ENC_601,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .quantization = V4L2_QUANTIZATION_LIM_RANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .xfer_func = V4L2_XFER_FUNC_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct mt9v111_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 addr_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #if IS_ENABLED(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct v4l2_ctrl *auto_awb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_ctrl *auto_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct v4l2_ctrl_handler ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Output image format and sizes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_mbus_framefmt fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Protects power up/down sequences. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct mutex pwr_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int pwr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Protects stream on/off sequences. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct mutex stream_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Flags to mark HW settings as not yet applied. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bool pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Clock provider and system clock frequency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct gpio_desc *oe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct gpio_desc *standby;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct gpio_desc *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define sd_to_mt9v111(__sd) container_of((__sd), struct mt9v111_dev, sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * mt9v111_mbus_fmt - List all media bus formats supported by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Only list the media bus code here. The image sizes are freely configurable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * in the pixel array sizes range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * The desired frame interval, in the supported frame interval range, is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * obtained by configuring blanking as the sensor does not have a PLL but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * only a fixed clock divider that generates the output pixel clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static struct mt9v111_mbus_fmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } mt9v111_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .code = MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .code = MEDIA_BUS_FMT_YUYV8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .code = MEDIA_BUS_FMT_VYUY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .code = MEDIA_BUS_FMT_YVYU8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static u32 mt9v111_frame_intervals[] = {5, 10, 15, 20, 30};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * mt9v111_frame_sizes - List sensor's supported resolutions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Resolution generated through decimation in the IFP block from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * full VGA pixel array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct v4l2_rect mt9v111_frame_sizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .width = 352,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .height = 288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .width = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .height = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .width = 176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .height = 144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .width = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .height = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* --- Device I/O access --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int __mt9v111_read(struct i2c_client *c, u8 reg, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) __be16 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) msg[0].addr = c->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) msg[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) msg[0].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) msg[0].buf = ®
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) msg[1].addr = c->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) msg[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) msg[1].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) msg[1].buf = (char *)&buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = i2c_transfer(c->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(&c->dev, "i2c read transfer error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *val = be16_to_cpu(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_dbg(&c->dev, "%s: %x=%x\n", __func__, reg, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int __mt9v111_write(struct i2c_client *c, u8 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u8 buf[3] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) buf[0] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) buf[1] = val >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) buf[2] = val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) msg.addr = c->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) msg.len = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) msg.buf = (char *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev_dbg(&c->dev, "%s: %x = %x%x\n", __func__, reg, buf[1], buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = i2c_transfer(c->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_err(&c->dev, "i2c write transfer error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int __mt9v111_addr_space_select(struct i2c_client *c, u16 addr_space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct v4l2_subdev *sd = i2c_get_clientdata(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (mt9v111->addr_space == addr_space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = __mt9v111_write(c, MT9V111_R01_ADDR_SPACE, addr_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Verify address space has been updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = __mt9v111_read(c, MT9V111_R01_ADDR_SPACE, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (val != addr_space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mt9v111->addr_space = addr_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int mt9v111_read(struct i2c_client *c, u8 addr_space, u8 reg, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Select register address space first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = __mt9v111_addr_space_select(c, addr_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = __mt9v111_read(c, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int mt9v111_write(struct i2c_client *c, u8 addr_space, u8 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Select register address space first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = __mt9v111_addr_space_select(c, addr_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = __mt9v111_write(c, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int mt9v111_update(struct i2c_client *c, u8 addr_space, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u16 mask, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u16 current_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Select register address space first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = __mt9v111_addr_space_select(c, addr_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Read the current register value, then update it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = __mt9v111_read(c, reg, ¤t_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) current_val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) current_val |= (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = __mt9v111_write(c, reg, current_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* --- Sensor HW operations --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int __mt9v111_power_on(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = clk_prepare_enable(mt9v111->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) clk_set_rate(mt9v111->clk, mt9v111->sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) gpiod_set_value(mt9v111->standby, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) gpiod_set_value(mt9v111->oe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int __mt9v111_power_off(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) gpiod_set_value(mt9v111->oe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) gpiod_set_value(mt9v111->standby, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) clk_disable_unprepare(mt9v111->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int __mt9v111_hw_reset(struct mt9v111_dev *mt9v111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!mt9v111->reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) gpiod_set_value(mt9v111->reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) gpiod_set_value(mt9v111->reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int __mt9v111_sw_reset(struct mt9v111_dev *mt9v111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct i2c_client *c = mt9v111->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Software reset core and IFP blocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = mt9v111_update(c, MT9V111_R01_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MT9V111_CORE_R0D_CORE_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MT9V111_CORE_R0D_CORE_RESET_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = mt9v111_update(c, MT9V111_R01_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MT9V111_CORE_R0D_CORE_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MT9V111_CORE_R0D_CORE_RESET_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = mt9v111_update(c, MT9V111_R01_IFP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MT9V111_IFP_R07_IFP_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MT9V111_IFP_R07_IFP_RESET_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret = mt9v111_update(c, MT9V111_R01_IFP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MT9V111_IFP_R07_IFP_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MT9V111_IFP_R07_IFP_RESET_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int mt9v111_calc_frame_rate(struct mt9v111_dev *mt9v111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct v4l2_fract *tpf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned int fps = tpf->numerator ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) tpf->denominator / tpf->numerator :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) tpf->denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned int best_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unsigned int frm_cols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned int row_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned int best_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned int pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned int diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned int hb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned int vb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Approximate to the closest supported frame interval. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) best_diff = ~0L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) for (i = 0, idx = 0; i < ARRAY_SIZE(mt9v111_frame_intervals); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) diff = abs(fps - mt9v111_frame_intervals[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (diff < best_diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) best_diff = diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) fps = mt9v111_frame_intervals[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * The sensor does not provide a PLL circuitry and pixel clock is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * generated dividing the master clock source by two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * Trow = (W + Hblank + 114) * 2 * (1 / SYSCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * TFrame = Trow * (H + Vblank + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * FPS = (SYSCLK / 2) / (Trow * (H + Vblank + 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * This boils down to tune H and V blanks to best approximate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * above equation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * Test all available H/V blank values, until we reach the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * desired frame rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) best_fps = vb = hb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pclk = DIV_ROUND_CLOSEST(mt9v111->sysclk, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) row_pclk = MT9V111_PIXEL_ARRAY_WIDTH + 7 + MT9V111_CORE_R04_WIN_H_OFFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) frm_cols = MT9V111_PIXEL_ARRAY_HEIGHT + 7 + MT9V111_CORE_R03_WIN_V_OFFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) best_diff = ~0L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) for (vb = MT9V111_CORE_R06_MIN_VBLANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) vb < MT9V111_CORE_R06_MAX_VBLANK; vb++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) for (hb = MT9V111_CORE_R05_MIN_HBLANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) hb < MT9V111_CORE_R05_MAX_HBLANK; hb += 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned int t_frame = (row_pclk + hb) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) (frm_cols + vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) unsigned int t_fps = DIV_ROUND_CLOSEST(pclk, t_frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) diff = abs(fps - t_fps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (diff < best_diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) best_diff = diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) best_fps = t_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (diff == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (diff == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = v4l2_ctrl_s_ctrl_int64(mt9v111->hblank, hb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = v4l2_ctrl_s_ctrl_int64(mt9v111->vblank, vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) tpf->numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) tpf->denominator = best_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int mt9v111_hw_config(struct mt9v111_dev *mt9v111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct i2c_client *c = mt9v111->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u16 outfmtctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Force device reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ret = __mt9v111_hw_reset(mt9v111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (ret == -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret = __mt9v111_sw_reset(mt9v111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Configure internal clock sample rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = mt9v111->sysclk < DIV_ROUND_CLOSEST(MT9V111_MAX_CLKIN, 2) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mt9v111_update(c, MT9V111_R01_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MT9V111_CORE_R07_OUT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MT9V111_CORE_R07_OUT_CTRL_SAMPLE, 1) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) mt9v111_update(c, MT9V111_R01_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MT9V111_CORE_R07_OUT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MT9V111_CORE_R07_OUT_CTRL_SAMPLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * Configure output image format components ordering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * TODO: IFP block can also output several RGB permutations, we only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * support YUYV permutations at the moment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) switch (mt9v111->fmt.code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case MEDIA_BUS_FMT_YUYV8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) outfmtctrl2 = MT9V111_IFP_R3A_OUTFMT_CTRL2_SWAP_YC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case MEDIA_BUS_FMT_VYUY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) outfmtctrl2 = MT9V111_IFP_R3A_OUTFMT_CTRL2_SWAP_CBCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case MEDIA_BUS_FMT_YVYU8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) outfmtctrl2 = MT9V111_IFP_R3A_OUTFMT_CTRL2_SWAP_YC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MT9V111_IFP_R3A_OUTFMT_CTRL2_SWAP_CBCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) outfmtctrl2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = mt9v111_update(c, MT9V111_R01_IFP, MT9V111_IFP_R3A_OUTFMT_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) MT9V111_IFP_R3A_OUTFMT_CTRL2_SWAP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) outfmtctrl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * Do not change default sensor's core configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * output the whole 640x480 pixel array, skip 18 columns and 6 rows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * Instead, control the output image size through IFP block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * TODO: No zoom&pan support. Currently we control the output image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * size only through decimation, with no zoom support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ret = mt9v111_write(c, MT9V111_R01_IFP, MT9V111_IFP_RA5_HPAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MT9V111_IFP_DECIMATION_FREEZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = mt9v111_write(c, MT9V111_R01_IFP, MT9V111_IFP_RA8_VPAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MT9V111_IFP_DECIMATION_FREEZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = mt9v111_write(c, MT9V111_R01_IFP, MT9V111_IFP_RA6_HZOOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MT9V111_IFP_DECIMATION_FREEZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MT9V111_PIXEL_ARRAY_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = mt9v111_write(c, MT9V111_R01_IFP, MT9V111_IFP_RA9_VZOOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) MT9V111_IFP_DECIMATION_FREEZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) MT9V111_PIXEL_ARRAY_HEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ret = mt9v111_write(c, MT9V111_R01_IFP, MT9V111_IFP_RA7_HOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) MT9V111_IFP_DECIMATION_FREEZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mt9v111->fmt.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = mt9v111_write(c, MT9V111_R01_IFP, MT9V111_IFP_RAA_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mt9v111->fmt.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Apply controls to set auto exp, auto awb and timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret = v4l2_ctrl_handler_setup(&mt9v111->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * Set pixel integration time to the whole frame time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * This value controls the the shutter delay when running with AE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * disabled. If longer than frame time, it affects the output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * frame rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return mt9v111_write(c, MT9V111_R01_CORE, MT9V111_CORE_R09_PIXEL_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) MT9V111_PIXEL_ARRAY_HEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* --- V4L2 subdev operations --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int mt9v111_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int pwr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) mutex_lock(&mt9v111->pwr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * Make sure we're transitioning from 0 to 1, or viceversa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * before actually changing the power state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) pwr_count = mt9v111->pwr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) pwr_count += on ? 1 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (pwr_count == !!on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ret = on ? __mt9v111_power_on(sd) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) __mt9v111_power_off(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* All went well, updated power counter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) mt9v111->pwr_count = pwr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) mutex_unlock(&mt9v111->pwr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * Update power counter to keep track of how many nested calls we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) WARN_ON(pwr_count < 0 || pwr_count > 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) mt9v111->pwr_count = pwr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mutex_unlock(&mt9v111->pwr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int mt9v111_s_stream(struct v4l2_subdev *subdev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct mt9v111_dev *mt9v111 = sd_to_mt9v111(subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) mutex_lock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (mt9v111->streaming == enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) mutex_unlock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = mt9v111_s_power(subdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) goto error_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (enable && mt9v111->pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ret = mt9v111_hw_config(mt9v111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) goto error_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * No need to update control here as far as only H/VBLANK are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * supported and immediately programmed to registers in .s_ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mt9v111->pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) mt9v111->streaming = enable ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) mutex_unlock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) error_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) mutex_unlock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int mt9v111_s_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct v4l2_subdev_frame_interval *ival)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct v4l2_fract *tpf = &ival->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) unsigned int fps = tpf->numerator ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) tpf->denominator / tpf->numerator :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) tpf->denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) unsigned int max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (!tpf->numerator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) tpf->numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) mutex_lock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (mt9v111->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) mutex_unlock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (mt9v111->fps == fps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) mutex_unlock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* Make sure frame rate/image sizes constraints are respected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (mt9v111->fmt.width < QVGA_WIDTH &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) mt9v111->fmt.height < QVGA_HEIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) max_fps = 90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) else if (mt9v111->fmt.width < CIF_WIDTH &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) mt9v111->fmt.height < CIF_HEIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) max_fps = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) max_fps = mt9v111->sysclk <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) DIV_ROUND_CLOSEST(MT9V111_MAX_CLKIN, 2) ? 15 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (fps > max_fps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) mutex_unlock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) mt9v111_calc_frame_rate(mt9v111, tpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mt9v111->fps = fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mt9v111->pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mutex_unlock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int mt9v111_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct v4l2_subdev_frame_interval *ival)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct v4l2_fract *tpf = &ival->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) mutex_lock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) tpf->numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) tpf->denominator = mt9v111->fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mutex_unlock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static struct v4l2_mbus_framefmt *__mt9v111_get_pad_format(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct mt9v111_dev *mt9v111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) enum v4l2_subdev_format_whence which)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) switch (which) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) case V4L2_SUBDEV_FORMAT_TRY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #if IS_ENABLED(CONFIG_VIDEO_V4L2_SUBDEV_API)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return v4l2_subdev_get_try_format(&mt9v111->sd, cfg, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return &cfg->try_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) case V4L2_SUBDEV_FORMAT_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return &mt9v111->fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static int mt9v111_enum_mbus_code(struct v4l2_subdev *subdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (code->pad || code->index > ARRAY_SIZE(mt9v111_formats) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) code->code = mt9v111_formats[code->index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int mt9v111_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (fie->pad || fie->index >= ARRAY_SIZE(mt9v111_frame_intervals))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) for (i = 0; i < ARRAY_SIZE(mt9v111_frame_sizes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (fie->width == mt9v111_frame_sizes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) fie->height == mt9v111_frame_sizes[i].height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (i == ARRAY_SIZE(mt9v111_frame_sizes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) fie->interval.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) fie->interval.denominator = mt9v111_frame_intervals[fie->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static int mt9v111_enum_frame_size(struct v4l2_subdev *subdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (fse->pad || fse->index >= ARRAY_SIZE(mt9v111_frame_sizes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) fse->min_width = mt9v111_frame_sizes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) fse->max_width = mt9v111_frame_sizes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) fse->min_height = mt9v111_frame_sizes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) fse->max_height = mt9v111_frame_sizes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int mt9v111_get_format(struct v4l2_subdev *subdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct mt9v111_dev *mt9v111 = sd_to_mt9v111(subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) mutex_lock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) format->format = *__mt9v111_get_pad_format(mt9v111, cfg, format->pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) format->which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) mutex_unlock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static int mt9v111_set_format(struct v4l2_subdev *subdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct mt9v111_dev *mt9v111 = sd_to_mt9v111(subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct v4l2_mbus_framefmt new_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct v4l2_mbus_framefmt *__fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) unsigned int best_fit = ~0L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) unsigned int idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) mutex_lock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (mt9v111->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) mutex_unlock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (format->pad) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) mutex_unlock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* Update mbus format code and sizes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) for (i = 0; i < ARRAY_SIZE(mt9v111_formats); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (format->format.code == mt9v111_formats[i].code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) new_fmt.code = mt9v111_formats[i].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (i == ARRAY_SIZE(mt9v111_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) new_fmt.code = mt9v111_formats[0].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) for (i = 0; i < ARRAY_SIZE(mt9v111_frame_sizes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) unsigned int fit = abs(mt9v111_frame_sizes[i].width -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) format->format.width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) abs(mt9v111_frame_sizes[i].height -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) format->format.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (fit < best_fit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) best_fit = fit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (fit == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) new_fmt.width = mt9v111_frame_sizes[idx].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) new_fmt.height = mt9v111_frame_sizes[idx].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* Update the device (or pad) format if it has changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) __fmt = __mt9v111_get_pad_format(mt9v111, cfg, format->pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) format->which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* Format hasn't changed, stop here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (__fmt->code == new_fmt.code &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) __fmt->width == new_fmt.width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) __fmt->height == new_fmt.height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* Update the format and sizes, then mark changes as pending. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) __fmt->code = new_fmt.code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) __fmt->width = new_fmt.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) __fmt->height = new_fmt.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) mt9v111->pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dev_dbg(mt9v111->dev, "%s: mbus_code: %x - (%ux%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) __func__, __fmt->code, __fmt->width, __fmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) format->format = *__fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) mutex_unlock(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static int mt9v111_init_cfg(struct v4l2_subdev *subdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct v4l2_subdev_pad_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) cfg->try_fmt = mt9v111_def_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static const struct v4l2_subdev_core_ops mt9v111_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .s_power = mt9v111_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static const struct v4l2_subdev_video_ops mt9v111_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .s_stream = mt9v111_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .s_frame_interval = mt9v111_s_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .g_frame_interval = mt9v111_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static const struct v4l2_subdev_pad_ops mt9v111_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .init_cfg = mt9v111_init_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .enum_mbus_code = mt9v111_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .enum_frame_size = mt9v111_enum_frame_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .enum_frame_interval = mt9v111_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .get_fmt = mt9v111_get_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .set_fmt = mt9v111_set_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static const struct v4l2_subdev_ops mt9v111_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .core = &mt9v111_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .video = &mt9v111_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .pad = &mt9v111_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #if IS_ENABLED(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const struct media_entity_operations mt9v111_subdev_entity_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .link_validate = v4l2_subdev_link_validate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* --- V4L2 ctrl --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static int mt9v111_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct mt9v111_dev *mt9v111 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct mt9v111_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) mutex_lock(&mt9v111->pwr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * If sensor is powered down, just cache new control values,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * no actual register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (!mt9v111->pwr_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) mt9v111->pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) mutex_unlock(&mt9v111->pwr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) mutex_unlock(&mt9v111->pwr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * Flickering control gets disabled if both auto exp and auto awb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * are disabled too. If any of the two is enabled, enable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * Disabling flickering when ae and awb are off allows a more precise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * control of the programmed frame rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (mt9v111->auto_exp->is_new || mt9v111->auto_awb->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (mt9v111->auto_exp->val == V4L2_EXPOSURE_MANUAL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) mt9v111->auto_awb->val == V4L2_WHITE_BALANCE_MANUAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ret = mt9v111_update(mt9v111->client, MT9V111_R01_IFP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) MT9V111_IFP_R08_OUTFMT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) MT9V111_IFP_R08_OUTFMT_CTRL_FLICKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret = mt9v111_update(mt9v111->client, MT9V111_R01_IFP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) MT9V111_IFP_R08_OUTFMT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) MT9V111_IFP_R08_OUTFMT_CTRL_FLICKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) case V4L2_CID_AUTO_WHITE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ret = mt9v111_update(mt9v111->client, MT9V111_R01_IFP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) MT9V111_IFP_R06_OPMODE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) MT9V111_IFP_R06_OPMODE_CTRL_AWB_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ctrl->val == V4L2_WHITE_BALANCE_AUTO ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) MT9V111_IFP_R06_OPMODE_CTRL_AWB_EN : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) case V4L2_CID_EXPOSURE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ret = mt9v111_update(mt9v111->client, MT9V111_R01_IFP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) MT9V111_IFP_R06_OPMODE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) MT9V111_IFP_R06_OPMODE_CTRL_AE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ctrl->val == V4L2_EXPOSURE_AUTO ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) MT9V111_IFP_R06_OPMODE_CTRL_AE_EN : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) case V4L2_CID_HBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ret = mt9v111_update(mt9v111->client, MT9V111_R01_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) MT9V111_CORE_R05_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) MT9V111_CORE_R05_MAX_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) mt9v111->hblank->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ret = mt9v111_update(mt9v111->client, MT9V111_R01_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) MT9V111_CORE_R06_VBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) MT9V111_CORE_R06_MAX_VBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) mt9v111->vblank->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static const struct v4l2_ctrl_ops mt9v111_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .s_ctrl = mt9v111_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static int mt9v111_chip_probe(struct mt9v111_dev *mt9v111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ret = __mt9v111_power_on(&mt9v111->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ret = mt9v111_read(mt9v111->client, MT9V111_R01_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) MT9V111_CORE_RFF_CHIP_VER, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if ((val >> 8) != MT9V111_CHIP_ID_HIGH &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) (val & 0xff) != MT9V111_CHIP_ID_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) dev_err(mt9v111->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) "Unable to identify MT9V111 chip: 0x%2x%2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) val >> 8, val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) dev_dbg(mt9v111->dev, "Chip identified: 0x%2x%2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) val >> 8, val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) __mt9v111_power_off(&mt9v111->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static int mt9v111_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct mt9v111_dev *mt9v111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct v4l2_fract tpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) mt9v111 = devm_kzalloc(&client->dev, sizeof(*mt9v111), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (!mt9v111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) mt9v111->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) mt9v111->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) mt9v111->clk = devm_clk_get(&client->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (IS_ERR(mt9v111->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return PTR_ERR(mt9v111->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) mt9v111->sysclk = clk_get_rate(mt9v111->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (mt9v111->sysclk > MT9V111_MAX_CLKIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) mt9v111->oe = devm_gpiod_get_optional(&client->dev, "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (IS_ERR(mt9v111->oe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) dev_err(&client->dev, "Unable to get GPIO \"enable\": %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PTR_ERR(mt9v111->oe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return PTR_ERR(mt9v111->oe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) mt9v111->standby = devm_gpiod_get_optional(&client->dev, "standby",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (IS_ERR(mt9v111->standby)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) dev_err(&client->dev, "Unable to get GPIO \"standby\": %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) PTR_ERR(mt9v111->standby));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return PTR_ERR(mt9v111->standby);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) mt9v111->reset = devm_gpiod_get_optional(&client->dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (IS_ERR(mt9v111->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) dev_err(&client->dev, "Unable to get GPIO \"reset\": %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) PTR_ERR(mt9v111->reset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return PTR_ERR(mt9v111->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) mutex_init(&mt9v111->pwr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) mutex_init(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) v4l2_ctrl_handler_init(&mt9v111->ctrls, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) mt9v111->auto_awb = v4l2_ctrl_new_std(&mt9v111->ctrls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) &mt9v111_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) V4L2_CID_AUTO_WHITE_BALANCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) 0, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) V4L2_WHITE_BALANCE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) mt9v111->auto_exp = v4l2_ctrl_new_std_menu(&mt9v111->ctrls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) &mt9v111_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) V4L2_CID_EXPOSURE_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) V4L2_EXPOSURE_MANUAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) 0, V4L2_EXPOSURE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) mt9v111->hblank = v4l2_ctrl_new_std(&mt9v111->ctrls, &mt9v111_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) MT9V111_CORE_R05_MIN_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) MT9V111_CORE_R05_MAX_HBLANK, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) MT9V111_CORE_R05_DEF_HBLANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) mt9v111->vblank = v4l2_ctrl_new_std(&mt9v111->ctrls, &mt9v111_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) V4L2_CID_VBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) MT9V111_CORE_R06_MIN_VBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) MT9V111_CORE_R06_MAX_VBLANK, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) MT9V111_CORE_R06_DEF_VBLANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* PIXEL_RATE is fixed: just expose it to user space. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) v4l2_ctrl_new_std(&mt9v111->ctrls, &mt9v111_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) V4L2_CID_PIXEL_RATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) DIV_ROUND_CLOSEST(mt9v111->sysclk, 2), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) DIV_ROUND_CLOSEST(mt9v111->sysclk, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (mt9v111->ctrls.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ret = mt9v111->ctrls.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) goto error_free_ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) mt9v111->sd.ctrl_handler = &mt9v111->ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* Start with default configuration: 640x480 UYVY. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) mt9v111->fmt = mt9v111_def_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* Re-calculate blankings for 640x480@15fps. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) mt9v111->fps = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) tpf.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) tpf.denominator = mt9v111->fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) mt9v111_calc_frame_rate(mt9v111, &tpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) mt9v111->pwr_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) mt9v111->addr_space = MT9V111_R01_IFP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) mt9v111->pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) v4l2_i2c_subdev_init(&mt9v111->sd, client, &mt9v111_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #if IS_ENABLED(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) mt9v111->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) mt9v111->sd.entity.ops = &mt9v111_subdev_entity_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) mt9v111->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) mt9v111->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ret = media_entity_pads_init(&mt9v111->sd.entity, 1, &mt9v111->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) goto error_free_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) ret = mt9v111_chip_probe(mt9v111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) goto error_free_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) ret = v4l2_async_register_subdev(&mt9v111->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) goto error_free_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) error_free_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #if IS_ENABLED(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) media_entity_cleanup(&mt9v111->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) error_free_ctrls:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) v4l2_ctrl_handler_free(&mt9v111->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) mutex_destroy(&mt9v111->pwr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) mutex_destroy(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static int mt9v111_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #if IS_ENABLED(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) v4l2_ctrl_handler_free(&mt9v111->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) mutex_destroy(&mt9v111->pwr_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) mutex_destroy(&mt9v111->stream_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) devm_gpiod_put(mt9v111->dev, mt9v111->oe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) devm_gpiod_put(mt9v111->dev, mt9v111->standby);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) devm_gpiod_put(mt9v111->dev, mt9v111->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) devm_clk_put(mt9v111->dev, mt9v111->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static const struct of_device_id mt9v111_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) { .compatible = "aptina,mt9v111", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static struct i2c_driver mt9v111_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .name = "mt9v111",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .of_match_table = mt9v111_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .probe_new = mt9v111_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .remove = mt9v111_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) module_i2c_driver(mt9v111_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) MODULE_DESCRIPTION("V4L2 sensor driver for Aptina MT9V111");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) MODULE_AUTHOR("Jacopo Mondi <jacopo@jmondi.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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