^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for MT9M111/MT9M112/MT9M131 CMOS Image Sensor from Micron/Aptina
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/v4l2-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * MT9M111, MT9M112 and MT9M131:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * i2c address is 0x48 or 0x5d (depending on SADDR pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The platform has to define struct i2c_board_info objects and link to them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * from struct soc_camera_host_desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Sensor core register addresses (0x000..0x0ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MT9M111_CHIP_VERSION 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MT9M111_ROW_START 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MT9M111_COLUMN_START 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MT9M111_WINDOW_HEIGHT 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MT9M111_WINDOW_WIDTH 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MT9M111_HORIZONTAL_BLANKING_B 0x005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MT9M111_VERTICAL_BLANKING_B 0x006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MT9M111_HORIZONTAL_BLANKING_A 0x007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MT9M111_VERTICAL_BLANKING_A 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MT9M111_SHUTTER_WIDTH 0x009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MT9M111_ROW_SPEED 0x00a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MT9M111_EXTRA_DELAY 0x00b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MT9M111_SHUTTER_DELAY 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MT9M111_RESET 0x00d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MT9M111_READ_MODE_B 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MT9M111_READ_MODE_A 0x021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MT9M111_FLASH_CONTROL 0x023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MT9M111_GREEN1_GAIN 0x02b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MT9M111_BLUE_GAIN 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MT9M111_RED_GAIN 0x02d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MT9M111_GREEN2_GAIN 0x02e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MT9M111_GLOBAL_GAIN 0x02f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MT9M111_CONTEXT_CONTROL 0x0c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MT9M111_PAGE_MAP 0x0f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MT9M111_BYTE_WISE_ADDR 0x0f1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MT9M111_RESET_SYNC_CHANGES (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MT9M111_RESET_RESTART_BAD_FRAME (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MT9M111_RESET_SHOW_BAD_FRAMES (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MT9M111_RESET_RESET_SOC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MT9M111_RESET_OUTPUT_DISABLE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MT9M111_RESET_CHIP_ENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MT9M111_RESET_ANALOG_STANDBY (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MT9M111_RESET_RESTART_FRAME (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MT9M111_RESET_RESET_MODE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MT9M111_RM_FULL_POWER_RD (0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MT9M111_RM_LOW_POWER_RD (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MT9M111_RM_COL_SKIP_4X (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MT9M111_RM_ROW_SKIP_4X (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MT9M111_RM_COL_SKIP_2X (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MT9M111_RM_ROW_SKIP_2X (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MT9M111_RMB_MIRROR_COLS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MT9M111_RMB_MIRROR_ROWS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MT9M111_CTXT_CTRL_RESTART (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MT9M111_CTXT_CTRL_DEFECTCOR_B (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MT9M111_CTXT_CTRL_RESIZE_B (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MT9M111_CTXT_CTRL_CTRL2_B (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MT9M111_CTXT_CTRL_GAMMA_B (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MT9M111_CTXT_CTRL_XENON_EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MT9M111_CTXT_CTRL_READ_MODE_B (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MT9M111_CTXT_CTRL_LED_FLASH_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MT9M111_CTXT_CTRL_VBLANK_SEL_B (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MT9M111_CTXT_CTRL_HBLANK_SEL_B (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Colorpipe register addresses (0x100..0x1ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MT9M111_OPER_MODE_CTRL 0x106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MT9M111_OUTPUT_FORMAT_CTRL 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MT9M111_TPG_CTRL 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MT9M111_REDUCER_XZOOM_B 0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MT9M111_REDUCER_XSIZE_B 0x1a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MT9M111_REDUCER_YZOOM_B 0x1a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MT9M111_REDUCER_YSIZE_B 0x1a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MT9M111_REDUCER_XZOOM_A 0x1a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MT9M111_REDUCER_XSIZE_A 0x1a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MT9M111_REDUCER_YZOOM_A 0x1a9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MT9M111_REDUCER_YSIZE_A 0x1aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MT9M111_EFFECTS_MODE 0x1e2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MT9M111_OPMODE_AUTOEXPO_EN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MT9M111_OPMODE_AUTOWHITEBAL_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MT9M111_OUTFMT_FLIP_BAYER_COL (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MT9M111_OUTFMT_FLIP_BAYER_ROW (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MT9M111_OUTFMT_PROCESSED_BAYER (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MT9M111_OUTFMT_BYPASS_IFP (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MT9M111_OUTFMT_INV_PIX_CLOCK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MT9M111_OUTFMT_RGB (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MT9M111_OUTFMT_RGB565 (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MT9M111_OUTFMT_RGB555 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MT9M111_OUTFMT_RGB444x (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MT9M111_OUTFMT_RGBx444 (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MT9M111_OUTFMT_TST_RAMP_OFF (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MT9M111_OUTFMT_TST_RAMP_COL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MT9M111_OUTFMT_TST_RAMP_ROW (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MT9M111_OUTFMT_TST_RAMP_FRAME (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MT9M111_OUTFMT_SHIFT_3_UP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MT9M111_OUTFMT_AVG_CHROMA (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MT9M111_TPG_SEL_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MT9M111_EFFECTS_MODE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MT9M111_RM_PWR_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MT9M111_RM_SKIP2_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Camera control register addresses (0x200..0x2ff not implemented)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) (val), (mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MT9M111_MIN_DARK_ROWS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MT9M111_MIN_DARK_COLS 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MT9M111_MAX_HEIGHT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MT9M111_MAX_WIDTH 1280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct mt9m111_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u16 read_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u16 blanking_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u16 blanking_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u16 reducer_xzoom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u16 reducer_yzoom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u16 reducer_xsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u16 reducer_ysize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u16 output_fmt_ctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u16 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct mt9m111_context context_a = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .read_mode = MT9M111_READ_MODE_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .blanking_h = MT9M111_HORIZONTAL_BLANKING_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .blanking_v = MT9M111_VERTICAL_BLANKING_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .reducer_xzoom = MT9M111_REDUCER_XZOOM_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .reducer_yzoom = MT9M111_REDUCER_YZOOM_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .reducer_xsize = MT9M111_REDUCER_XSIZE_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .reducer_ysize = MT9M111_REDUCER_YSIZE_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .control = MT9M111_CTXT_CTRL_RESTART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct mt9m111_context context_b = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .read_mode = MT9M111_READ_MODE_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .blanking_h = MT9M111_HORIZONTAL_BLANKING_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .blanking_v = MT9M111_VERTICAL_BLANKING_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .reducer_xzoom = MT9M111_REDUCER_XZOOM_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .reducer_yzoom = MT9M111_REDUCER_YZOOM_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .reducer_xsize = MT9M111_REDUCER_XSIZE_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .reducer_ysize = MT9M111_REDUCER_YSIZE_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .control = MT9M111_CTXT_CTRL_RESTART |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MT9M111_CTXT_CTRL_DEFECTCOR_B | MT9M111_CTXT_CTRL_RESIZE_B |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MT9M111_CTXT_CTRL_CTRL2_B | MT9M111_CTXT_CTRL_GAMMA_B |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MT9M111_CTXT_CTRL_READ_MODE_B | MT9M111_CTXT_CTRL_VBLANK_SEL_B |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MT9M111_CTXT_CTRL_HBLANK_SEL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* MT9M111 has only one fixed colorspace per pixelcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct mt9m111_datafmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) enum v4l2_colorspace colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct mt9m111_datafmt mt9m111_colour_fmts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {MEDIA_BUS_FMT_BGR565_2X8_LE, V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {MEDIA_BUS_FMT_BGR565_2X8_BE, V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) enum mt9m111_mode_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MT9M111_MODE_SXGA_8FPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MT9M111_MODE_SXGA_15FPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MT9M111_MODE_QSXGA_30FPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MT9M111_NUM_MODES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct mt9m111_mode_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int sensor_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int sensor_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int max_image_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int max_image_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct mt9m111 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct v4l2_ctrl *gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct mt9m111_context *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct v4l2_rect rect; /* cropping rectangle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct v4l2_clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned int width; /* output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned int height; /* sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct v4l2_fract frame_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) const struct mt9m111_mode_info *current_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct mutex power_lock; /* lock to protect power_count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int power_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) const struct mt9m111_datafmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int lastpage; /* PageMap cache value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) bool is_streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* user point of view - 0: falling 1: rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned int pclk_sample:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #ifdef CONFIG_MEDIA_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const struct mt9m111_mode_info mt9m111_mode_data[MT9M111_NUM_MODES] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [MT9M111_MODE_SXGA_8FPS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .sensor_w = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .sensor_h = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .max_image_w = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .max_image_h = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .max_fps = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .reg_val = MT9M111_RM_LOW_POWER_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [MT9M111_MODE_SXGA_15FPS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .sensor_w = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .sensor_h = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .max_image_w = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .max_image_h = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .max_fps = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .reg_val = MT9M111_RM_FULL_POWER_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [MT9M111_MODE_QSXGA_30FPS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .sensor_w = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .sensor_h = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .max_image_w = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .max_image_h = 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .max_fps = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .reg_val = MT9M111_RM_LOW_POWER_RD | MT9M111_RM_COL_SKIP_2X |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MT9M111_RM_ROW_SKIP_2X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Find a data format by a pixel code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct mt9m111_datafmt *mt9m111_find_datafmt(struct mt9m111 *mt9m111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) for (i = 0; i < ARRAY_SIZE(mt9m111_colour_fmts); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (mt9m111_colour_fmts[i].code == code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return mt9m111_colour_fmts + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return mt9m111->fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct mt9m111 *to_mt9m111(const struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return container_of(i2c_get_clientdata(client), struct mt9m111, subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int reg_page_map_set(struct i2c_client *client, const u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u16 page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct mt9m111 *mt9m111 = to_mt9m111(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) page = (reg >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (page == mt9m111->lastpage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (page > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = i2c_smbus_write_word_swapped(client, MT9M111_PAGE_MAP, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mt9m111->lastpage = page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int mt9m111_reg_read(struct i2c_client *client, const u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = reg_page_map_set(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ret = i2c_smbus_read_word_swapped(client, reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int mt9m111_reg_write(struct i2c_client *client, const u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) const u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = reg_page_map_set(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = i2c_smbus_write_word_swapped(client, reg & 0xff, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int mt9m111_reg_set(struct i2c_client *client, const u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) const u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = mt9m111_reg_read(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ret = mt9m111_reg_write(client, reg, ret | data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) const u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ret = mt9m111_reg_read(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ret = mt9m111_reg_write(client, reg, ret & ~data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) const u16 data, const u16 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = mt9m111_reg_read(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int mt9m111_set_context(struct mt9m111 *mt9m111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct mt9m111_context *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return reg_write(CONTEXT_CONTROL, ctx->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int mt9m111_setup_rect_ctx(struct mt9m111 *mt9m111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct mt9m111_context *ctx, struct v4l2_rect *rect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned int width, unsigned int height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int ret = mt9m111_reg_write(client, ctx->reducer_xzoom, rect->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = mt9m111_reg_write(client, ctx->reducer_yzoom, rect->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = mt9m111_reg_write(client, ctx->reducer_xsize, width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = mt9m111_reg_write(client, ctx->reducer_ysize, height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int mt9m111_setup_geometry(struct mt9m111 *mt9m111, struct v4l2_rect *rect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int width, int height, u32 code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = reg_write(COLUMN_START, rect->left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = reg_write(ROW_START, rect->top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = reg_write(WINDOW_WIDTH, rect->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = reg_write(WINDOW_HEIGHT, rect->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* IFP in use, down-scaling possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = mt9m111_setup_rect_ctx(mt9m111, &context_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) rect, width, height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = mt9m111_setup_rect_ctx(mt9m111, &context_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) rect, width, height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_dbg(&client->dev, "%s(%x): %ux%u@%u:%u -> %ux%u = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) __func__, code, rect->width, rect->height, rect->left, rect->top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) width, height, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int mt9m111_enable(struct mt9m111 *mt9m111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int mt9m111_reset(struct mt9m111 *mt9m111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = reg_set(RESET, MT9M111_RESET_RESET_SOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) | MT9M111_RESET_RESET_SOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int mt9m111_set_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct mt9m111 *mt9m111 = to_mt9m111(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct v4l2_rect rect = sel->r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int width, height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int ret, align = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) sel->target != V4L2_SEL_TGT_CROP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mt9m111->fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Bayer format - even size lengths */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) align = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Let the user play with the starting pixel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* FIXME: the datasheet doesn't specify minimum sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) v4l_bound_align_image(&rect.width, 2, MT9M111_MAX_WIDTH, align,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) &rect.height, 2, MT9M111_MAX_HEIGHT, align, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) rect.left = clamp(rect.left, MT9M111_MIN_DARK_COLS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MT9M111_MIN_DARK_COLS + MT9M111_MAX_WIDTH -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) (__s32)rect.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) rect.top = clamp(rect.top, MT9M111_MIN_DARK_ROWS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MT9M111_MIN_DARK_ROWS + MT9M111_MAX_HEIGHT -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) (__s32)rect.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) width = min(mt9m111->width, rect.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) height = min(mt9m111->height, rect.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = mt9m111_setup_geometry(mt9m111, &rect, width, height, mt9m111->fmt->code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mt9m111->rect = rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mt9m111->width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) mt9m111->height = height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int mt9m111_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct mt9m111 *mt9m111 = to_mt9m111(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) switch (sel->target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case V4L2_SEL_TGT_CROP_BOUNDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) sel->r.left = MT9M111_MIN_DARK_COLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) sel->r.top = MT9M111_MIN_DARK_ROWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) sel->r.width = MT9M111_MAX_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) sel->r.height = MT9M111_MAX_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) case V4L2_SEL_TGT_CROP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) sel->r = mt9m111->rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int mt9m111_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mf = v4l2_subdev_get_try_format(sd, cfg, format->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) format->format = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mf->width = mt9m111->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mf->height = mt9m111->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mf->code = mt9m111->fmt->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mf->colorspace = mt9m111->fmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) mf->quantization = V4L2_QUANTIZATION_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u16 data_outfmt2, mask_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) MT9M111_OUTFMT_RGB444x | MT9M111_OUTFMT_RGBx444 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) switch (code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case MEDIA_BUS_FMT_SBGGR8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) data_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MT9M111_OUTFMT_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) data_outfmt2 = MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case MEDIA_BUS_FMT_RGB565_2X8_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case MEDIA_BUS_FMT_RGB565_2X8_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case MEDIA_BUS_FMT_BGR565_2X8_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case MEDIA_BUS_FMT_BGR565_2X8_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) data_outfmt2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case MEDIA_BUS_FMT_VYUY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) case MEDIA_BUS_FMT_YUYV8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) case MEDIA_BUS_FMT_YVYU8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_err(&client->dev, "Pixel format not handled: %x\n", code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* receiver samples on falling edge, chip-hw default is rising */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (mt9m111->pclk_sample == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mask_outfmt2 |= MT9M111_OUTFMT_INV_PIX_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = mt9m111_reg_mask(client, context_a.output_fmt_ctrl2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) data_outfmt2, mask_outfmt2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ret = mt9m111_reg_mask(client, context_b.output_fmt_ctrl2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) data_outfmt2, mask_outfmt2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static int mt9m111_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) const struct mt9m111_datafmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct v4l2_rect *rect = &mt9m111->rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) bool bayer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (mt9m111->is_streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) fmt = mt9m111_find_datafmt(mt9m111, mf->code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) bayer = fmt->code == MEDIA_BUS_FMT_SBGGR8_1X8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * With Bayer format enforce even side lengths, but let the user play
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * with the starting pixel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (bayer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) rect->width = ALIGN(rect->width, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) rect->height = ALIGN(rect->height, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (fmt->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* IFP bypass mode, no scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) mf->width = rect->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) mf->height = rect->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* No upscaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (mf->width > rect->width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) mf->width = rect->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (mf->height > rect->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) mf->height = rect->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dev_dbg(&client->dev, "%s(): %ux%u, code=%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) mf->width, mf->height, fmt->code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mf->code = fmt->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) mf->colorspace = fmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) mf->quantization = V4L2_QUANTIZATION_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) cfg->try_fmt = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = mt9m111_setup_geometry(mt9m111, rect, mf->width, mf->height, mf->code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ret = mt9m111_set_pixfmt(mt9m111, mf->code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) mt9m111->width = mf->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) mt9m111->height = mf->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mt9m111->fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const struct mt9m111_mode_info *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) mt9m111_find_mode(struct mt9m111 *mt9m111, unsigned int req_fps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned int width, unsigned int height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) const struct mt9m111_mode_info *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct v4l2_rect *sensor_rect = &mt9m111->rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) unsigned int gap, gap_best = (unsigned int) -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int i, best_gap_idx = MT9M111_MODE_SXGA_15FPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) bool skip_30fps = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * The fps selection is based on the row, column skipping mechanism.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * So ensure that the sensor window is set to default else the fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * aren't calculated correctly within the sensor hw.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (sensor_rect->width != MT9M111_MAX_WIDTH ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) sensor_rect->height != MT9M111_MAX_HEIGHT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_info(mt9m111->subdev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) "Framerate selection is not supported for cropped "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) "images\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* 30fps only supported for images not exceeding 640x512 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (width > MT9M111_MAX_WIDTH / 2 || height > MT9M111_MAX_HEIGHT / 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_dbg(mt9m111->subdev.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) "Framerates > 15fps are supported only for images "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "not exceeding 640x512\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) skip_30fps = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* find best matched fps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) for (i = 0; i < MT9M111_NUM_MODES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) unsigned int fps = mt9m111_mode_data[i].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (fps == 30 && skip_30fps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) gap = abs(fps - req_fps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (gap < gap_best) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) best_gap_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) gap_best = gap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * Use context a/b default timing values instead of calculate blanking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * timing values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) mode = &mt9m111_mode_data[best_gap_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) mt9m111->ctx = (best_gap_idx == MT9M111_MODE_QSXGA_30FPS) ? &context_a :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) &context_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int mt9m111_g_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (reg->reg > 0x2ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) val = mt9m111_reg_read(client, reg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) reg->size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) reg->val = (u64)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (reg->val > 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static int mt9m111_s_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (reg->reg > 0x2ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (mt9m111_reg_write(client, reg->reg, reg->val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (flip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = mt9m111_reg_set(client, mt9m111->ctx->read_mode, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ret = mt9m111_reg_clear(client, mt9m111->ctx->read_mode, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int mt9m111_get_global_gain(struct mt9m111 *mt9m111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) data = reg_read(GLOBAL_GAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (data >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return (data & 0x2f) * (1 << ((data >> 10) & 1)) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) (1 << ((data >> 9) & 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static int mt9m111_set_global_gain(struct mt9m111 *mt9m111, int gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (gain > 63 * 2 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if ((gain >= 64 * 2) && (gain < 63 * 2 * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) val = (1 << 10) | (1 << 9) | (gain / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) else if ((gain >= 64) && (gain < 64 * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) val = (1 << 9) | (gain / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) val = gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return reg_write(GLOBAL_GAIN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (val == V4L2_EXPOSURE_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int mt9m111_set_autowhitebalance(struct mt9m111 *mt9m111, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static const char * const mt9m111_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) "Vertical monochrome gradient",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) "Flat color type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) "Flat color type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) "Flat color type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) "Flat color type 4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) "Flat color type 5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) "Color bar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int mt9m111_set_test_pattern(struct mt9m111 *mt9m111, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return mt9m111_reg_mask(client, MT9M111_TPG_CTRL, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) MT9M111_TPG_SEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static int mt9m111_set_colorfx(struct mt9m111 *mt9m111, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static const struct v4l2_control colorfx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) { V4L2_COLORFX_NONE, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) { V4L2_COLORFX_BW, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) { V4L2_COLORFX_SEPIA, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) { V4L2_COLORFX_NEGATIVE, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) { V4L2_COLORFX_SOLARIZATION, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) for (i = 0; i < ARRAY_SIZE(colorfx); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (colorfx[i].id == val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return mt9m111_reg_mask(client, MT9M111_EFFECTS_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) colorfx[i].value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) MT9M111_EFFECTS_MODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct mt9m111 *mt9m111 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct mt9m111, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return mt9m111_set_flip(mt9m111, ctrl->val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) MT9M111_RMB_MIRROR_ROWS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return mt9m111_set_flip(mt9m111, ctrl->val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) MT9M111_RMB_MIRROR_COLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case V4L2_CID_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return mt9m111_set_global_gain(mt9m111, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) case V4L2_CID_EXPOSURE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return mt9m111_set_autoexposure(mt9m111, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) case V4L2_CID_AUTO_WHITE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return mt9m111_set_autowhitebalance(mt9m111, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return mt9m111_set_test_pattern(mt9m111, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) case V4L2_CID_COLORFX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return mt9m111_set_colorfx(mt9m111, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static int mt9m111_suspend(struct mt9m111 *mt9m111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) v4l2_ctrl_s_ctrl(mt9m111->gain, mt9m111_get_global_gain(mt9m111));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ret = reg_set(RESET, MT9M111_RESET_RESET_SOC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) MT9M111_RESET_OUTPUT_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) MT9M111_RESET_ANALOG_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static void mt9m111_restore_state(struct mt9m111 *mt9m111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) mt9m111_set_context(mt9m111, mt9m111->ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) mt9m111_setup_geometry(mt9m111, &mt9m111->rect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) mt9m111->width, mt9m111->height, mt9m111->fmt->code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) v4l2_ctrl_handler_setup(&mt9m111->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) mt9m111_reg_mask(client, mt9m111->ctx->read_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) mt9m111->current_mode->reg_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) mt9m111->current_mode->reg_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int mt9m111_resume(struct mt9m111 *mt9m111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) int ret = mt9m111_enable(mt9m111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ret = mt9m111_reset(mt9m111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) mt9m111_restore_state(mt9m111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static int mt9m111_init(struct mt9m111 *mt9m111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ret = mt9m111_enable(mt9m111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ret = mt9m111_reset(mt9m111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ret = mt9m111_set_context(mt9m111, mt9m111->ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) dev_err(&client->dev, "mt9m111 init failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static int mt9m111_power_on(struct mt9m111 *mt9m111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ret = v4l2_clk_enable(mt9m111->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ret = regulator_enable(mt9m111->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ret = mt9m111_resume(mt9m111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) goto out_regulator_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) out_regulator_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) regulator_disable(mt9m111->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) v4l2_clk_disable(mt9m111->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dev_err(&client->dev, "Failed to resume the sensor: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static void mt9m111_power_off(struct mt9m111 *mt9m111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) mt9m111_suspend(mt9m111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) regulator_disable(mt9m111->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) v4l2_clk_disable(mt9m111->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static int mt9m111_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) mutex_lock(&mt9m111->power_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * If the power count is modified from 0 to != 0 or from != 0 to 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * update the power state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (mt9m111->power_count == !on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ret = mt9m111_power_on(mt9m111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) mt9m111_power_off(mt9m111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* Update the power count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) mt9m111->power_count += on ? 1 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) WARN_ON(mt9m111->power_count < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) mutex_unlock(&mt9m111->power_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static const struct v4l2_ctrl_ops mt9m111_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .s_ctrl = mt9m111_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static const struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .s_power = mt9m111_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .log_status = v4l2_ctrl_subdev_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .g_register = mt9m111_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .s_register = mt9m111_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static int mt9m111_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) fi->interval = mt9m111->frame_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static int mt9m111_s_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) const struct mt9m111_mode_info *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct v4l2_fract *fract = &fi->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) int fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (mt9m111->is_streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (fi->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (fract->numerator == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) fract->denominator = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) fract->numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) fps = DIV_ROUND_CLOSEST(fract->denominator, fract->numerator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* Find best fitting mode. Do not update the mode if no one was found. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) mode = mt9m111_find_mode(mt9m111, fps, mt9m111->width, mt9m111->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (mode->max_fps != fps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) fract->denominator = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) fract->numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) mt9m111->current_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) mt9m111->frame_interval = fi->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static int mt9m111_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (code->pad || code->index >= ARRAY_SIZE(mt9m111_colour_fmts))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) code->code = mt9m111_colour_fmts[code->index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static int mt9m111_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) mt9m111->is_streaming = !!enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static int mt9m111_init_cfg(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct v4l2_subdev_pad_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct v4l2_mbus_framefmt *format =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) format->width = MT9M111_MAX_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) format->height = MT9M111_MAX_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) format->code = mt9m111_colour_fmts[0].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) format->colorspace = mt9m111_colour_fmts[0].colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) format->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) format->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) format->quantization = V4L2_QUANTIZATION_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) format->xfer_func = V4L2_XFER_FUNC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static int mt9m111_get_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct v4l2_mbus_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) cfg->flags = V4L2_MBUS_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) V4L2_MBUS_DATA_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) cfg->flags |= mt9m111->pclk_sample ? V4L2_MBUS_PCLK_SAMPLE_RISING :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) V4L2_MBUS_PCLK_SAMPLE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) cfg->type = V4L2_MBUS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static const struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .s_stream = mt9m111_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .g_frame_interval = mt9m111_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .s_frame_interval = mt9m111_s_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static const struct v4l2_subdev_pad_ops mt9m111_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .init_cfg = mt9m111_init_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .enum_mbus_code = mt9m111_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .get_selection = mt9m111_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .set_selection = mt9m111_set_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .get_fmt = mt9m111_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .set_fmt = mt9m111_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .get_mbus_config = mt9m111_get_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static const struct v4l2_subdev_ops mt9m111_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .core = &mt9m111_subdev_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .video = &mt9m111_subdev_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .pad = &mt9m111_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * Interface active, can use i2c. If it fails, it can indeed mean, that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * this wasn't our capture interface, so, we wait for the right one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static int mt9m111_video_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) struct mt9m111 *mt9m111 = to_mt9m111(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) s32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ret = mt9m111_s_power(&mt9m111->subdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) data = reg_read(CHIP_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) switch (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) case 0x143a: /* MT9M111 or MT9M131 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) dev_info(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) "Detected a MT9M111/MT9M131 chip ID %x\n", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) case 0x148c: /* MT9M112 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) dev_info(&client->dev, "Detected a MT9M112 chip ID %x\n", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) "No MT9M111/MT9M112/MT9M131 chip detected register read %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ret = mt9m111_init(mt9m111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) ret = v4l2_ctrl_handler_setup(&mt9m111->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) mt9m111_s_power(&mt9m111->subdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static int mt9m111_probe_fw(struct i2c_client *client, struct mt9m111 *mt9m111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct v4l2_fwnode_endpoint bus_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .bus_type = V4L2_MBUS_PARALLEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct fwnode_handle *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) np = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ret = v4l2_fwnode_endpoint_parse(np, &bus_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) goto out_put_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) mt9m111->pclk_sample = !!(bus_cfg.bus.parallel.flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) V4L2_MBUS_PCLK_SAMPLE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) out_put_fw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) fwnode_handle_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static int mt9m111_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct mt9m111 *mt9m111;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) dev_warn(&adapter->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) mt9m111 = devm_kzalloc(&client->dev, sizeof(struct mt9m111), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (!mt9m111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (dev_fwnode(&client->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ret = mt9m111_probe_fw(client, mt9m111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) mt9m111->clk = v4l2_clk_get(&client->dev, "mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (IS_ERR(mt9m111->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return PTR_ERR(mt9m111->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) mt9m111->regulator = devm_regulator_get(&client->dev, "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (IS_ERR(mt9m111->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) dev_err(&client->dev, "regulator not found: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) PTR_ERR(mt9m111->regulator));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return PTR_ERR(mt9m111->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /* Default HIGHPOWER context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) mt9m111->ctx = &context_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) mt9m111->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) v4l2_ctrl_handler_init(&mt9m111->hdl, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) mt9m111->gain = v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) V4L2_CID_GAIN, 0, 63 * 2 * 2, 1, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) v4l2_ctrl_new_std_menu(&mt9m111->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) &mt9m111_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) V4L2_EXPOSURE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) v4l2_ctrl_new_std_menu_items(&mt9m111->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) &mt9m111_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) ARRAY_SIZE(mt9m111_test_pattern_menu) - 1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) mt9m111_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) v4l2_ctrl_new_std_menu(&mt9m111->hdl, &mt9m111_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) V4L2_CID_COLORFX, V4L2_COLORFX_SOLARIZATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) ~(BIT(V4L2_COLORFX_NONE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) BIT(V4L2_COLORFX_BW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) BIT(V4L2_COLORFX_SEPIA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) BIT(V4L2_COLORFX_NEGATIVE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) BIT(V4L2_COLORFX_SOLARIZATION)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) V4L2_COLORFX_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) mt9m111->subdev.ctrl_handler = &mt9m111->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (mt9m111->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) ret = mt9m111->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) goto out_clkput;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #ifdef CONFIG_MEDIA_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) mt9m111->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) mt9m111->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ret = media_entity_pads_init(&mt9m111->subdev.entity, 1, &mt9m111->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) goto out_hdlfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) mt9m111->current_mode = &mt9m111_mode_data[MT9M111_MODE_SXGA_15FPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) mt9m111->frame_interval.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) mt9m111->frame_interval.denominator = mt9m111->current_mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /* Second stage probe - when a capture adapter is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) mt9m111->rect.left = MT9M111_MIN_DARK_COLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) mt9m111->rect.top = MT9M111_MIN_DARK_ROWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) mt9m111->rect.width = MT9M111_MAX_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) mt9m111->rect.height = MT9M111_MAX_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) mt9m111->width = mt9m111->rect.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) mt9m111->height = mt9m111->rect.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) mt9m111->fmt = &mt9m111_colour_fmts[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) mt9m111->lastpage = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) mutex_init(&mt9m111->power_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ret = mt9m111_video_probe(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) goto out_entityclean;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) mt9m111->subdev.dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ret = v4l2_async_register_subdev(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) goto out_entityclean;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) out_entityclean:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) #ifdef CONFIG_MEDIA_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) media_entity_cleanup(&mt9m111->subdev.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) out_hdlfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) v4l2_ctrl_handler_free(&mt9m111->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) out_clkput:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) v4l2_clk_put(mt9m111->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) static int mt9m111_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) struct mt9m111 *mt9m111 = to_mt9m111(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) v4l2_async_unregister_subdev(&mt9m111->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) media_entity_cleanup(&mt9m111->subdev.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) v4l2_clk_put(mt9m111->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) v4l2_ctrl_handler_free(&mt9m111->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static const struct of_device_id mt9m111_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) { .compatible = "micron,mt9m111", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) MODULE_DEVICE_TABLE(of, mt9m111_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static const struct i2c_device_id mt9m111_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) { "mt9m111", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) MODULE_DEVICE_TABLE(i2c, mt9m111_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static struct i2c_driver mt9m111_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .name = "mt9m111",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .of_match_table = of_match_ptr(mt9m111_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .probe_new = mt9m111_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .remove = mt9m111_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .id_table = mt9m111_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) module_i2c_driver(mt9m111_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) MODULE_DESCRIPTION("Micron/Aptina MT9M111/MT9M112/MT9M131 Camera driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) MODULE_AUTHOR("Robert Jarzmik");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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