^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for MT9M001 CMOS Image Sensor from Micron
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * mt9m001 i2c address 0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* mt9m001 selected register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MT9M001_CHIP_VERSION 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MT9M001_ROW_START 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MT9M001_COLUMN_START 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MT9M001_WINDOW_HEIGHT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MT9M001_WINDOW_WIDTH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MT9M001_HORIZONTAL_BLANKING 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MT9M001_VERTICAL_BLANKING 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MT9M001_OUTPUT_CONTROL 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MT9M001_SHUTTER_WIDTH 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MT9M001_FRAME_RESTART 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MT9M001_SHUTTER_DELAY 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MT9M001_RESET 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MT9M001_READ_OPTIONS1 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MT9M001_READ_OPTIONS2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MT9M001_GLOBAL_GAIN 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MT9M001_CHIP_ENABLE 0xF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MT9M001_MAX_WIDTH 1280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MT9M001_MAX_HEIGHT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MT9M001_MIN_WIDTH 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MT9M001_MIN_HEIGHT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MT9M001_COLUMN_SKIP 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MT9M001_ROW_SKIP 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MT9M001_DEFAULT_HBLANK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MT9M001_DEFAULT_VBLANK 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* MT9M001 has only one fixed colorspace per pixelcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct mt9m001_datafmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum v4l2_colorspace colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Find a data format by a pixel code in an array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct mt9m001_datafmt *mt9m001_find_datafmt(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 code, const struct mt9m001_datafmt *fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) for (i = 0; i < n; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (fmt[i].code == code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return fmt + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const struct mt9m001_datafmt mt9m001_colour_fmts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Order important: first natively supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * second supported with a GPIO extender
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {MEDIA_BUS_FMT_SBGGR10_1X10, V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const struct mt9m001_datafmt mt9m001_monochrome_fmts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Order important - see above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {MEDIA_BUS_FMT_Y10_1X10, V4L2_COLORSPACE_JPEG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {MEDIA_BUS_FMT_Y8_1X8, V4L2_COLORSPACE_JPEG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct mt9m001 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* exposure/auto-exposure cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct v4l2_ctrl *autoexposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct v4l2_rect rect; /* Sensor window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct gpio_desc *standby_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const struct mt9m001_datafmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const struct mt9m001_datafmt *fmts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int num_fmts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int total_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned short y_skip_top; /* Lines to skip at the top */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct mt9m001 *to_mt9m001(const struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return container_of(i2c_get_clientdata(client), struct mt9m001, subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int reg_read(struct i2c_client *client, const u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return i2c_smbus_read_word_swapped(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int reg_write(struct i2c_client *client, const u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return i2c_smbus_write_word_swapped(client, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int reg_set(struct i2c_client *client, const u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = reg_read(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return reg_write(client, reg, ret | data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int reg_clear(struct i2c_client *client, const u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = reg_read(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return reg_write(client, reg, ret & ~data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct mt9m001_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int multi_reg_write(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const struct mt9m001_reg *regs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int ret = reg_write(client, regs[i].reg, regs[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int mt9m001_init(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct mt9m001_reg init_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Issue a soft reset. This returns all registers to their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * default values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { MT9M001_RESET, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { MT9M001_RESET, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Disable chip, synchronous option update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { MT9M001_OUTPUT_CONTROL, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_dbg(&client->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return multi_reg_write(client, init_regs, ARRAY_SIZE(init_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int mt9m001_apply_selection(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct mt9m001 *mt9m001 = to_mt9m001(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) const struct mt9m001_reg regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Blanking and start values - default... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { MT9M001_HORIZONTAL_BLANKING, MT9M001_DEFAULT_HBLANK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { MT9M001_VERTICAL_BLANKING, MT9M001_DEFAULT_VBLANK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * The caller provides a supported format, as verified per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * call to .set_fmt(FORMAT_TRY).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { MT9M001_COLUMN_START, mt9m001->rect.left },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { MT9M001_ROW_START, mt9m001->rect.top },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { MT9M001_WINDOW_WIDTH, mt9m001->rect.width - 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { MT9M001_WINDOW_HEIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mt9m001->rect.height + mt9m001->y_skip_top - 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return multi_reg_write(client, regs, ARRAY_SIZE(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int mt9m001_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct mt9m001 *mt9m001 = to_mt9m001(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mutex_lock(&mt9m001->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (mt9m001->streaming == enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto put_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = mt9m001_apply_selection(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) goto put_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = __v4l2_ctrl_handler_setup(&mt9m001->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) goto put_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Switch to master "normal" mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = reg_write(client, MT9M001_OUTPUT_CONTROL, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) goto put_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Switch to master stop sensor readout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) reg_write(client, MT9M001_OUTPUT_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mt9m001->streaming = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) mutex_unlock(&mt9m001->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) put_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mutex_unlock(&mt9m001->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int mt9m001_set_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct mt9m001 *mt9m001 = to_mt9m001(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct v4l2_rect rect = sel->r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) sel->target != V4L2_SEL_TGT_CROP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (mt9m001->fmts == mt9m001_colour_fmts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Bayer format - even number of rows for simplicity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * but let the user play with the top row.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) rect.height = ALIGN(rect.height, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Datasheet requirement: see register description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) rect.width = ALIGN(rect.width, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) rect.left = ALIGN(rect.left, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) rect.width = clamp_t(u32, rect.width, MT9M001_MIN_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MT9M001_MAX_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) rect.left = clamp_t(u32, rect.left, MT9M001_COLUMN_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MT9M001_COLUMN_SKIP + MT9M001_MAX_WIDTH - rect.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) rect.height = clamp_t(u32, rect.height, MT9M001_MIN_HEIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MT9M001_MAX_HEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) rect.top = clamp_t(u32, rect.top, MT9M001_ROW_SKIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MT9M001_ROW_SKIP + MT9M001_MAX_HEIGHT - rect.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mt9m001->total_h = rect.height + mt9m001->y_skip_top +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MT9M001_DEFAULT_VBLANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mt9m001->rect = rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int mt9m001_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct mt9m001 *mt9m001 = to_mt9m001(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) switch (sel->target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case V4L2_SEL_TGT_CROP_BOUNDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) sel->r.left = MT9M001_COLUMN_SKIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) sel->r.top = MT9M001_ROW_SKIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) sel->r.width = MT9M001_MAX_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) sel->r.height = MT9M001_MAX_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case V4L2_SEL_TGT_CROP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) sel->r = mt9m001->rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int mt9m001_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct mt9m001 *mt9m001 = to_mt9m001(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mf = v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) format->format = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mf->width = mt9m001->rect.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) mf->height = mt9m001->rect.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mf->code = mt9m001->fmt->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) mf->colorspace = mt9m001->fmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) mf->quantization = V4L2_QUANTIZATION_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int mt9m001_s_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) const struct mt9m001_datafmt *fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct v4l2_mbus_framefmt *mf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct mt9m001 *mt9m001 = to_mt9m001(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct v4l2_subdev_selection sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .which = V4L2_SUBDEV_FORMAT_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .target = V4L2_SEL_TGT_CROP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .r.left = mt9m001->rect.left,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .r.top = mt9m001->rect.top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .r.width = mf->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .r.height = mf->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* No support for scaling so far, just crop. TODO: use skipping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = mt9m001_set_selection(sd, NULL, &sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mf->width = mt9m001->rect.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mf->height = mt9m001->rect.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mt9m001->fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mf->colorspace = fmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int mt9m001_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct mt9m001 *mt9m001 = to_mt9m001(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) const struct mt9m001_datafmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) v4l_bound_align_image(&mf->width, MT9M001_MIN_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MT9M001_MAX_WIDTH, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) &mf->height, MT9M001_MIN_HEIGHT + mt9m001->y_skip_top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MT9M001_MAX_HEIGHT + mt9m001->y_skip_top, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (mt9m001->fmts == mt9m001_colour_fmts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) mf->height = ALIGN(mf->height - 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) fmt = mt9m001_find_datafmt(mf->code, mt9m001->fmts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) mt9m001->num_fmts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) fmt = mt9m001->fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mf->code = fmt->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mf->colorspace = fmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mf->quantization = V4L2_QUANTIZATION_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return mt9m001_s_fmt(sd, fmt, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) cfg->try_fmt = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int mt9m001_g_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (reg->reg > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) reg->size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) reg->val = reg_read(client, reg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (reg->val > 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int mt9m001_s_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (reg->reg > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (reg_write(client, reg->reg, reg->val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int mt9m001_power_on(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct mt9m001 *mt9m001 = to_mt9m001(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = clk_prepare_enable(mt9m001->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (mt9m001->standby_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) gpiod_set_value_cansleep(mt9m001->standby_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (mt9m001->reset_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) gpiod_set_value_cansleep(mt9m001->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) gpiod_set_value_cansleep(mt9m001->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int mt9m001_power_off(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct mt9m001 *mt9m001 = to_mt9m001(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) gpiod_set_value_cansleep(mt9m001->standby_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) clk_disable_unprepare(mt9m001->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int mt9m001_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct mt9m001 *mt9m001 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct mt9m001, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) s32 min, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case V4L2_CID_EXPOSURE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) min = mt9m001->exposure->minimum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) max = mt9m001->exposure->maximum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) mt9m001->exposure->val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) (524 + (mt9m001->total_h - 1) * (max - min)) / 1048 + min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int mt9m001_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct mt9m001 *mt9m001 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct mt9m001, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct v4l2_subdev *sd = &mt9m001->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct v4l2_ctrl *exp = mt9m001->exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = reg_set(client, MT9M001_READ_OPTIONS2, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = reg_clear(client, MT9M001_READ_OPTIONS2, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case V4L2_CID_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* See Datasheet Table 7, Gain settings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (ctrl->val <= ctrl->default_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Pack it into 0..1 step 0.125, register values 0..8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned long range = ctrl->default_value - ctrl->minimum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) data = ((ctrl->val - (s32)ctrl->minimum) * 8 + range / 2) / range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_dbg(&client->dev, "Setting gain %d\n", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret = reg_write(client, MT9M001_GLOBAL_GAIN, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* Pack it into 1.125..15 variable step, register values 9..67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* We assume qctrl->maximum - qctrl->default_value - 1 > 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned long range = ctrl->maximum - ctrl->default_value - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned long gain = ((ctrl->val - (s32)ctrl->default_value - 1) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 111 + range / 2) / range + 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (gain <= 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) data = gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) else if (gain <= 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) data = ((gain - 32) * 16 + 16) / 32 + 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) data = ((gain - 64) * 7 + 28) / 56 + 96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dev_dbg(&client->dev, "Setting gain from %d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) reg_read(client, MT9M001_GLOBAL_GAIN), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = reg_write(client, MT9M001_GLOBAL_GAIN, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case V4L2_CID_EXPOSURE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned long range = exp->maximum - exp->minimum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned long shutter = ((exp->val - (s32)exp->minimum) * 1048 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) range / 2) / range + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) "Setting shutter width from %d to %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) reg_read(client, MT9M001_SHUTTER_WIDTH), shutter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = reg_write(client, MT9M001_SHUTTER_WIDTH, shutter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mt9m001->total_h = mt9m001->rect.height +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mt9m001->y_skip_top + MT9M001_DEFAULT_VBLANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = reg_write(client, MT9M001_SHUTTER_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mt9m001->total_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * Interface active, can use i2c. If it fails, it can indeed mean, that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * this wasn't our capture interface, so, we wait for the right one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int mt9m001_video_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct mt9m001 *mt9m001 = to_mt9m001(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) s32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Enable the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) data = reg_write(client, MT9M001_CHIP_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dev_dbg(&client->dev, "write: %d\n", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Read out the chip version register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) data = reg_read(client, MT9M001_CHIP_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* must be 0x8411 or 0x8421 for colour sensor and 8431 for bw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) switch (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case 0x8411:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case 0x8421:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) mt9m001->fmts = mt9m001_colour_fmts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) mt9m001->num_fmts = ARRAY_SIZE(mt9m001_colour_fmts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) case 0x8431:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) mt9m001->fmts = mt9m001_monochrome_fmts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) mt9m001->num_fmts = ARRAY_SIZE(mt9m001_monochrome_fmts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) "No MT9M001 chip detected, register read %x\n", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mt9m001->fmt = &mt9m001->fmts[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_info(&client->dev, "Detected a MT9M001 chip ID %x (%s)\n", data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) data == 0x8431 ? "C12STM" : "C12ST");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ret = mt9m001_init(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev_err(&client->dev, "Failed to initialise the camera\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* mt9m001_init() has reset the chip, returning registers to defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ret = v4l2_ctrl_handler_setup(&mt9m001->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int mt9m001_g_skip_top_lines(struct v4l2_subdev *sd, u32 *lines)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct mt9m001 *mt9m001 = to_mt9m001(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) *lines = mt9m001->y_skip_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static const struct v4l2_ctrl_ops mt9m001_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .g_volatile_ctrl = mt9m001_g_volatile_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .s_ctrl = mt9m001_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static const struct v4l2_subdev_core_ops mt9m001_subdev_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .log_status = v4l2_ctrl_subdev_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .g_register = mt9m001_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .s_register = mt9m001_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static int mt9m001_init_cfg(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct v4l2_subdev_pad_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct mt9m001 *mt9m001 = to_mt9m001(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) try_fmt->width = MT9M001_MAX_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) try_fmt->height = MT9M001_MAX_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) try_fmt->code = mt9m001->fmts[0].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) try_fmt->colorspace = mt9m001->fmts[0].colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) try_fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) try_fmt->quantization = V4L2_QUANTIZATION_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) try_fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int mt9m001_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct mt9m001 *mt9m001 = to_mt9m001(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (code->pad || code->index >= mt9m001->num_fmts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) code->code = mt9m001->fmts[code->index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static int mt9m001_get_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct v4l2_mbus_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* MT9M001 has all capture_format parameters fixed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) cfg->flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) V4L2_MBUS_DATA_ACTIVE_HIGH | V4L2_MBUS_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) cfg->type = V4L2_MBUS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static const struct v4l2_subdev_video_ops mt9m001_subdev_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .s_stream = mt9m001_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const struct v4l2_subdev_sensor_ops mt9m001_subdev_sensor_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .g_skip_top_lines = mt9m001_g_skip_top_lines,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static const struct v4l2_subdev_pad_ops mt9m001_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .init_cfg = mt9m001_init_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .enum_mbus_code = mt9m001_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .get_selection = mt9m001_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .set_selection = mt9m001_set_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .get_fmt = mt9m001_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .set_fmt = mt9m001_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .get_mbus_config = mt9m001_get_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static const struct v4l2_subdev_ops mt9m001_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .core = &mt9m001_subdev_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .video = &mt9m001_subdev_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .sensor = &mt9m001_subdev_sensor_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .pad = &mt9m001_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static int mt9m001_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct mt9m001 *mt9m001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_warn(&adapter->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) mt9m001 = devm_kzalloc(&client->dev, sizeof(*mt9m001), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!mt9m001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) mt9m001->clk = devm_clk_get(&client->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (IS_ERR(mt9m001->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return PTR_ERR(mt9m001->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mt9m001->standby_gpio = devm_gpiod_get_optional(&client->dev, "standby",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (IS_ERR(mt9m001->standby_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return PTR_ERR(mt9m001->standby_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) mt9m001->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (IS_ERR(mt9m001->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return PTR_ERR(mt9m001->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) v4l2_i2c_subdev_init(&mt9m001->subdev, client, &mt9m001_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) mt9m001->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) v4l2_ctrl_handler_init(&mt9m001->hdl, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) v4l2_ctrl_new_std(&mt9m001->hdl, &mt9m001_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) v4l2_ctrl_new_std(&mt9m001->hdl, &mt9m001_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) V4L2_CID_GAIN, 0, 127, 1, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mt9m001->exposure = v4l2_ctrl_new_std(&mt9m001->hdl, &mt9m001_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) V4L2_CID_EXPOSURE, 1, 255, 1, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * Simulated autoexposure. If enabled, we calculate shutter width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * ourselves in the driver based on vertical blanking and frame width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) mt9m001->autoexposure = v4l2_ctrl_new_std_menu(&mt9m001->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) &mt9m001_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) V4L2_EXPOSURE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) mt9m001->subdev.ctrl_handler = &mt9m001->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (mt9m001->hdl.error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return mt9m001->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) v4l2_ctrl_auto_cluster(2, &mt9m001->autoexposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) V4L2_EXPOSURE_MANUAL, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) mutex_init(&mt9m001->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) mt9m001->hdl.lock = &mt9m001->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Second stage probe - when a capture adapter is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) mt9m001->y_skip_top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mt9m001->rect.left = MT9M001_COLUMN_SKIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) mt9m001->rect.top = MT9M001_ROW_SKIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) mt9m001->rect.width = MT9M001_MAX_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) mt9m001->rect.height = MT9M001_MAX_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = mt9m001_power_on(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) goto error_hdl_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) pm_runtime_set_active(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) pm_runtime_enable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = mt9m001_video_probe(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) goto error_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) mt9m001->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) mt9m001->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = media_entity_pads_init(&mt9m001->subdev.entity, 1, &mt9m001->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) goto error_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = v4l2_async_register_subdev(&mt9m001->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) goto error_entity_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pm_runtime_idle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) error_entity_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) media_entity_cleanup(&mt9m001->subdev.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) error_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) mt9m001_power_off(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) error_hdl_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) v4l2_ctrl_handler_free(&mt9m001->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) mutex_destroy(&mt9m001->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static int mt9m001_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct mt9m001 *mt9m001 = to_mt9m001(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) v4l2_async_unregister_subdev(&mt9m001->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) media_entity_cleanup(&mt9m001->subdev.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) mt9m001_power_off(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) v4l2_ctrl_handler_free(&mt9m001->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) mutex_destroy(&mt9m001->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static const struct i2c_device_id mt9m001_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) { "mt9m001", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) MODULE_DEVICE_TABLE(i2c, mt9m001_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static const struct dev_pm_ops mt9m001_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) SET_RUNTIME_PM_OPS(mt9m001_power_off, mt9m001_power_on, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static const struct of_device_id mt9m001_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) { .compatible = "onnn,mt9m001", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) MODULE_DEVICE_TABLE(of, mt9m001_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static struct i2c_driver mt9m001_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .name = "mt9m001",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .pm = &mt9m001_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .of_match_table = mt9m001_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .probe_new = mt9m001_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .remove = mt9m001_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .id_table = mt9m001_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) module_i2c_driver(mt9m001_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) MODULE_DESCRIPTION("Micron MT9M001 Camera driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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