Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OKI Semiconductor ML86V7667 video decoder driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Vladimir Barinov <source@cogentembedded.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2013 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2013 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <media/v4l2-ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DRV_NAME "ml86v7667"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* Subaddresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MRA_REG			0x00 /* Mode Register A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MRC_REG			0x02 /* Mode Register C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LUMC_REG		0x0C /* Luminance Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLC_REG			0x10 /* Contrast level control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SSEPL_REG		0x11 /* Sync separation level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CHRCA_REG		0x12 /* Chrominance Control A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ACCC_REG		0x14 /* ACC Loop filter & Chrominance control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ACCRC_REG		0x15 /* ACC Reference level control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define HUE_REG			0x16 /* Hue control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ADC2_REG		0x1F /* ADC Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PLLR1_REG		0x20 /* PLL Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define STATUS_REG		0x2C /* STATUS Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Mode Register A register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MRA_OUTPUT_MODE_MASK	(3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MRA_ITUR_BT601		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MRA_ITUR_BT656		(0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MRA_INPUT_MODE_MASK	(7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MRA_PAL_BT601		(4 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MRA_NTSC_BT601		(0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MRA_REGISTER_MODE	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* Mode Register C register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MRC_AUTOSELECT		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* Luminance Control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define LUMC_ONOFF_SHIFT	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define LUMC_ONOFF_MASK		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* Contrast level control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CLC_CONTRAST_ONOFF	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CLC_CONTRAST_MASK	0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* Sync separation level register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SSEPL_LUMINANCE_ONOFF	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SSEPL_LUMINANCE_MASK	0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* Chrominance Control A register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CHRCA_MODE_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CHRCA_MODE_MASK		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* ACC Loop filter & Chrominance control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define ACCC_CHROMA_CR_SHIFT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define ACCC_CHROMA_CR_MASK	(7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define ACCC_CHROMA_CB_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define ACCC_CHROMA_CB_MASK	(7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* ACC Reference level control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define ACCRC_CHROMA_MASK	0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define ACCRC_CHROMA_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* ADC Register 2 register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define ADC2_CLAMP_VOLTAGE_MASK	(7 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define ADC2_CLAMP_VOLTAGE(n)	((n & 7) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* PLL Register 1 register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PLLR1_FIXED_CLOCK	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* STATUS Register register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define STATUS_HLOCK_DETECT	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define STATUS_NTSCPAL		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) struct ml86v7667_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct v4l2_subdev		sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct v4l2_ctrl_handler	hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	v4l2_std_id			std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static inline struct ml86v7667_priv *to_ml86v7667(struct v4l2_subdev *subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	return container_of(subdev, struct ml86v7667_priv, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return &container_of(ctrl->handler, struct ml86v7667_priv, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int ml86v7667_mask_set(struct i2c_client *client, const u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			      const u8 mask, const u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	int val = i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	val = (val & ~mask) | (data & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return i2c_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int ml86v7667_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		ret = ml86v7667_mask_set(client, SSEPL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 					 SSEPL_LUMINANCE_MASK, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		ret = ml86v7667_mask_set(client, CLC_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 					 CLC_CONTRAST_MASK, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	case V4L2_CID_CHROMA_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		ret = ml86v7667_mask_set(client, ACCRC_REG, ACCRC_CHROMA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 					 ctrl->val << ACCRC_CHROMA_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		ret = ml86v7667_mask_set(client, HUE_REG, ~0, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	case V4L2_CID_RED_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		ret = ml86v7667_mask_set(client, ACCC_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 					 ACCC_CHROMA_CR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 					 ctrl->val << ACCC_CHROMA_CR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	case V4L2_CID_BLUE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		ret = ml86v7667_mask_set(client, ACCC_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 					 ACCC_CHROMA_CB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 					 ctrl->val << ACCC_CHROMA_CB_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	case V4L2_CID_SHARPNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		ret = ml86v7667_mask_set(client, LUMC_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 					 LUMC_ONOFF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 					 ctrl->val << LUMC_ONOFF_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	case V4L2_CID_COLOR_KILLER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		ret = ml86v7667_mask_set(client, CHRCA_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 					 CHRCA_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 					 ctrl->val << CHRCA_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int ml86v7667_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	status = i2c_smbus_read_byte_data(client, STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (status & STATUS_HLOCK_DETECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		*std &= status & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		*std = V4L2_STD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int ml86v7667_g_input_status(struct v4l2_subdev *sd, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	int status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	status_reg = i2c_smbus_read_byte_data(client, STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (status_reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	*status = status_reg & STATUS_HLOCK_DETECT ? 0 : V4L2_IN_ST_NO_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int ml86v7667_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (code->pad || code->index > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	code->code = MEDIA_BUS_FMT_YUYV8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int ml86v7667_fill_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct ml86v7667_priv *priv = to_ml86v7667(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct v4l2_mbus_framefmt *fmt = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	fmt->code = MEDIA_BUS_FMT_YUYV8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/* The top field is always transferred first by the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	fmt->field = V4L2_FIELD_INTERLACED_TB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	fmt->width = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	fmt->height = priv->std & V4L2_STD_525_60 ? 480 : 576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int ml86v7667_get_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				     unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				     struct v4l2_mbus_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		     V4L2_MBUS_DATA_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	cfg->type = V4L2_MBUS_BT656;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int ml86v7667_g_std(struct v4l2_subdev *sd, v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct ml86v7667_priv *priv = to_ml86v7667(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	*std = priv->std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int ml86v7667_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct ml86v7667_priv *priv = to_ml86v7667(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/* PAL/NTSC ITU-R BT.601 input mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	mode = std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ret = ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	priv->std = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int ml86v7667_g_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	ret = i2c_smbus_read_byte_data(client, (u8)reg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	reg->val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	reg->size = sizeof(u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int ml86v7667_s_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return i2c_smbus_write_byte_data(client, (u8)reg->reg, (u8)reg->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const struct v4l2_ctrl_ops ml86v7667_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.s_ctrl = ml86v7667_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct v4l2_subdev_video_ops ml86v7667_subdev_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.g_std = ml86v7667_g_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.s_std = ml86v7667_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.querystd = ml86v7667_querystd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.g_input_status = ml86v7667_g_input_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct v4l2_subdev_pad_ops ml86v7667_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.enum_mbus_code = ml86v7667_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.get_fmt = ml86v7667_fill_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.set_fmt = ml86v7667_fill_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.get_mbus_config = ml86v7667_get_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct v4l2_subdev_core_ops ml86v7667_subdev_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.g_register = ml86v7667_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.s_register = ml86v7667_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct v4l2_subdev_ops ml86v7667_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.core = &ml86v7667_subdev_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.video = &ml86v7667_subdev_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.pad = &ml86v7667_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int ml86v7667_init(struct ml86v7667_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	/* BT.656-4 output mode, register mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	ret = ml86v7667_mask_set(client, MRA_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 				 MRA_OUTPUT_MODE_MASK | MRA_REGISTER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 				 MRA_ITUR_BT656 | MRA_REGISTER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	/* PLL circuit fixed clock, 32MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	ret |= ml86v7667_mask_set(client, PLLR1_REG, PLLR1_FIXED_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 				  PLLR1_FIXED_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	/* ADC2 clamping voltage maximum  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	ret |= ml86v7667_mask_set(client, ADC2_REG, ADC2_CLAMP_VOLTAGE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 				  ADC2_CLAMP_VOLTAGE(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	/* enable luminance function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ret |= ml86v7667_mask_set(client, SSEPL_REG, SSEPL_LUMINANCE_ONOFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 				  SSEPL_LUMINANCE_ONOFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	/* enable contrast function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	ret |= ml86v7667_mask_set(client, CLC_REG, CLC_CONTRAST_ONOFF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	 * PAL/NTSC autodetection is enabled after reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	 * set the autodetected std in manual std mode and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	 * disable autodetection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	val = i2c_smbus_read_byte_data(client, STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	priv->std = val & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	ret |= ml86v7667_mask_set(client, MRC_REG, MRC_AUTOSELECT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	val = priv->std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	ret |= ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int ml86v7667_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			   const struct i2c_device_id *did)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	struct ml86v7667_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	v4l2_i2c_subdev_init(&priv->sd, client, &ml86v7667_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	v4l2_ctrl_handler_init(&priv->hdl, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			  V4L2_CID_BRIGHTNESS, -64, 63, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 			  V4L2_CID_CONTRAST, -8, 7, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			  V4L2_CID_CHROMA_GAIN, -32, 31, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			  V4L2_CID_HUE, -128, 127, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			  V4L2_CID_RED_BALANCE, -4, 3, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			  V4L2_CID_BLUE_BALANCE, -4, 3, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 			  V4L2_CID_SHARPNESS, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 			  V4L2_CID_COLOR_KILLER, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	priv->sd.ctrl_handler = &priv->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	ret = priv->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	v4l2_ctrl_handler_setup(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	ret = ml86v7667_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	v4l_info(client, "chip found @ 0x%02x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		 client->addr, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	v4l2_ctrl_handler_free(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	v4l2_device_unregister_subdev(&priv->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	v4l_err(client, "failed to probe @ 0x%02x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		client->addr, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int ml86v7667_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	struct ml86v7667_priv *priv = to_ml86v7667(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	v4l2_ctrl_handler_free(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	v4l2_device_unregister_subdev(&priv->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const struct i2c_device_id ml86v7667_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	{DRV_NAME, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MODULE_DEVICE_TABLE(i2c, ml86v7667_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct i2c_driver ml86v7667_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		.name	= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.probe		= ml86v7667_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.remove		= ml86v7667_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	.id_table	= ml86v7667_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) module_i2c_driver(ml86v7667_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MODULE_DESCRIPTION("OKI Semiconductor ML86V7667 video decoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MODULE_AUTHOR("Vladimir Barinov");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_LICENSE("GPL");