^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * max96722 GMSL2/GMSL1 to CSI-2 Deserializer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAX96722_LINK_FREQ_400MHZ 400000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAX96722_PIXEL_RATE (MAX96722_LINK_FREQ_400MHZ * 2LL * 4LL / 24LL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MAX96722_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CHIP_ID 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MAX96722_REG_CHIP_ID 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MAX96722_REG_CTRL_MODE 0x08a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MAX96722_MODE_SW_STANDBY 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MAX96722_MODE_STREAMING 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MAX96722_REMOTE_CTRL 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MAX96722_REMOTE_DISABLE 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MAX96722_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MAX96722_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MAX96722_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MAX96722_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MAX96722_NAME "max96722"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MAX96722_MEDIA_BUS_FMT MEDIA_BUS_FMT_RGB888_1X24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const char * const max96722_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MAX96722_NUM_SUPPLIES ARRAY_SIZE(max96722_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u16 i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct max96722_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 link_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct max96722 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct regulator_bulk_data supplies[MAX96722_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) bool hot_plug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 is_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const struct max96722_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define to_max96722(sd) container_of(sd, struct max96722, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct regval max96722_mipi_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {0x6b, 0x0006, 0xF0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) // Disable MIPI output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {0x6b, 0x040B, 0x00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) // RGB888 software override for all pipes since connected GMSL1 is under parallel mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {0x6b, 0x040B, 0xC0, 0x00}, //0b11000-000, bpp0=0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {0x6b, 0x040E, 0xA4, 0x00}, //0b10-100100, DT0=0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {0x6b, 0x040F, 0x04, 0x00}, //0b0000-0100, DT1=0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {0x6b, 0x0411, 0x18, 0x00}, //0b000-11000, bpp1=0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) //Video pipe sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {0x6b, 0x00F0, 0x40, 0x00}, //LINKA-pipex=pipe0, LINKB-pipex=pipe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) // Send RGB888, FS, and FE from Pipe 0 to Controller 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0x6b, 0x090B, 0x07, 0x00}, // Enable 3 Mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0x6b, 0x092D, 0x15, 0x00}, //Map Data to Port A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) // For the following MSB 2 bits = VC, LSB 6 bits =DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0x6b, 0x090D, 0x24, 0x00}, // SRC DT = RGB888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x6b, 0x090E, 0x24, 0x00}, // DEST DT = RGB888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x6b, 0x090F, 0x00, 0x00}, // SRC DT = Frame Start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x6b, 0x0910, 0x00, 0x00}, // DEST DT = Frame Start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x6b, 0x0911, 0x01, 0x00}, // SRC DT = Frame End
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0x6b, 0x0912, 0x01, 0x00}, // DEST DT = Frame End
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) //Send RGB888, FS, and FE from Pipe 1 to Controller 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x6b, 0x094B, 0x07, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x6b, 0x096D, 0xAA, 0x00}, // map to MIPI Controller 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) // For the following MSB 2 bits = VC, LSB 6 bits =DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x6b, 0x094D, 0x24, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x6b, 0x094E, 0x24, 0x00}, // map to VC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x6b, 0x094F, 0x00, 0x00}, // frame start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x6b, 0x0950, 0x00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x6b, 0x0951, 0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x6b, 0x0952, 0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) // MIPI PHY Setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) // Set Des in 2x4 mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x6b, 0x08A0, 0x04, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) // Set Lane Mapping for 4-lane port A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x6b, 0x08A3, 0xE4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x6b, 0x08A4, 0xE4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) // Set 4 lane D-PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x6b, 0x090A, 0xC0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x6b, 0x094A, 0xC0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x6b, 0x098A, 0xC0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x6b, 0x09CA, 0xC0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) // Turn on MIPI PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x6b, 0x08A2, 0xF0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) // Hold DPLL in reset (config_soft_rst_n = 0) before changing the rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x6b, 0x1C00, 0xF4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x6b, 0x1D00, 0xF4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x6b, 0x1E00, 0xF4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x6b, 0x1F00, 0xF4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) // Set Data rate to be 800Mbps/lane for port A and enable software override
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x6b, 0x0415, 0xE8, 0x00}, //override pipe0/1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x6b, 0x0418, 0x28, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x6b, 0x041B, 0x28, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x6b, 0x041E, 0x28, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) // Release reset to DPLL (config_soft_rst_n = 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x6b, 0x1C00, 0xF5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x6b, 0x1D00, 0xF5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x6b, 0x1E00, 0xF5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x6b, 0x1F00, 0xF5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x6b, 0x0003, 0xFF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x6b, 0x0006, 0xF3, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) // {0x6b, 0x08A0, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x6b, REG_NULL, 0x00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct max96722_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .reg_list = max96722_mipi_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const s64 link_freq_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MAX96722_LINK_FREQ_400MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int max96722_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (i2c_master_send(client, buf, len + 2) != len + 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(&client->dev, "%s: writing register 0x%x from 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __func__, reg, client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int max96722_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) client->addr = regs[i].i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = max96722_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MAX96722_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) msleep(regs[i].delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int max96722_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ret != ARRAY_SIZE(msgs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_err(&client->dev, "%s: reading register 0x%x from 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __func__, reg, client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int max96722_get_reso_dist(const struct max96722_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct max96722_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) max96722_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dist = max96722_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int max96722_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct max96722 *max96722 = to_max96722(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) const struct max96722_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mutex_lock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mode = max96722_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) fmt->format.code = MAX96722_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mutex_unlock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (max96722->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mutex_unlock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mutex_unlock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int max96722_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct max96722 *max96722 = to_max96722(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) const struct max96722_mode *mode = max96722->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mutex_lock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mutex_unlock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) fmt->format.code = MAX96722_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) mutex_unlock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int max96722_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) code->code = MAX96722_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int max96722_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (fse->code != MAX96722_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int max96722_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct max96722 *max96722 = to_max96722(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) const struct max96722_mode *mode = max96722->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) mutex_lock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) mutex_unlock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void max96722_get_module_inf(struct max96722 *max96722,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) strscpy(inf->base.sensor, MAX96722_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) strscpy(inf->base.module, max96722->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) strscpy(inf->base.lens, max96722->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static void max96722_get_vicap_rst_inf(struct max96722 *max96722,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct rkmodule_vicap_reset_info *rst_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct i2c_client *client = max96722->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) rst_info->is_reset = max96722->hot_plug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) max96722->hot_plug = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) rst_info->src = RKCIF_RESET_SRC_ERR_HOTPLUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_info(&client->dev, "%s: rst_info->is_reset:%d.\n", __func__, rst_info->is_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static void max96722_set_vicap_rst_inf(struct max96722 *max96722,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct rkmodule_vicap_reset_info rst_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) max96722->is_reset = rst_info.is_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static long max96722_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct max96722 *max96722 = to_max96722(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) max96722_get_module_inf(max96722, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = max96722_write_reg(max96722->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MAX96722_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MAX96722_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MAX96722_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = max96722_write_reg(max96722->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MAX96722_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MAX96722_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MAX96722_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case RKMODULE_GET_VICAP_RST_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) max96722_get_vicap_rst_inf(max96722,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) (struct rkmodule_vicap_reset_info *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case RKMODULE_SET_VICAP_RST_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) max96722_set_vicap_rst_inf(max96722,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) *(struct rkmodule_vicap_reset_info *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case RKMODULE_GET_CSI_DSI_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) *(int *)arg = RKMODULE_CSI_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static long max96722_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct rkmodule_vicap_reset_info *vicap_rst_inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int *seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = max96722_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = max96722_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) case RKMODULE_GET_VICAP_RST_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) vicap_rst_inf = kzalloc(sizeof(*vicap_rst_inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!vicap_rst_inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = max96722_ioctl(sd, cmd, vicap_rst_inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = copy_to_user(up, vicap_rst_inf, sizeof(*vicap_rst_inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) kfree(vicap_rst_inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case RKMODULE_SET_VICAP_RST_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) vicap_rst_inf = kzalloc(sizeof(*vicap_rst_inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (!vicap_rst_inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = copy_from_user(vicap_rst_inf, up, sizeof(*vicap_rst_inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = max96722_ioctl(sd, cmd, vicap_rst_inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) kfree(vicap_rst_inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case RKMODULE_GET_START_STREAM_SEQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) seq = kzalloc(sizeof(*seq), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (!seq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = max96722_ioctl(sd, cmd, seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = copy_to_user(up, seq, sizeof(*seq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) kfree(seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = max96722_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case RKMODULE_GET_CSI_DSI_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) seq = kzalloc(sizeof(*seq), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (!seq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ret = max96722_ioctl(sd, cmd, seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = copy_to_user(up, seq, sizeof(*seq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) kfree(seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static int __max96722_start_stream(struct max96722 *max96722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ret = max96722_write_array(max96722->client, max96722->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mutex_unlock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = v4l2_ctrl_handler_setup(&max96722->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) mutex_lock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return max96722_write_reg(max96722->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) MAX96722_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) MAX96722_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) MAX96722_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int __max96722_stop_stream(struct max96722 *max96722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return max96722_write_reg(max96722->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MAX96722_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) MAX96722_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MAX96722_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int max96722_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct max96722 *max96722 = to_max96722(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct i2c_client *client = max96722->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) max96722->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) max96722->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) DIV_ROUND_CLOSEST(max96722->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) max96722->cur_mode->max_fps.numerator));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mutex_lock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (on == max96722->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret = __max96722_start_stream(max96722);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) __max96722_stop_stream(max96722);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) max96722->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) mutex_unlock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static int max96722_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct max96722 *max96722 = to_max96722(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct i2c_client *client = max96722->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) mutex_lock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (max96722->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) max96722->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) max96722->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) mutex_unlock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static inline u32 max96722_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return DIV_ROUND_UP(cycles, MAX96722_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static int __max96722_power_on(struct max96722 *max96722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct device *dev = &max96722->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (!IS_ERR(max96722->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) gpiod_set_value_cansleep(max96722->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (!IS_ERR_OR_NULL(max96722->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ret = pinctrl_select_state(max96722->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) max96722->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!IS_ERR(max96722->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) gpiod_set_value_cansleep(max96722->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ret = regulator_bulk_enable(MAX96722_NUM_SUPPLIES, max96722->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (!IS_ERR(max96722->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) gpiod_set_value_cansleep(max96722->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (!IS_ERR(max96722->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) gpiod_set_value_cansleep(max96722->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) delay_us = max96722_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) clk_disable_unprepare(max96722->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static void __max96722_power_off(struct max96722 *max96722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct device *dev = &max96722->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (!IS_ERR(max96722->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) gpiod_set_value_cansleep(max96722->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) clk_disable_unprepare(max96722->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (!IS_ERR(max96722->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) gpiod_set_value_cansleep(max96722->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (!IS_ERR_OR_NULL(max96722->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ret = pinctrl_select_state(max96722->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) max96722->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (!IS_ERR(max96722->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) gpiod_set_value_cansleep(max96722->power_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) regulator_bulk_disable(MAX96722_NUM_SUPPLIES, max96722->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int max96722_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct max96722 *max96722 = to_max96722(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return __max96722_power_on(max96722);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static int max96722_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct max96722 *max96722 = to_max96722(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) __max96722_power_off(max96722);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static int max96722_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct max96722 *max96722 = to_max96722(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) const struct max96722_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) mutex_lock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) try_fmt->code = MAX96722_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) mutex_unlock(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static int max96722_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (fie->code != MAX96722_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static int max96722_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) config->flags = V4L2_MBUS_CSI2_4_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int max96722_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct max96722 *max96722 = to_max96722(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) sel->r.width = max96722->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) sel->r.top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) sel->r.height = max96722->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static const struct dev_pm_ops max96722_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) SET_RUNTIME_PM_OPS(max96722_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) max96722_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static const struct v4l2_subdev_internal_ops max96722_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .open = max96722_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static const struct v4l2_subdev_core_ops max96722_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .s_power = max96722_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .ioctl = max96722_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .compat_ioctl32 = max96722_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static const struct v4l2_subdev_video_ops max96722_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .s_stream = max96722_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .g_frame_interval = max96722_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static const struct v4l2_subdev_pad_ops max96722_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .enum_mbus_code = max96722_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .enum_frame_size = max96722_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .enum_frame_interval = max96722_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .get_fmt = max96722_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .set_fmt = max96722_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .get_selection = max96722_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .get_mbus_config = max96722_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const struct v4l2_subdev_ops max96722_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .core = &max96722_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .video = &max96722_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .pad = &max96722_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static int max96722_initialize_controls(struct max96722 *max96722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) const struct max96722_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) handler = &max96722->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) mode = max96722->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret = v4l2_ctrl_handler_init(handler, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) handler->lock = &max96722->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) max96722->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) 1, 0, link_freq_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) max96722->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) 0, MAX96722_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) 1, MAX96722_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) __v4l2_ctrl_s_ctrl(max96722->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) mode->link_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_err(&max96722->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) max96722->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static int max96722_check_sensor_id(struct max96722 *max96722,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct device *dev = &max96722->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ret = max96722_read_reg(client, MAX96722_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) MAX96722_REG_VALUE_08BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) dev_err(dev, "Unexpected sensor id(%02x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) dev_info(dev, "Detected %02x sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static int max96722_configure_regulators(struct max96722 *max96722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) for (i = 0; i < MAX96722_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) max96722->supplies[i].supply = max96722_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return devm_regulator_bulk_get(&max96722->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) MAX96722_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) max96722->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static int max96722_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct max96722 *max96722;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) max96722 = devm_kzalloc(dev, sizeof(*max96722), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (!max96722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) &max96722->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) &max96722->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) &max96722->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) &max96722->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) max96722->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) max96722->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) max96722->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (IS_ERR(max96722->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) max96722->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (IS_ERR(max96722->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) max96722->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (IS_ERR(max96722->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret = max96722_configure_regulators(max96722);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) max96722->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (!IS_ERR(max96722->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) max96722->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) pinctrl_lookup_state(max96722->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (IS_ERR(max96722->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) max96722->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) pinctrl_lookup_state(max96722->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (IS_ERR(max96722->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) mutex_init(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) sd = &max96722->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) v4l2_i2c_subdev_init(sd, client, &max96722_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ret = max96722_initialize_controls(max96722);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ret = __max96722_power_on(max96722);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ret = max96722_write_reg(max96722->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) MAX96722_REMOTE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) MAX96722_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) MAX96722_REMOTE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dev_err(dev, "disable i2c remote control error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ret = max96722_check_sensor_id(max96722, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) sd->internal_ops = &max96722_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) max96722->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ret = media_entity_pads_init(&sd->entity, 1, &max96722->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (strcmp(max96722->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) max96722->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) MAX96722_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) __max96722_power_off(max96722);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) v4l2_ctrl_handler_free(&max96722->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) mutex_destroy(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static int max96722_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct max96722 *max96722 = to_max96722(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) v4l2_ctrl_handler_free(&max96722->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) mutex_destroy(&max96722->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) __max96722_power_off(max96722);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static const struct of_device_id max96722_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) { .compatible = "maxim,max96722" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) MODULE_DEVICE_TABLE(of, max96722_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static const struct i2c_device_id max96722_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) { "maxim,max96722", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static struct i2c_driver max96722_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .name = MAX96722_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .pm = &max96722_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .of_match_table = of_match_ptr(max96722_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .probe = &max96722_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .remove = &max96722_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .id_table = max96722_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return i2c_add_driver(&max96722_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) i2c_del_driver(&max96722_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) MODULE_DESCRIPTION("Maxim max96722 deserializer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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