^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Maxim MAX9286 GMSL Deserializer Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017-2019 Jacopo Mondi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2017-2019 Kieran Bingham
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2017-2019 Laurent Pinchart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2017-2019 Niklas Söderlund
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2016 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2015 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c-mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Register 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAX9286_MSTLINKSEL_AUTO (7 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MAX9286_MSTLINKSEL(n) ((n) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MAX9286_EN_VS_GEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAX9286_LINKEN(n) (1 << (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Register 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAX9286_FSYNCMODE_ECU (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MAX9286_FSYNCMODE_EXT (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MAX9286_FSYNCMODE_INT_OUT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MAX9286_FSYNCMODE_INT_HIZ (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MAX9286_GPIEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MAX9286_ENLMO_RSTFSYNC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MAX9286_FSYNCMETH_AUTO (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MAX9286_FSYNCMETH_SEMI_AUTO (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MAX9286_FSYNCMETH_MANUAL (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MAX9286_REG_FSYNC_PERIOD_L 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MAX9286_REG_FSYNC_PERIOD_M 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MAX9286_REG_FSYNC_PERIOD_H 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Register 0x0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MAX9286_FWDCCEN(n) (1 << ((n) + 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MAX9286_REVCCEN(n) (1 << (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Register 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MAX9286_HVEN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MAX9286_EDC_6BIT_HAMMING (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MAX9286_EDC_6BIT_CRC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MAX9286_EDC_1BIT_PARITY (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MAX9286_DESEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MAX9286_INVVS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MAX9286_INVHS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MAX9286_HVSRC_D0 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MAX9286_HVSRC_D14 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MAX9286_HVSRC_D18 (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Register 0x0f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MAX9286_0X0F_RESERVED BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Register 0x12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MAX9286_CSILANECNT(n) (((n) - 1) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MAX9286_CSIDBL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MAX9286_DBL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MAX9286_DATATYPE_USER_8BIT (11 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MAX9286_DATATYPE_USER_YUV_12BIT (10 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MAX9286_DATATYPE_USER_24BIT (9 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MAX9286_DATATYPE_RAW14 (8 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MAX9286_DATATYPE_RAW11 (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MAX9286_DATATYPE_RAW10 (6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MAX9286_DATATYPE_RAW8 (5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MAX9286_DATATYPE_YUV422_10BIT (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MAX9286_DATATYPE_YUV422_8BIT (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MAX9286_DATATYPE_RGB555 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MAX9286_DATATYPE_RGB565 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MAX9286_DATATYPE_RGB888 (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Register 0x15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MAX9286_VC(n) ((n) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MAX9286_VCTYPE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MAX9286_CSIOUTEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MAX9286_0X15_RESV (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Register 0x1b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MAX9286_SWITCHIN(n) (1 << ((n) + 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MAX9286_ENEQ(n) (1 << (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Register 0x27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MAX9286_LOCKED BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Register 0x31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MAX9286_FSYNC_LOCKED BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Register 0x34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MAX9286_I2CLOCACK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MAX9286_I2CSLVSH_1046NS_469NS (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MAX9286_I2CSLVSH_938NS_352NS (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MAX9286_I2CSLVSH_469NS_234NS (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MAX9286_I2CSLVSH_352NS_117NS (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MAX9286_I2CMSTBT_837KBPS (7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MAX9286_I2CMSTBT_533KBPS (6 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MAX9286_I2CMSTBT_339KBPS (5 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MAX9286_I2CMSTBT_173KBPS (4 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MAX9286_I2CMSTBT_105KBPS (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MAX9286_I2CMSTBT_84KBPS (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MAX9286_I2CMSTBT_28KBPS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MAX9286_I2CMSTBT_8KBPS (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MAX9286_I2CSLVTO_NONE (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MAX9286_I2CSLVTO_1024US (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MAX9286_I2CSLVTO_256US (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MAX9286_I2CSLVTO_64US (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Register 0x3b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MAX9286_REV_TRF(n) ((n) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MAX9286_REV_AMP(n) ((((n) - 30) / 10) << 1) /* in mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MAX9286_REV_AMP_X BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Register 0x3f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MAX9286_EN_REV_CFG BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MAX9286_REV_FLEN(n) ((n) - 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Register 0x49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MAX9286_VIDEO_DETECT_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Register 0x69 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MAX9286_LFLTBMONMASKED BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MAX9286_LOCKMONMASKED BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MAX9286_AUTOCOMBACKEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MAX9286_AUTOMASKEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MAX9286_MASKLINK(n) ((n) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * The sink and source pads are created to match the OF graph port numbers so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * that their indexes can be used interchangeably.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MAX9286_NUM_GMSL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MAX9286_N_SINKS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MAX9286_N_PADS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MAX9286_SRC_PAD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct max9286_source {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct max9286_asd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct v4l2_async_subdev base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct max9286_source *source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static inline struct max9286_asd *to_max9286_asd(struct v4l2_async_subdev *asd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return container_of(asd, struct max9286_asd, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct max9286_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct gpio_desc *gpiod_pwdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct media_pad pads[MAX9286_N_PADS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 gpio_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct i2c_mux_core *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int mux_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool mux_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct v4l2_ctrl_handler ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct v4l2_ctrl *pixelrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct v4l2_mbus_framefmt fmt[MAX9286_N_SINKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Protects controls and fmt structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned int nsources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int source_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int route_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int bound_sources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int csi2_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct max9286_source sources[MAX9286_NUM_GMSL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct v4l2_async_notifier notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static struct max9286_source *next_source(struct max9286_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct max9286_source *source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (!source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) source = &priv->sources[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) source++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) for (; source < &priv->sources[MAX9286_NUM_GMSL]; source++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (source->fwnode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define for_each_source(priv, source) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) for ((source) = NULL; ((source) = next_source((priv), (source))); )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define to_index(priv, source) ((source) - &(priv)->sources[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static inline struct max9286_priv *sd_to_max9286(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return container_of(sd, struct max9286_priv, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * I2C IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int max9286_read(struct max9286_priv *priv, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ret = i2c_smbus_read_byte_data(priv->client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_err(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "%s: register 0x%02x read failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) __func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int max9286_write(struct max9286_priv *priv, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = i2c_smbus_write_byte_data(priv->client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_err(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "%s: register 0x%02x write failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) __func__, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * I2C Multiplexer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void max9286_i2c_mux_configure(struct max9286_priv *priv, u8 conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) max9286_write(priv, 0x0a, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * We must sleep after any change to the forward or reverse channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void max9286_i2c_mux_open(struct max9286_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Open all channels on the MAX9286 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) max9286_i2c_mux_configure(priv, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) priv->mux_open = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void max9286_i2c_mux_close(struct max9286_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Ensure that both the forward and reverse channel are disabled on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * mux, and that the channel ID is invalidated to ensure we reconfigure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * on the next max9286_i2c_mux_select() call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) max9286_i2c_mux_configure(priv, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) priv->mux_open = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) priv->mux_channel = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int max9286_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct max9286_priv *priv = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Channel select is disabled when configured in the opened state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (priv->mux_open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (priv->mux_channel == chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) priv->mux_channel = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) max9286_i2c_mux_configure(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MAX9286_FWDCCEN(chan) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MAX9286_REVCCEN(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int max9286_i2c_mux_init(struct max9286_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct max9286_source *source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (!i2c_check_functionality(priv->client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) priv->nsources, 0, I2C_MUX_LOCKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) max9286_i2c_mux_select, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (!priv->mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) priv->mux->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) for_each_source(priv, source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned int index = to_index(priv, source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = i2c_mux_add_adapter(priv->mux, 0, index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) i2c_mux_del_adapters(priv->mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void max9286_configure_i2c(struct max9286_priv *priv, bool localack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 config = MAX9286_I2CSLVSH_469NS_234NS | MAX9286_I2CSLVTO_1024US |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MAX9286_I2CMSTBT_105KBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (localack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) config |= MAX9286_I2CLOCACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) max9286_write(priv, 0x34, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * max9286_check_video_links() - Make sure video links are detected and locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Performs safety checks on video link status. Make sure they are detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * and all enabled links are locked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Returns 0 for success, -EIO for errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int max9286_check_video_links(struct max9286_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Make sure valid video links are detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * The delay is not characterized in de-serializer manual, wait up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * to 5 ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = max9286_read(priv, 0x49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if ((ret & MAX9286_VIDEO_DETECT_MASK) == priv->source_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) usleep_range(350, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (i == 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_err(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "Unable to detect video links: 0x%02x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Make sure all enabled links are locked (4ms max). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = max9286_read(priv, 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (ret & MAX9286_LOCKED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) usleep_range(350, 450);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (i == 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_err(&priv->client->dev, "Not all enabled links locked\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * max9286_check_config_link() - Detect and wait for configuration links
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * Determine if the configuration channel is up and settled for a link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Returns 0 for success, -EIO for errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int max9286_check_config_link(struct max9286_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int source_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned int conflink_mask = (source_mask & 0x0f) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * Make sure requested configuration links are detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * The delay is not characterized in the chip manual: wait up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * to 5 milliseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = max9286_read(priv, 0x49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret &= 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ret == conflink_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) usleep_range(350, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (ret != conflink_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_err(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "Unable to detect configuration links: 0x%02x expected 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret, conflink_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_info(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "Successfully detected configuration links after %u loops: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) i, conflink_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * V4L2 Subdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int max9286_set_pixelrate(struct max9286_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct max9286_source *source = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u64 pixelrate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) for_each_source(priv, source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u64 source_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Pixel rate is mandatory to be reported by sources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ctrl = v4l2_ctrl_find(source->sd->ctrl_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) V4L2_CID_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pixelrate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* All source must report the same pixel rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) source_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (!pixelrate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pixelrate = source_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) } else if (pixelrate != source_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_err(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "Unable to calculate pixel rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (!pixelrate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_err(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) "No pixel rate control available in sources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * The CSI-2 transmitter pixel rate is the single source rate multiplied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * by the number of available sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return v4l2_ctrl_s_ctrl_int64(priv->pixelrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pixelrate * priv->nsources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int max9286_notify_bound(struct v4l2_async_notifier *notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct v4l2_subdev *subdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct v4l2_async_subdev *asd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct max9286_priv *priv = sd_to_max9286(notifier->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct max9286_source *source = to_max9286_asd(asd)->source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned int index = to_index(priv, source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned int src_pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ret = media_entity_get_fwnode_pad(&subdev->entity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) source->fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MEDIA_PAD_FL_SOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_err(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) "Failed to find pad for %s\n", subdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) priv->bound_sources |= BIT(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) source->sd = subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) src_pad = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ret = media_create_pad_link(&source->sd->entity, src_pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) &priv->sd.entity, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MEDIA_LNK_FL_ENABLED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MEDIA_LNK_FL_IMMUTABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dev_err(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "Unable to link %s:%u -> %s:%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) source->sd->name, src_pad, priv->sd.name, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev_dbg(&priv->client->dev, "Bound %s pad: %u on index %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) subdev->name, src_pad, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * We can only register v4l2_async_notifiers, which do not provide a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * means to register a complete callback. bound_sources allows us to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * identify when all remote serializers have completed their probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (priv->bound_sources != priv->source_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * All enabled sources have probed and enabled their reverse control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * channels:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * - Verify all configuration links are properly detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * - Disable auto-ack as communication on the control channel are now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * stable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) max9286_check_config_link(priv, priv->source_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * Re-configure I2C with local acknowledge disabled after cameras have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * probed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) max9286_configure_i2c(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return max9286_set_pixelrate(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static void max9286_notify_unbind(struct v4l2_async_notifier *notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct v4l2_subdev *subdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct v4l2_async_subdev *asd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct max9286_priv *priv = sd_to_max9286(notifier->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct max9286_source *source = to_max9286_asd(asd)->source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned int index = to_index(priv, source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) source->sd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) priv->bound_sources &= ~BIT(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static const struct v4l2_async_notifier_operations max9286_notify_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .bound = max9286_notify_bound,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .unbind = max9286_notify_unbind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int max9286_v4l2_notifier_register(struct max9286_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct device *dev = &priv->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct max9286_source *source = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (!priv->nsources)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) v4l2_async_notifier_init(&priv->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) for_each_source(priv, source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned int i = to_index(priv, source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct v4l2_async_subdev *asd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) asd = v4l2_async_notifier_add_fwnode_subdev(&priv->notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) source->fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) sizeof(struct max9286_asd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (IS_ERR(asd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dev_err(dev, "Failed to add subdev for source %u: %ld",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) i, PTR_ERR(asd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) v4l2_async_notifier_cleanup(&priv->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return PTR_ERR(asd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) to_max9286_asd(asd)->source = source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) priv->notifier.ops = &max9286_notify_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ret = v4l2_async_subdev_notifier_register(&priv->sd, &priv->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dev_err(dev, "Failed to register subdev_notifier");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) v4l2_async_notifier_cleanup(&priv->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void max9286_v4l2_notifier_unregister(struct max9286_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (!priv->nsources)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) v4l2_async_notifier_unregister(&priv->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) v4l2_async_notifier_cleanup(&priv->notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int max9286_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct max9286_priv *priv = sd_to_max9286(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct max9286_source *source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) bool sync = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * The frame sync between cameras is transmitted across the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * reverse channel as GPIO. We must open all channels while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * streaming to allow this synchronisation signal to be shared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) max9286_i2c_mux_open(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Start all cameras. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) for_each_source(priv, source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = v4l2_subdev_call(source->sd, video, s_stream, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = max9286_check_video_links(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * Wait until frame synchronization is locked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * Manual says frame sync locking should take ~6 VTS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * From practical experience at least 8 are required. Give
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * 12 complete frames time (~400ms at 30 fps) to achieve frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * locking before returning error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) for (i = 0; i < 40; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (max9286_read(priv, 0x31) & MAX9286_FSYNC_LOCKED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) sync = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) usleep_range(9000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (!sync) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dev_err(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) "Failed to get frame synchronization\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return -EXDEV; /* Invalid cross-device link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * Enable CSI output, VC set according to link number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Bit 7 must be set (chip manual says it's 0 and reserved).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) max9286_write(priv, 0x15, 0x80 | MAX9286_VCTYPE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) MAX9286_CSIOUTEN | MAX9286_0X15_RESV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_0X15_RESV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Stop all cameras. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) for_each_source(priv, source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) v4l2_subdev_call(source->sd, video, s_stream, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) max9286_i2c_mux_close(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static int max9286_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (code->pad || code->index > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) code->code = MEDIA_BUS_FMT_UYVY8_1X16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static struct v4l2_mbus_framefmt *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) max9286_get_pad_format(struct max9286_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) unsigned int pad, u32 which)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) switch (which) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case V4L2_SUBDEV_FORMAT_TRY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return v4l2_subdev_get_try_format(&priv->sd, cfg, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case V4L2_SUBDEV_FORMAT_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return &priv->fmt[pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int max9286_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct max9286_priv *priv = sd_to_max9286(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct v4l2_mbus_framefmt *cfg_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (format->pad == MAX9286_SRC_PAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* Refuse non YUV422 formats as we hardcode DT to 8 bit YUV422 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) switch (format->format.code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) case MEDIA_BUS_FMT_UYVY8_1X16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) case MEDIA_BUS_FMT_VYUY8_1X16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) case MEDIA_BUS_FMT_YUYV8_1X16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) case MEDIA_BUS_FMT_YVYU8_1X16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) format->format.code = MEDIA_BUS_FMT_UYVY8_1X16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) cfg_fmt = max9286_get_pad_format(priv, cfg, format->pad, format->which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (!cfg_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) mutex_lock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) *cfg_fmt = format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) mutex_unlock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static int max9286_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct max9286_priv *priv = sd_to_max9286(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct v4l2_mbus_framefmt *cfg_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) unsigned int pad = format->pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * Multiplexed Stream Support: Support link validation by returning the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * format of the first bound link. All links must have the same format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * as we do not support mixing and matching of cameras connected to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * max9286.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (pad == MAX9286_SRC_PAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pad = __ffs(priv->bound_sources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) cfg_fmt = max9286_get_pad_format(priv, cfg, pad, format->which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (!cfg_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) mutex_lock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) format->format = *cfg_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) mutex_unlock(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static const struct v4l2_subdev_video_ops max9286_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .s_stream = max9286_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const struct v4l2_subdev_pad_ops max9286_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .enum_mbus_code = max9286_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .get_fmt = max9286_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .set_fmt = max9286_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const struct v4l2_subdev_ops max9286_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .video = &max9286_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .pad = &max9286_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static void max9286_init_format(struct v4l2_mbus_framefmt *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) fmt->width = 1280;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) fmt->height = 800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) fmt->code = MEDIA_BUS_FMT_UYVY8_1X16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) fmt->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) fmt->quantization = V4L2_QUANTIZATION_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static int max9286_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct v4l2_mbus_framefmt *format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) for (i = 0; i < MAX9286_N_SINKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) format = v4l2_subdev_get_try_format(subdev, fh->pad, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) max9286_init_format(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static const struct v4l2_subdev_internal_ops max9286_subdev_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .open = max9286_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static int max9286_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) case V4L2_CID_PIXEL_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static const struct v4l2_ctrl_ops max9286_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .s_ctrl = max9286_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int max9286_v4l2_register(struct max9286_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct device *dev = &priv->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct fwnode_handle *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* Register v4l2 async notifiers for connected Camera subdevices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = max9286_v4l2_notifier_register(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev_err(dev, "Unable to register V4L2 async notifiers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* Configure V4L2 for the MAX9286 itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) for (i = 0; i < MAX9286_N_SINKS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) max9286_init_format(&priv->fmt[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) v4l2_i2c_subdev_init(&priv->sd, priv->client, &max9286_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) priv->sd.internal_ops = &max9286_subdev_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) v4l2_ctrl_handler_init(&priv->ctrls, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) priv->pixelrate = v4l2_ctrl_new_std(&priv->ctrls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) &max9286_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) 1, INT_MAX, 1, 50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) priv->sd.ctrl_handler = &priv->ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ret = priv->ctrls.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) goto err_async;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) priv->pads[MAX9286_SRC_PAD].flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) for (i = 0; i < MAX9286_SRC_PAD; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) priv->pads[i].flags = MEDIA_PAD_FL_SINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = media_entity_pads_init(&priv->sd.entity, MAX9286_N_PADS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) priv->pads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) goto err_async;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), MAX9286_SRC_PAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (!ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) dev_err(dev, "Unable to retrieve endpoint on \"port@4\"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) goto err_async;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) priv->sd.fwnode = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ret = v4l2_async_register_subdev(&priv->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) dev_err(dev, "Unable to register subdevice\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) goto err_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) err_put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) fwnode_handle_put(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) err_async:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) max9286_v4l2_notifier_unregister(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static void max9286_v4l2_unregister(struct max9286_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) fwnode_handle_put(priv->sd.fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) v4l2_async_unregister_subdev(&priv->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) max9286_v4l2_notifier_unregister(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * Probe/Remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static int max9286_setup(struct max9286_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * Link ordering values for all enabled links combinations. Orders must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * be assigned sequentially from 0 to the number of enabled links
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * without leaving any hole for disabled links. We thus assign orders to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * enabled links first, and use the remaining order values for disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * links are all links must have a different order value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static const u8 link_order[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxx0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) (3 << 6) | (2 << 4) | (0 << 2) | (1 << 0), /* xx0x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xx10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) (3 << 6) | (0 << 4) | (2 << 2) | (1 << 0), /* x0xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) (3 << 6) | (1 << 4) | (2 << 2) | (0 << 0), /* x1x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) (3 << 6) | (1 << 4) | (0 << 2) | (2 << 0), /* x10x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) (3 << 6) | (1 << 4) | (1 << 2) | (0 << 0), /* x210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) (0 << 6) | (3 << 4) | (2 << 2) | (1 << 0), /* 0xxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) (1 << 6) | (3 << 4) | (2 << 2) | (0 << 0), /* 1xx0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) (1 << 6) | (3 << 4) | (0 << 2) | (2 << 0), /* 1x0x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) (2 << 6) | (3 << 4) | (1 << 2) | (0 << 0), /* 2x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) (1 << 6) | (0 << 4) | (3 << 2) | (2 << 0), /* 10xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) (2 << 6) | (1 << 4) | (3 << 2) | (0 << 0), /* 21x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) (2 << 6) | (1 << 4) | (0 << 2) | (3 << 0), /* 210x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* 3210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * Set the I2C bus speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * Enable I2C Local Acknowledge during the probe sequences of the camera
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * only. This should be disabled after the mux is initialised.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) max9286_configure_i2c(priv, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * Reverse channel setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * - Enable custom reverse channel configuration (through register 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * and set the first pulse length to 35 clock cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * - Increase the reverse channel amplitude to 170mV to accommodate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * high threshold enabled by the serializer driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) max9286_write(priv, 0x3f, MAX9286_EN_REV_CFG | MAX9286_REV_FLEN(35));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) max9286_write(priv, 0x3b, MAX9286_REV_TRF(1) | MAX9286_REV_AMP(70) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) MAX9286_REV_AMP_X);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) usleep_range(2000, 2500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * Enable GMSL links, mask unused ones and autodetect link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * used as CSI clock source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) max9286_write(priv, 0x00, MAX9286_MSTLINKSEL_AUTO | priv->route_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) max9286_write(priv, 0x0b, link_order[priv->route_mask]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) max9286_write(priv, 0x69, (0xf & ~priv->route_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * Video format setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * Disable CSI output, VC is set according to Link number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_0X15_RESV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* Enable CSI-2 Lane D0-D3 only, DBL mode, YUV422 8-bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) max9286_write(priv, 0x12, MAX9286_CSIDBL | MAX9286_DBL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) MAX9286_CSILANECNT(priv->csi2_data_lanes) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) MAX9286_DATATYPE_YUV422_8BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* Automatic: FRAMESYNC taken from the slowest Link. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_HIZ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) MAX9286_FSYNCMETH_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* Enable HS/VS encoding, use D14/15 for HS/VS, invert VS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) max9286_write(priv, 0x0c, MAX9286_HVEN | MAX9286_INVVS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) MAX9286_HVSRC_D14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * The overlap window seems to provide additional validation by tracking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * the delay between vsync and frame sync, generating an error if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * delay is bigger than the programmed window, though it's not yet clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * what value should be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * As it's an optional value and can be disabled, we do so by setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * a 0 overlap value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) max9286_write(priv, 0x63, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) max9286_write(priv, 0x64, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * Wait for 2ms to allow the link to resynchronize after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * configuration change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) usleep_range(2000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static void max9286_gpio_set(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct max9286_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) priv->gpio_state |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) priv->gpio_state &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) max9286_write(priv, 0x0f, MAX9286_0X0F_RESERVED | priv->gpio_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static int max9286_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct max9286_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return priv->gpio_state & BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static int max9286_register_gpio(struct max9286_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct device *dev = &priv->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct gpio_chip *gpio = &priv->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* Configure the GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) gpio->label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) gpio->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) gpio->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) gpio->of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) gpio->ngpio = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) gpio->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) gpio->set = max9286_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) gpio->get = max9286_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) gpio->can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* GPIO values default to high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) priv->gpio_state = BIT(0) | BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ret = devm_gpiochip_add_data(dev, gpio, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dev_err(dev, "Unable to create gpio_chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static int max9286_init(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct max9286_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) priv = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* Enable the bus power. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ret = regulator_enable(priv->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) dev_err(&client->dev, "Unable to turn PoC on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ret = max9286_setup(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dev_err(dev, "Unable to setup max9286\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) goto err_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * Register all V4L2 interactions for the MAX9286 and notifiers for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * any subdevices connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ret = max9286_v4l2_register(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dev_err(dev, "Failed to register with V4L2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) goto err_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = max9286_i2c_mux_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) dev_err(dev, "Unable to initialize I2C multiplexer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) goto err_v4l2_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* Leave the mux channels disabled until they are selected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) max9286_i2c_mux_close(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) err_v4l2_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) max9286_v4l2_unregister(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) err_regulator:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) regulator_disable(priv->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static void max9286_cleanup_dt(struct max9286_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct max9286_source *source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) for_each_source(priv, source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) fwnode_handle_put(source->fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) source->fwnode = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static int max9286_parse_dt(struct max9286_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct device *dev = &priv->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct device_node *i2c_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct device_node *node = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) unsigned int i2c_mux_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* Balance the of_node_put() performed by of_find_node_by_name(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) of_node_get(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) i2c_mux = of_find_node_by_name(dev->of_node, "i2c-mux");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (!i2c_mux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dev_err(dev, "Failed to find i2c-mux node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* Identify which i2c-mux channels are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) for_each_child_of_node(i2c_mux, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) of_property_read_u32(node, "reg", &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (id >= MAX9286_NUM_GMSL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (!of_device_is_available(node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) dev_dbg(dev, "Skipping disabled I2C bus port %u\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) i2c_mux_mask |= BIT(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) of_node_put(i2c_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* Parse the endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) for_each_endpoint_of_node(dev->of_node, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct max9286_source *source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct of_endpoint ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) of_graph_parse_endpoint(node, &ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev_dbg(dev, "Endpoint %pOF on port %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ep.local_node, ep.port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (ep.port > MAX9286_NUM_GMSL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) dev_err(dev, "Invalid endpoint %s on port %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) of_node_full_name(ep.local_node), ep.port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* For the source endpoint just parse the bus configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (ep.port == MAX9286_SRC_PAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) struct v4l2_fwnode_endpoint vep = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .bus_type = V4L2_MBUS_CSI2_DPHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ret = v4l2_fwnode_endpoint_parse(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) of_fwnode_handle(node), &vep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) priv->csi2_data_lanes =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) vep.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* Skip if the corresponding GMSL link is unavailable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (!(i2c_mux_mask & BIT(ep.port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (priv->sources[ep.port].fwnode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) "Multiple port endpoints are not supported: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ep.port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) source = &priv->sources[ep.port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) source->fwnode = fwnode_graph_get_remote_endpoint(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) of_fwnode_handle(node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (!source->fwnode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) "Endpoint %pOF has no remote endpoint connection\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ep.local_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) priv->source_mask |= BIT(ep.port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) priv->nsources++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) priv->route_mask = priv->source_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static int max9286_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) struct max9286_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) mutex_init(&priv->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) priv->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) i2c_set_clientdata(client, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) priv->gpiod_pwdn = devm_gpiod_get_optional(&client->dev, "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (IS_ERR(priv->gpiod_pwdn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return PTR_ERR(priv->gpiod_pwdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) gpiod_set_consumer_name(priv->gpiod_pwdn, "max9286-pwdn");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) gpiod_set_value_cansleep(priv->gpiod_pwdn, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* Wait at least 4ms before the I2C lines latch to the address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (priv->gpiod_pwdn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) usleep_range(4000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * The MAX9286 starts by default with all ports enabled, we disable all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * ports early to ensure that all channels are disabled if we error out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * and keep the bus consistent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) max9286_i2c_mux_close(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * The MAX9286 initialises with auto-acknowledge enabled by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * This can be invasive to other transactions on the same bus, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * disable it early. It will be enabled only as and when needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) max9286_configure_i2c(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ret = max9286_register_gpio(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) goto err_powerdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) priv->regulator = devm_regulator_get(&client->dev, "poc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (IS_ERR(priv->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (PTR_ERR(priv->regulator) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) "Unable to get PoC regulator (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) PTR_ERR(priv->regulator));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) ret = PTR_ERR(priv->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) goto err_powerdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) ret = max9286_parse_dt(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) goto err_powerdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ret = max9286_init(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) goto err_cleanup_dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) err_cleanup_dt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) max9286_cleanup_dt(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) err_powerdown:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static int max9286_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct max9286_priv *priv = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) i2c_mux_del_adapters(priv->mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) max9286_v4l2_unregister(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) regulator_disable(priv->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) max9286_cleanup_dt(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static const struct of_device_id max9286_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) { .compatible = "maxim,max9286" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) MODULE_DEVICE_TABLE(of, max9286_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) static struct i2c_driver max9286_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .name = "max9286",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .of_match_table = of_match_ptr(max9286_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .probe_new = max9286_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .remove = max9286_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) module_i2c_driver(max9286_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) MODULE_DESCRIPTION("Maxim MAX9286 GMSL Deserializer Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) MODULE_AUTHOR("Jacopo Mondi, Kieran Bingham, Laurent Pinchart, Niklas Söderlund, Vladimir Barinov");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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