Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2017-2020 Jacopo Mondi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2017-2020 Kieran Bingham
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017-2020 Laurent Pinchart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2017-2020 Niklas Söderlund
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2016 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2015 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define MAX9271_DEFAULT_ADDR	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* Register 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MAX9271_SPREAD_SPECT_0		(0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MAX9271_SPREAD_SPECT_05		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MAX9271_SPREAD_SPECT_15		(2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MAX9271_SPREAD_SPECT_1		(5 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MAX9271_SPREAD_SPECT_2		(3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MAX9271_SPREAD_SPECT_3		(6 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MAX9271_SPREAD_SPECT_4		(7 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MAX9271_R02_RES			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MAX9271_PCLK_AUTODETECT		(3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MAX9271_SERIAL_AUTODETECT	(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* Register 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MAX9271_SEREN			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MAX9271_CLINKEN			BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MAX9271_PRBSEN			BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MAX9271_SLEEP			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MAX9271_INTTYPE_I2C		(0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MAX9271_INTTYPE_UART		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MAX9271_INTTYPE_NONE		(2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MAX9271_REVCCEN			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MAX9271_FWDCCEN			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Register 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MAX9271_DBL			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MAX9271_DRS			BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MAX9271_BWS			BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MAX9271_ES			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MAX9271_HVEN			BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MAX9271_EDC_1BIT_PARITY		(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MAX9271_EDC_6BIT_CRC		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MAX9271_EDC_6BIT_HAMMING	(2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* Register 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MAX9271_INVVS			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MAX9271_INVHS			BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MAX9271_REV_LOGAIN		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MAX9271_REV_HIVTH		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* Register 0x09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MAX9271_ID			0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* Register 0x0d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MAX9271_I2CLOCACK		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MAX9271_I2CSLVSH_1046NS_469NS	(3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MAX9271_I2CSLVSH_938NS_352NS	(2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MAX9271_I2CSLVSH_469NS_234NS	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MAX9271_I2CSLVSH_352NS_117NS	(0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MAX9271_I2CMSTBT_837KBPS	(7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MAX9271_I2CMSTBT_533KBPS	(6 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MAX9271_I2CMSTBT_339KBPS	(5 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MAX9271_I2CMSTBT_173KBPS	(4 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MAX9271_I2CMSTBT_105KBPS	(3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MAX9271_I2CMSTBT_84KBPS		(2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MAX9271_I2CMSTBT_28KBPS		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MAX9271_I2CMSTBT_8KBPS		(0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MAX9271_I2CSLVTO_NONE		(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MAX9271_I2CSLVTO_1024US		(2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MAX9271_I2CSLVTO_256US		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MAX9271_I2CSLVTO_64US		(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* Register 0x0f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MAX9271_GPIO5OUT		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MAX9271_GPIO4OUT		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MAX9271_GPIO3OUT		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define MAX9271_GPIO2OUT		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MAX9271_GPIO1OUT		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define MAX9271_GPO			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* Register 0x15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MAX9271_PCLKDET			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * struct max9271_device - max9271 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * @client: The i2c client for the max9271 instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) struct max9271_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * max9271_set_serial_link() - Enable/disable serial link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * @dev: The max9271 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * @enable: Serial link enable/disable flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * Return 0 on success or a negative error code on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) int max9271_set_serial_link(struct max9271_device *dev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * max9271_configure_i2c() - Configure I2C bus parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * @dev: The max9271 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * @i2c_config: The I2C bus configuration bit mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * Configure MAX9271 I2C interface. The bus configuration provided in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * @i2c_config parameter shall be assembled using bit values defined by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * MAX9271_I2C* macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * Return 0 on success or a negative error code on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int max9271_configure_i2c(struct max9271_device *dev, u8 i2c_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * max9271_set_high_threshold() - Enable or disable reverse channel high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  *				  threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * @dev: The max9271 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * @enable: High threshold enable/disable flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * Return 0 on success or a negative error code on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int max9271_set_high_threshold(struct max9271_device *dev, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * max9271_configure_gmsl_link() - Configure the GMSL link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * @dev: The max9271 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * FIXME: the GMSL link configuration is currently hardcoded and performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * by programming registers 0x04, 0x07 and 0x02.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * Return 0 on success or a negative error code on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int max9271_configure_gmsl_link(struct max9271_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * max9271_set_gpios() - Set gpio lines to physical high value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * @dev: The max9271 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * @gpio_mask: The mask of gpio lines to set to high value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * The @gpio_mask parameter shall be assembled using the MAX9271_GP[IO|O]*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  * bit values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * Return 0 on success or a negative error code on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int max9271_set_gpios(struct max9271_device *dev, u8 gpio_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * max9271_clear_gpios() - Set gpio lines to physical low value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * @dev: The max9271 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * @gpio_mask: The mask of gpio lines to set to low value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * The @gpio_mask parameter shall be assembled using the MAX9271_GP[IO|O]*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * bit values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * Return 0 on success or a negative error code on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int max9271_clear_gpios(struct max9271_device *dev, u8 gpio_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * max9271_enable_gpios() - Enable gpio lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * @dev: The max9271 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  * @gpio_mask: The mask of gpio lines to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * The @gpio_mask parameter shall be assembled using the MAX9271_GPIO*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  * bit values. GPO line is always enabled by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * Return 0 on success or a negative error code on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int max9271_enable_gpios(struct max9271_device *dev, u8 gpio_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * max9271_disable_gpios() - Disable gpio lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  * @dev: The max9271 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * @gpio_mask: The mask of gpio lines to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * The @gpio_mask parameter shall be assembled using the MAX9271_GPIO*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * bit values. GPO line is always enabled by default and cannot be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * Return 0 on success or a negative error code on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int max9271_disable_gpios(struct max9271_device *dev, u8 gpio_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  * max9271_verify_id() - Read and verify MAX9271 id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  * @dev: The max9271 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  * Return 0 on success or a negative error code on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int max9271_verify_id(struct max9271_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  * max9271_set_address() - Program a new I2C address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * @dev: The max9271 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * @addr: The new I2C address in 7-bit format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  * This function only takes care of programming the new I2C address @addr to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * in the MAX9271 chip registers, it is responsiblity of the caller to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * the i2c address client to the @addr value to be able to communicate with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  * the MAX9271 chip using the I2C framework APIs after this function returns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  * Return 0 on success or a negative error code on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int max9271_set_address(struct max9271_device *dev, u8 addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * max9271_set_deserializer_address() - Program the remote deserializer address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * @dev: The max9271 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * @addr: The deserializer I2C address in 7-bit format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * Return 0 on success or a negative error code on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int max9271_set_deserializer_address(struct max9271_device *dev, u8 addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  * max9271_set_translation() - Program I2C address translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * @dev: The max9271 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * @source: The I2C source address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  * @dest: The I2C destination address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  * Program address translation from @source to @dest. This is required to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * communicate with local devices that do not support address reprogramming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  * TODO: The device supports translation of two address, this function currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  * supports a single one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  * Return 0 on success or a negative error code on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int max9271_set_translation(struct max9271_device *dev, u8 source, u8 dest);