^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Dingxian Wen <shawn.wen@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _LT8619C_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _LT8619C_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* --------------- configuration -------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLK_SRC XTAL_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define REF_RESISTANCE EXT_RESISTANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CP_CONVERT_MODE HDPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define YUV_COLORDEPTH OUTPUT_16BIT_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BT_TX_SYNC_POL BT_TX_SYNC_POSITIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* -------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LT8619C_CHIPID 0x1604B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EDID_NUM_BLOCKS_MAX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EDID_BLOCK_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define POLL_INTERVAL_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define lt8619c_PIXEL_RATE 400000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BANK_REG 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BANK_60 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BANK_80 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CHIPID_REG_H 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CHIPID_REG_M 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CHIPID_REG_L 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LT8619C_MAX_REGISTER 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define WAIT_MAX_TIMES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BT656_OUTPUT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BT1120_OUTPUT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BT1120_8BIT_OUTPUT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BT_TX_SYNC_POSITIVE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BT_TX_SYNC_NEGATIVE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PROGRESSIVE_INDICATOR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define INTERLACE_INDICATOR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* 0x08: Use xtal clk; 0x18: Use internal clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XTAL_CLK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define INT_CLK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* internal resistance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define INT_RESISTANCE 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* external resistance(Pin 16 - REXT, 2K resistance) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EXT_RESISTANCE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_SDRMODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* CLK divided by 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_DDRMODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SDTV 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SDPC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HDTV 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HDPC 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * D0 ~ D7 Y ; D8 ~ D15 C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * D8 ~ D15 Y ; D16 ~ D23 C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define YC_SWAP_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * D0 ~ D7 C ; D8 ~ D15 Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * D8 ~ D15 C ; D16 ~ D23 Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define YC_SWAP_DIS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * BT1120 24bit / BT656 12bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * when YC_SWAP_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * BT656 12bit D0 ~ D11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * BT1120 24bit : D0 ~ D11 Y ; D12 ~ D23 C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * when YC_SWAP_DIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * BT656 12bit D12 ~ D23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * BT1120 24bit : D0 ~ D11 C ; D12 ~ D23 Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OUTPUT_24BIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * BT1120 20bit / BT656 10bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * when YC_SWAP_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * BT656 10bit D4 ~ D13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * BT1120 20bit : D4 ~ D13 Y ; D14 ~ D23 C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * when YC_SWAP_DIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * BT656 10bit D14 ~ D23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * BT1120 20bit : D4 ~ D13 C ; D14 ~ D23 Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OUTPUT_20BIT_HIGH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * when YC_SWAP_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * BT656 10bit D0 ~ D9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * BT1120 20bit : D0 ~ D9 Y ; D10 ~ D19 C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * when YC_SWAP_DIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * BT656 10bit D10 ~ D19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * BT1120 20bit : D0 ~ D9 C ; D10 ~ D19 Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OUTPUT_20BIT_LOW 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * BT1120 16bit / BT656 8bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * when YC_SWAP_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * BT656 8bit D8 ~ D15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * BT1120 16bit : D8 ~ D15 Y ; D16 ~ D23 C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * when YC_SWAP_DIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * BT656 8bit D16 ~ D23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * BT1120 16bit : D8 ~ D15 C ; D16 ~ D23 Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OUTPUT_16BIT_HIGH 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * when YC_SWAP_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * BT656 8bit D0 ~ D7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * BT1120 16bit : D0 ~ D7 Y ; D8 ~ D15 C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * when YC_SWAP_DIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * BT656 8bit D8 ~ D15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * BT1120 16bit : D0 ~ D7 C ; D8 ~ D15 Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OUTPUT_16BIT_LOW 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* ---------------- regs ----------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* reg: 0x60_60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SYNC_POL_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IP_SEL_MASK GENMASK(3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OUTPUT_MODE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* reg: 0x80_05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RGD_HS_POL_ADJ_MASK GENMASK(5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RGD_VS_POL_ADJ_MASK GENMASK(4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* reg: 0x80_17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RGOD_VID_HSPOL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RGOD_VID_VSPOL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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