^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Dingxian Wen <shawn.wen@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 1. add BT656 mode support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2. add ddr mode support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 3. fix 576i and 480i support mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * V0.0X01.0X02 add 4K30 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/hdmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "lt8619c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LT8619C_NAME "LT8619C"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MODULE_PARM_DESC(debug, "debug level (0-2)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RK_CAMERA_MODULE_DUAL_EDGE "rockchip,dual-edge"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LT8619C_DEFAULT_DUAL_EDGE 1U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RK_CAMERA_MODULE_DVP_MODE "rockchip,dvp-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LT8619C_DEFAULT_DVP_MODE BT1120_OUTPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct lt8619c_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct lt8619c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct i2c_client *i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct mutex confctl_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct v4l2_ctrl *detect_tx_5v_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct delayed_work delayed_work_enable_hotplug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct delayed_work delayed_work_monitor_resolution;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct regmap *reg_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct gpio_desc *plugin_det_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const struct lt8619c_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bool nosignal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) bool enable_hdcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 clk_ddrmode_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bool BT656_double_clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) bool hpd_output_inverted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int plugin_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 edid_blocks_written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 mbus_fmt_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 yuv_output_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 cp_convert_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 yc_swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 yuv_colordepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 bt_tx_sync_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct v4l2_dv_timings_cap lt8619c_timings_cap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .type = V4L2_DV_BT_656_1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* keep this initialization for compatibility with GCC < 4.4.6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .reserved = { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 410000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) V4L2_DV_BT_CAP_REDUCED_BLANKING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) V4L2_DV_BT_CAP_CUSTOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static u8 edid_init_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 0x49, 0x78, 0x01, 0x88, 0x00, 0x88, 0x88, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0x1C, 0x1F, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0x6E, 0x28, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0x37, 0x34, 0x39, 0x2D, 0x66, 0x48, 0x44, 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0x32, 0x30, 0x0A, 0x20, 0x00, 0x00, 0x00, 0xFD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x00, 0x14, 0x78, 0x01, 0xFF, 0x1D, 0x00, 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0x02, 0x03, 0x1C, 0x71, 0x49, 0x90, 0x04, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0x5F, 0x11, 0x07, 0x05, 0x16, 0x22, 0x23, 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 0x07, 0x01, 0x83, 0x01, 0x00, 0x00, 0x65, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0x0C, 0x00, 0x10, 0x00, 0x8C, 0x0A, 0xD0, 0x8A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x3E, 0x96, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 0x13, 0x8E, 0x21, 0x00, 0x00, 0x1E, 0xD8, 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0x80, 0xA0, 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 0xA2, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 0x8C, 0x0A, 0xD0, 0x90, 0x20, 0x40, 0x31, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0x0C, 0x40, 0x55, 0x00, 0x48, 0x39, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 0x00, 0x18, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0xC0, 0x6C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0x00, 0x00, 0x00, 0x18, 0x01, 0x1D, 0x80, 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 0x71, 0x1C, 0x16, 0x20, 0x58, 0x2C, 0x25, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 0xC0, 0x6C, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static u8 phase_num[10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0x20, 0x28, 0x21, 0x29, 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 0x2a, 0x23, 0x2b, 0x24, 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct lt8619c_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .width = 3840,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .height = 2160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .hts_def = 4400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .vts_def = 2250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .hts_def = 2200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .vts_def = 1125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .hts_def = 2200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .vts_def = 1125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .height = 540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .hts_def = 2200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .vts_def = 562,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .height = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .hts_def = 1650,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .vts_def = 750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .width = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .height = 576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .denominator = 500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .hts_def = 864,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .vts_def = 625,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .width = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .hts_def = 858,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .vts_def = 525,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .width = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .hts_def = 1716,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .vts_def = 525,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .width = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .height = 576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .denominator = 500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .hts_def = 1728,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .vts_def = 625,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void lt8619c_set_hpd(struct v4l2_subdev *sd, int en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void lt8619c_wait_for_signal_stable(struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void lt8619c_yuv_config(struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void lt8619c_format_change(struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void enable_stream(struct v4l2_subdev *sd, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int lt8619c_s_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct v4l2_dv_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void LVDSPLL_Lock_Det(struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void LT8619C_phase_config(struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static bool lt8619c_rcv_supported_res(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct v4l2_dv_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static bool lt8619c_timing_changed(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct v4l2_dv_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static inline struct lt8619c *to_lt8619c(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return container_of(sd, struct lt8619c, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val = gpiod_get_value(lt8619c->plugin_det_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) v4l2_dbg(1, debug, sd, "%s 5v_present: %d!\n", __func__, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return (val > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static inline bool no_signal(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) v4l2_dbg(1, debug, sd, "no signal:%d\n", lt8619c->nosignal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return lt8619c->nosignal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static bool lt8619c_is_supported_interlaced_res(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 hact, u32 vact)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if ((hact == 1920 && vact == 540) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) (hact == 1440 && vact == 288) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) (hact == 1440 && vact == 240))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int lt8619c_get_detected_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct v4l2_bt_timings *bt = &timings->bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 hact, vact, htotal, vtotal, hbp, hfp, hs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 fps, hdmi_clk_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 val, vbp, vfp, vs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 pix_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) memset(timings, 0, sizeof(struct v4l2_dv_timings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) timings->type = V4L2_DV_BT_656_1120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) regmap_read(lt8619c->reg_map, 0x22, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) hact = val << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) regmap_read(lt8619c->reg_map, 0x23, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) hact |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) regmap_read(lt8619c->reg_map, 0x20, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) vact = (val & 0xf) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) regmap_read(lt8619c->reg_map, 0x21, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) vact |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) regmap_read(lt8619c->reg_map, 0x1e, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) htotal = val << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) regmap_read(lt8619c->reg_map, 0x1f, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) htotal |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) regmap_read(lt8619c->reg_map, 0x1c, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) vtotal = (val & 0xf) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) regmap_read(lt8619c->reg_map, 0x1d, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) vtotal |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) regmap_read(lt8619c->reg_map, 0x1a, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) hfp = val << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) regmap_read(lt8619c->reg_map, 0x1b, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) hfp |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) regmap_read(lt8619c->reg_map, 0x18, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) hbp = val << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) regmap_read(lt8619c->reg_map, 0x19, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) hbp |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) regmap_read(lt8619c->reg_map, 0x14, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) hs = val << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) regmap_read(lt8619c->reg_map, 0x15, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) hs |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) regmap_read(lt8619c->reg_map, 0x17, &vfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) regmap_read(lt8619c->reg_map, 0x16, &vbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) regmap_read(lt8619c->reg_map, 0x13, &vs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) regmap_read(lt8619c->reg_map, 0x44, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) hdmi_clk_cnt = (val & 0x3) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) regmap_read(lt8619c->reg_map, 0x45, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) hdmi_clk_cnt |= val << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) regmap_read(lt8619c->reg_map, 0x46, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) hdmi_clk_cnt |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) bt->width = hact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) bt->height = vact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) bt->hfrontporch = hfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bt->hsync = hs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) bt->hbackporch = hbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) bt->vfrontporch = vfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) bt->vsync = vs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) bt->vbackporch = vbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pix_clk = hdmi_clk_cnt * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) bt->pixelclock = pix_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) fps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (htotal * vtotal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) fps = (pix_clk + (htotal * vtotal) / 2) / (htotal * vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* for interlaced res 1080i 576i 480i */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (lt8619c_is_supported_interlaced_res(sd, hact, vact)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) bt->interlaced = V4L2_DV_INTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) bt->height *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) bt->il_vsync = bt->vsync + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) bt->interlaced = V4L2_DV_PROGRESSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "%s: act:%dx%d, total:%dx%d, fps:%d, pixclk:%llu, frame mode:%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) __func__, hact, vact, htotal, vtotal, fps, bt->pixelclock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) (bt->interlaced == V4L2_DV_INTERLACED) ? "I" : "P");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "%s: hfp:%d, hs:%d, hbp:%d, vfp:%d, vs:%d, vbp:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) __func__, bt->hfrontporch, bt->hsync, bt->hbackporch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) bt->vfrontporch, bt->vsync, bt->vbackporch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void lt8619c_config_all(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) lt8619c_wait_for_signal_stable(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) LVDSPLL_Lock_Det(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) lt8619c_yuv_config(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) LT8619C_phase_config(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) lt8619c_format_change(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void lt8619c_delayed_work_enable_hotplug(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct delayed_work *dwork = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct lt8619c *lt8619c = container_of(dwork, struct lt8619c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct v4l2_subdev *sd = <8619c->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) v4l2_dbg(2, debug, sd, "%s: in\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mutex_lock(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (tx_5v_power_present(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) lt8619c_set_hpd(sd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) lt8619c_config_all(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) lt8619c->nosignal = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* monitor resolution after 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) schedule_delayed_work(<8619c->delayed_work_monitor_resolution,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) HZ / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) cancel_delayed_work(<8619c->delayed_work_monitor_resolution);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) lt8619c_set_hpd(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) lt8619c->nosignal = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mutex_unlock(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static void lt8619c_delayed_work_monitor_resolution(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct delayed_work *dwork = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct lt8619c *lt8619c = container_of(dwork, struct lt8619c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) delayed_work_monitor_resolution);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct v4l2_subdev *sd = <8619c->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) bool is_supported_res, is_timing_changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) v4l2_dbg(1, debug, sd, "%s: in\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (!tx_5v_power_present(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) v4l2_dbg(2, debug, sd, "%s: HDMI pull out, return!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) lt8619c->nosignal = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mutex_lock(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) lt8619c_get_detected_timings(sd, &timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) is_supported_res = lt8619c_rcv_supported_res(sd, &timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) is_timing_changed = lt8619c_timing_changed(sd, &timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) v4l2_dbg(2, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) "%s: is_supported_res: %d, is_timing_changed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) __func__, is_supported_res, is_timing_changed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!is_supported_res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) lt8619c->nosignal = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) v4l2_dbg(1, debug, sd, "%s: no supported res, cfg as nosignal!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (is_supported_res && is_timing_changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) lt8619c_config_all(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) lt8619c->nosignal = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mutex_unlock(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) schedule_delayed_work(<8619c->delayed_work_monitor_resolution, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void lt8619c_load_hdcpkey(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int wait_cnt = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) regmap_write(lt8619c->reg_map, 0xb2, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) regmap_write(lt8619c->reg_map, 0xa3, 0x77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) while (wait_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) usleep_range(50*1000, 50*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) regmap_read(lt8619c->reg_map, 0xc0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (val & 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) wait_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) regmap_write(lt8619c->reg_map, 0xb2, 0xd0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) regmap_write(lt8619c->reg_map, 0xa3, 0x57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (val & 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) v4l2_info(sd, "load hdcp key success!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) v4l2_err(sd, "load hdcp key failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static void lt8619c_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) v4l2_dbg(2, debug, sd, "%s: %sable\n", __func__, enable ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) lt8619c_load_hdcpkey(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) v4l2_info(sd, "disable hdcp function!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static void lt8619c_mode_config(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) regmap_update_bits(lt8619c->reg_map, 0x2c, BIT(5) | BIT(4), BIT(5) | BIT(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) regmap_write(lt8619c->reg_map, 0x80, CLK_SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) regmap_write(lt8619c->reg_map, 0x89, REF_RESISTANCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) regmap_write(lt8619c->reg_map, 0x8b, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Turn off BT output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) regmap_write(lt8619c->reg_map, 0xa8, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* enable PLL detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) regmap_write(lt8619c->reg_map, 0x04, 0xf2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (lt8619c->BT656_double_clk_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) regmap_write(lt8619c->reg_map, 0x96, 0x71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) regmap_write(lt8619c->reg_map, 0xa0, 0x51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) regmap_write(lt8619c->reg_map, 0xa3, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) regmap_write(lt8619c->reg_map, 0xa2, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) regmap_write(lt8619c->reg_map, 0x96, 0x71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) regmap_write(lt8619c->reg_map, 0xa0, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) regmap_write(lt8619c->reg_map, 0xa3, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) regmap_write(lt8619c->reg_map, 0xa2, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) regmap_update_bits(lt8619c->reg_map, 0x60, OUTPUT_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) lt8619c->yuv_output_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (lt8619c->clk_ddrmode_en == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) regmap_write(lt8619c->reg_map, 0xa4, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) regmap_write(lt8619c->reg_map, 0xa4, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* Vblank change reference EAV flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) regmap_write(lt8619c->reg_map, 0x6f, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) v4l2_dbg(1, debug, sd, "%s: output mode:%s, clk ddrmode en:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) __func__, (lt8619c->yuv_output_mode == BT656_OUTPUT) ? "BT656" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) "BT1120", lt8619c->clk_ddrmode_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void lt8619c_set_hpd(struct v4l2_subdev *sd, int en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) v4l2_dbg(2, debug, sd, "%s: %d\n", __func__, en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) level = lt8619c->hpd_output_inverted ? !en : en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) regmap_update_bits(lt8619c->reg_map, 0x06, BIT(3), BIT(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) regmap_update_bits(lt8619c->reg_map, 0x06, BIT(3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static void lt8619c_write_edid(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct v4l2_subdev_edid *edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 edid_len = edid->blocks * EDID_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Enable EDID shadow operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) regmap_write(lt8619c->reg_map, 0x8e, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* EDID data write start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) regmap_write(lt8619c->reg_map, 0x8f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) for (i = 0; i < edid_len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) regmap_write(lt8619c->reg_map, 0x90, edid->edid[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) regmap_write(lt8619c->reg_map, 0x8e, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static void lt8619c_read_edid(struct v4l2_subdev *sd, u8 *edid, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* Enable EDID shadow operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) regmap_write(lt8619c->reg_map, 0x8e, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* EDID data write start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) regmap_write(lt8619c->reg_map, 0x8f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) regmap_read(lt8619c->reg_map, 0x90, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) edid[i] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) regmap_write(lt8619c->reg_map, 0x8e, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int lt8619c_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return v4l2_ctrl_s_ctrl(lt8619c->detect_tx_5v_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) tx_5v_power_present(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int lt8619c_update_controls(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret = lt8619c_s_ctrl_detect_tx_5v(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static void enable_stream(struct v4l2_subdev *sd, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) v4l2_info(sd, "%s: stream on!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) v4l2_info(sd, "%s: stream off!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static void lt8619c_set_bt_tx_timing(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct v4l2_bt_timings *bt = &timings.bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u32 h_offset, v_offset, v_blank, htotal, vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u32 hact, hfp, hbp, hs, vact, vfp, vbp, vs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u32 double_cnt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* read timing from HDMI RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) lt8619c_get_detected_timings(sd, &timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) hact = bt->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) vact = bt->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) hfp = bt->hfrontporch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) hs = bt->hsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) hbp = bt->hbackporch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) vfp = bt->vfrontporch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) vs = bt->vsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) vbp = bt->vbackporch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) htotal = hs + hbp + hact + hfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) vtotal = vs + vbp + vact + vfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) h_offset = hbp + hs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) v_offset = vbp + vs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) v_blank = vtotal - vact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (bt->interlaced == V4L2_DV_INTERLACED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* already *2 in lt8619c_get_detected_timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) vact /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) double_cnt = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) regmap_update_bits(lt8619c->reg_map, 0x60, IP_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) INTERLACE_INDICATOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) vact = vact * double_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) vtotal = vtotal * double_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) v4l2_dbg(2, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) "%s: act:%dx%d, total:%dx%d, h_offset:%d, v_offset:%d, v_blank:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) __func__, hact, vact, htotal, vtotal, h_offset, v_offset, v_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) v4l2_dbg(2, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) "%s: hfp:%d, hs:%d, hbp:%d, vfp:%d, vs:%d, vbp:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) __func__, hfp, hs, hbp, vfp, vs, vbp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* write timing to BT TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) regmap_write(lt8619c->reg_map, 0x61, (h_offset >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) regmap_write(lt8619c->reg_map, 0x62, h_offset & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) regmap_write(lt8619c->reg_map, 0x63, (hact >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) regmap_write(lt8619c->reg_map, 0x64, hact & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) regmap_write(lt8619c->reg_map, 0x65, (htotal >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) regmap_write(lt8619c->reg_map, 0x66, htotal & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) regmap_write(lt8619c->reg_map, 0x67, v_offset & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) regmap_write(lt8619c->reg_map, 0x68, v_blank & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) regmap_write(lt8619c->reg_map, 0x69, (vact >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) regmap_write(lt8619c->reg_map, 0x6a, vact & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) regmap_write(lt8619c->reg_map, 0x6b, (vtotal >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) regmap_write(lt8619c->reg_map, 0x6c, vtotal & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static void lt8619c_power_on(struct lt8619c *lt8619c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (lt8619c->power_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) gpiod_set_value(lt8619c->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (lt8619c->reset_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) gpiod_set_value(lt8619c->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) usleep_range(100*1000, 110*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) gpiod_set_value(lt8619c->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) usleep_range(50*1000, 50*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static void lt8619c_wait_for_signal_stable(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) for (i = 0; i < WAIT_MAX_TIMES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) usleep_range(100*1000, 110*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) regmap_read(lt8619c->reg_map, 0x43, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (val & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (val & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) v4l2_info(sd, "tmds clk det success, wait cnt:%d!\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) v4l2_err(sd, "tmds clk det failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) for (i = 0; i < WAIT_MAX_TIMES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) usleep_range(100*1000, 110*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) regmap_read(lt8619c->reg_map, 0x13, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (val & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (val & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) v4l2_info(sd, "Hsync stable, wait cnt:%d!\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) v4l2_err(sd, "Hsync unstable!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* reset HDMI RX logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) regmap_write(lt8619c->reg_map, 0x09, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) usleep_range(10*1000, 11*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) regmap_write(lt8619c->reg_map, 0x09, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) usleep_range(100*1000, 110*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* reset video check logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) regmap_write(lt8619c->reg_map, 0x0c, 0xfb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) usleep_range(10*1000, 11*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) regmap_write(lt8619c->reg_map, 0x0c, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) usleep_range(100*1000, 110*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static void LVDSPLL_Lock_Det(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) regmap_write(lt8619c->reg_map, 0x0e, 0xfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) usleep_range(5*1000, 5*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) regmap_write(lt8619c->reg_map, 0x0e, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) usleep_range(100*1000, 100*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) regmap_read(lt8619c->reg_map, 0x87, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) while ((val & 0x20) == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) regmap_write(lt8619c->reg_map, 0x0e, 0xfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) usleep_range(5*1000, 5*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) regmap_write(lt8619c->reg_map, 0x0e, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) regmap_read(lt8619c->reg_map, 0x87, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) temp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (temp > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) v4l2_err(sd, "lvds pll lock det failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static void LT8619C_phase_config(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 i, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) int start = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) int end = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) u32 bt_clk_lag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) regmap_read(lt8619c->reg_map, 0x87, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) while ((val & 0x20) == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) regmap_write(lt8619c->reg_map, 0x0e, 0xfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) usleep_range(5*1000, 5*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) regmap_write(lt8619c->reg_map, 0x0e, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) regmap_write(lt8619c->reg_map, 0x0a, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) usleep_range(5*1000, 5*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) regmap_write(lt8619c->reg_map, 0x0a, 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) usleep_range(100*1000, 100*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) regmap_read(lt8619c->reg_map, 0x87, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) for (i = 0; i < ARRAY_SIZE(phase_num); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) regmap_write(lt8619c->reg_map, 0xa2, phase_num[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) usleep_range(50*1000, 50*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) regmap_read(lt8619c->reg_map, 0x91, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (val == 0x05) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) bt_clk_lag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) } else if (val == 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (start == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) start = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) end = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) v4l2_info(sd, "%s: BT_clk_lag:%d, start:%d, end:%d!\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) bt_clk_lag, start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (bt_clk_lag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) regmap_write(lt8619c->reg_map, 0xa2, phase_num[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if ((start != -1) && (end != -1) && (end >= start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) regmap_write(lt8619c->reg_map, 0xa2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) phase_num[start + (end - start) / 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) regmap_write(lt8619c->reg_map, 0xa2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) phase_num[ARRAY_SIZE(phase_num) - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* Turn on BT output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) regmap_write(lt8619c->reg_map, 0xa8, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static void sync_polarity_config(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u32 val, adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (lt8619c->bt_tx_sync_pol == BT_TX_SYNC_POSITIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) v4l2_info(sd, "%s: cfg h_vsync pol: POSITIVE\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) regmap_update_bits(lt8619c->reg_map, 0x60, SYNC_POL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) BT_TX_SYNC_POSITIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) regmap_read(lt8619c->reg_map, 0x17, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) regmap_read(lt8619c->reg_map, 0x05, &adj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if ((val & RGOD_VID_VSPOL) != RGOD_VID_VSPOL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) adj ^= RGD_VS_POL_ADJ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) regmap_update_bits(lt8619c->reg_map, 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) RGD_VS_POL_ADJ_MASK, adj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if ((val & RGOD_VID_HSPOL) != RGOD_VID_HSPOL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) adj ^= RGD_HS_POL_ADJ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) regmap_update_bits(lt8619c->reg_map, 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) RGD_HS_POL_ADJ_MASK, adj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) v4l2_info(sd, "%s: cfg h_vsync pol: NEGATIVE\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) regmap_update_bits(lt8619c->reg_map, 0x60, SYNC_POL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) BT_TX_SYNC_NEGATIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) regmap_read(lt8619c->reg_map, 0x17, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) regmap_read(lt8619c->reg_map, 0x05, &adj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if ((val & RGOD_VID_VSPOL) == RGOD_VID_VSPOL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) adj ^= RGD_VS_POL_ADJ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) regmap_update_bits(lt8619c->reg_map, 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) RGD_VS_POL_ADJ_MASK, adj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if ((val & RGOD_VID_HSPOL) == RGOD_VID_HSPOL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) adj ^= RGD_HS_POL_ADJ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) regmap_update_bits(lt8619c->reg_map, 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) RGD_HS_POL_ADJ_MASK, adj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static void lt8619c_yuv_config(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u32 val, colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) sync_polarity_config(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* softrest BT TX module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) regmap_update_bits(lt8619c->reg_map, 0x0d, BIT(1) | BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) usleep_range(10*1000, 10*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) regmap_update_bits(lt8619c->reg_map, 0x0d, BIT(1) | BIT(0), BIT(1) | BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* ColorSpace convert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) regmap_write(lt8619c->reg_map, BANK_REG, BANK_80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) regmap_read(lt8619c->reg_map, 0x71, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) colorspace = (val & 0x60) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (colorspace == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* YCbCr444 convert YCbCr422 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) regmap_write(lt8619c->reg_map, 0x07, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) regmap_write(lt8619c->reg_map, 0x52, 0x02 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) lt8619c->cp_convert_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) v4l2_info(sd, "%s: colorspace: yuv444\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) } else if (colorspace == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* yuv422 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) regmap_write(lt8619c->reg_map, 0x07, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) regmap_write(lt8619c->reg_map, 0x52, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) v4l2_info(sd, "%s: colorspace: yuv222\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* RGB convert YCbCr422 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) regmap_write(lt8619c->reg_map, 0x07, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) regmap_write(lt8619c->reg_map, 0x52, 0x0a +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) lt8619c->cp_convert_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) v4l2_info(sd, "%s: colorspace: RGB\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) lt8619c_set_bt_tx_timing(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) regmap_write(lt8619c->reg_map, 0x6d, lt8619c->yc_swap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) regmap_write(lt8619c->reg_map, 0x6e, lt8619c->yuv_colordepth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* LVDS PLL soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) regmap_update_bits(lt8619c->reg_map, 0x0e, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) usleep_range(50*1000, 50*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) regmap_update_bits(lt8619c->reg_map, 0x0e, BIT(1), BIT(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* BT TX controller and afifo soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) regmap_update_bits(lt8619c->reg_map, 0x0d, BIT(1) | BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) usleep_range(50*1000, 50*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) regmap_update_bits(lt8619c->reg_map, 0x0d, BIT(1) | BIT(0), BIT(1) | BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static void lt8619c_initial_setup(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static struct v4l2_dv_timings default_timing =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) V4L2_DV_BT_CEA_640X480P59_94;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct v4l2_subdev_edid def_edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) def_edid.pad = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) def_edid.start_block = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) def_edid.blocks = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) def_edid.edid = edid_init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) lt8619c->enable_hdcp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) lt8619c->cp_convert_mode = CP_CONVERT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) lt8619c->yuv_colordepth = YUV_COLORDEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) lt8619c->bt_tx_sync_pol = BT_TX_SYNC_POL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (lt8619c->yuv_output_mode == BT656_OUTPUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) lt8619c->yc_swap = YC_SWAP_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) lt8619c->BT656_double_clk_en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) lt8619c->yc_swap = YC_SWAP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) lt8619c->BT656_double_clk_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) lt8619c_set_hpd(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) lt8619c_write_edid(sd, &def_edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) lt8619c->edid_blocks_written = def_edid.blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) lt8619c_set_hdmi_hdcp(sd, lt8619c->enable_hdcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) lt8619c_mode_config(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (tx_5v_power_present(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) lt8619c_set_hpd(sd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) lt8619c_config_all(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* monitor resolution after 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) schedule_delayed_work(<8619c->delayed_work_monitor_resolution,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) HZ / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) lt8619c_s_dv_timings(sd, &default_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) v4l2_dbg(1, debug, sd, "%s: init ok\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static void lt8619c_format_change(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) const struct v4l2_event lt8619c_ev_fmt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .type = V4L2_EVENT_SOURCE_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) lt8619c_get_detected_timings(sd, &timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (!v4l2_match_dv_timings(<8619c->timings, &timings, 0, false)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* automatically set timing rather than set by userspace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) lt8619c_s_dv_timings(sd, &timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) v4l2_print_dv_timings(sd->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) "lt8619c_format_change: New format: ", &timings, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (sd->devnode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) v4l2_subdev_notify_event(sd, <8619c_ev_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static bool lt8619c_timing_changed(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct v4l2_bt_timings *new_bt = &timings->bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct v4l2_bt_timings *bt = <8619c->timings.bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if ((bt->width != new_bt->width) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) (bt->height != new_bt->height) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) (abs(bt->hfrontporch - new_bt->hfrontporch) > 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) (abs(bt->hsync - new_bt->hsync) > 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) (abs(bt->hbackporch - new_bt->hbackporch) > 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) (abs(bt->vfrontporch - new_bt->vfrontporch) > 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) (abs(bt->vsync - new_bt->vsync) > 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) (abs(bt->vbackporch - new_bt->vbackporch) > 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) (abs(bt->pixelclock - new_bt->pixelclock) > 5000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) v4l2_info(sd, "%s: timing changed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static bool lt8619c_rcv_supported_res(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u32 hact, vact, htotal, vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct v4l2_bt_timings *bt = &timings->bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) hact = bt->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) vact = bt->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) htotal = bt->hsync + bt->hbackporch + hact + bt->hfrontporch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) vtotal = bt->vsync + bt->vbackporch + vact + bt->vfrontporch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if ((supported_modes[i].width == hact) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) (supported_modes[i].height == vact)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) v4l2_err(sd, "%s do not support res act: %dx%d, total: %dx%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) __func__, hact, vact, htotal, vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (bt->pixelclock < 25000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) v4l2_err(sd, "%s pixclk: %llu, err!\n", __func__, bt->pixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static int lt8619c_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct v4l2_event_subscription *sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) switch (sub->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) case V4L2_EVENT_SOURCE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) case V4L2_EVENT_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static int lt8619c_g_input_status(struct v4l2_subdev *sd, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static int lt8619c_s_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (!timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) v4l2_print_dv_timings(sd->name, "lt8619c_s_dv_timings: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) timings, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (v4l2_match_dv_timings(<8619c->timings, timings, 0, false)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!v4l2_valid_dv_timings(timings, <8619c_timings_cap, NULL, NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) lt8619c->timings = *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static int lt8619c_g_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) *timings = lt8619c->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static int lt8619c_enum_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct v4l2_enum_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (timings->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return v4l2_enum_dv_timings_cap(timings, <8619c_timings_cap, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static int lt8619c_query_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) mutex_lock(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ret = lt8619c_get_detected_timings(sd, timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) mutex_unlock(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) v4l2_print_dv_timings(sd->name, "lt8619c_query_dv_timings: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) timings, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (!v4l2_valid_dv_timings(timings, <8619c_timings_cap, NULL, NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static int lt8619c_dv_timings_cap(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct v4l2_dv_timings_cap *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (cap->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) *cap = lt8619c_timings_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static int lt8619c_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct v4l2_mbus_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) cfg->type = V4L2_MBUS_BT656;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (lt8619c->clk_ddrmode_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) cfg->flags = RKMODULE_CAMERA_BT656_CHANNELS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) V4L2_MBUS_PCLK_SAMPLE_RISING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) V4L2_MBUS_PCLK_SAMPLE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) cfg->flags = RKMODULE_CAMERA_BT656_CHANNELS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) V4L2_MBUS_PCLK_SAMPLE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static int lt8619c_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) enable_stream(sd, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static int lt8619c_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) switch (code->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) code->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static int lt8619c_get_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct lt8619c *lt8619c = container_of(ctrl->handler, struct lt8619c, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct v4l2_subdev *sd = &(lt8619c->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (ctrl->id == V4L2_CID_DV_RX_POWER_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ret = tx_5v_power_present(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) *ctrl->p_new.p_s32 = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static int lt8619c_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static int lt8619c_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static int lt8619c_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct v4l2_bt_timings *bt = &(lt8619c->timings.bt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) mutex_lock(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) format->format.code = lt8619c->mbus_fmt_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) format->format.width = lt8619c->timings.bt.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) format->format.height = lt8619c->timings.bt.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) format->format.colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (bt->interlaced == V4L2_DV_INTERLACED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) format->format.field = V4L2_FIELD_INTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) format->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) mutex_unlock(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) v4l2_dbg(2, debug, sd, "fmt code:%d, w:%d, h:%d, field:%s, cosp:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) format->format.code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) format->format.width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) format->format.height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) (format->format.field == V4L2_FIELD_INTERLACED) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) "I" : "P",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) format->format.colorspace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static int lt8619c_get_reso_dist(const struct lt8619c_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static const struct lt8619c_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) lt8619c_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) dist = lt8619c_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static int lt8619c_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) const struct lt8619c_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /* is overwritten by get_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) u32 code = format->format.code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) int ret = lt8619c_get_fmt(sd, cfg, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) format->format.code = code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) switch (code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (format->which == V4L2_SUBDEV_FORMAT_TRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) lt8619c->mbus_fmt_code = format->format.code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) mode = lt8619c_find_best_fit(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) lt8619c->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static int lt8619c_g_edid(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) struct v4l2_subdev_edid *edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) memset(edid->reserved, 0, sizeof(edid->reserved));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (edid->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (edid->start_block == 0 && edid->blocks == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) edid->blocks = lt8619c->edid_blocks_written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (lt8619c->edid_blocks_written == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (edid->start_block >= lt8619c->edid_blocks_written ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) edid->blocks == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (edid->start_block + edid->blocks > lt8619c->edid_blocks_written)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) edid->blocks = lt8619c->edid_blocks_written - edid->start_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) lt8619c_read_edid(sd, edid->edid, edid->blocks * EDID_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static int lt8619c_s_edid(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct v4l2_subdev_edid *edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) __func__, edid->pad, edid->start_block, edid->blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) memset(edid->reserved, 0, sizeof(edid->reserved));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (edid->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (edid->start_block != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) edid->blocks = EDID_NUM_BLOCKS_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) lt8619c_set_hpd(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (edid->blocks == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) lt8619c->edid_blocks_written = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) lt8619c_write_edid(sd, edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) lt8619c->edid_blocks_written = edid->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (tx_5v_power_present(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) lt8619c_set_hpd(sd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) static int lt8619c_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) const struct lt8619c_mode *mode = lt8619c->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) mutex_lock(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) mutex_unlock(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static int lt8619c_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (lt8619c->yuv_output_mode == BT656_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) *std = V4L2_STD_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) *std = V4L2_STD_ATSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static void lt8619c_get_module_inf(struct lt8619c *lt8619c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) strscpy(inf->base.sensor, LT8619C_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) strscpy(inf->base.module, lt8619c->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) strscpy(inf->base.lens, lt8619c->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static int lt8619c_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) struct v4l2_bt_timings *bt = &(lt8619c->timings.bt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) const struct lt8619c_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) mutex_lock(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) try_fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (bt->interlaced == V4L2_DV_INTERLACED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) try_fmt->field = V4L2_FIELD_INTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) mutex_unlock(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static long lt8619c_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) lt8619c_get_module_inf(lt8619c, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static long lt8619c_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) ret = lt8619c_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static const struct v4l2_ctrl_ops lt8619c_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .g_volatile_ctrl = lt8619c_get_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static const struct v4l2_subdev_internal_ops lt8619c_subdev_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .open = lt8619c_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static const struct v4l2_subdev_core_ops lt8619c_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .subscribe_event = lt8619c_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .ioctl = lt8619c_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .compat_ioctl32 = lt8619c_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static const struct v4l2_subdev_video_ops lt8619c_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .g_input_status = lt8619c_g_input_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .s_dv_timings = lt8619c_s_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .g_dv_timings = lt8619c_g_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .query_dv_timings = lt8619c_query_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .s_stream = lt8619c_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .g_frame_interval = lt8619c_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .querystd = lt8619c_querystd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static const struct v4l2_subdev_pad_ops lt8619c_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .enum_mbus_code = lt8619c_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .enum_frame_size = lt8619c_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .enum_frame_interval = lt8619c_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .set_fmt = lt8619c_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .get_fmt = lt8619c_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .get_edid = lt8619c_g_edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .set_edid = lt8619c_s_edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .enum_dv_timings = lt8619c_enum_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .dv_timings_cap = lt8619c_dv_timings_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .get_mbus_config = lt8619c_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static const struct v4l2_subdev_ops lt8619c_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .core = <8619c_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .video = <8619c_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .pad = <8619c_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static irqreturn_t plugin_detect_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) struct lt8619c *lt8619c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct v4l2_subdev *sd = <8619c->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) /* enable hpd after 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) schedule_delayed_work(<8619c->delayed_work_enable_hotplug, HZ / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) v4l2_dbg(2, debug, sd, "%s: plug change!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) tx_5v_power_present(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) static int lt8619c_parse_of(struct lt8619c *lt8619c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) struct device *dev = <8619c->i2c_client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) lt8619c->hpd_output_inverted = of_property_read_bool(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) "hpd-output-inverted");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) err = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) <8619c->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) err |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) <8619c->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) err |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) <8619c->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) err |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) <8619c->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) lt8619c->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (IS_ERR(lt8619c->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) err = clk_prepare_enable(lt8619c->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) dev_err(dev, "Failed! to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) lt8619c->power_gpio = devm_gpiod_get_optional(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (IS_ERR(lt8619c->power_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) dev_err(dev, "failed to get power gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) err = PTR_ERR(lt8619c->power_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) lt8619c->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (IS_ERR(lt8619c->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) dev_err(dev, "failed to get reset gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) err = PTR_ERR(lt8619c->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) lt8619c->plugin_det_gpio = devm_gpiod_get_optional(dev, "plugin-det",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (IS_ERR(lt8619c->plugin_det_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) dev_err(dev, "failed to get plugin_det gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) err = PTR_ERR(lt8619c->plugin_det_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (of_property_read_u32(node, RK_CAMERA_MODULE_DUAL_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) <8619c->clk_ddrmode_en)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) lt8619c->clk_ddrmode_en = LT8619C_DEFAULT_DUAL_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) dev_warn(dev, "can not get module %s from dts, use default(%d)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) RK_CAMERA_MODULE_DUAL_EDGE, LT8619C_DEFAULT_DUAL_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) dev_info(dev, "get module %s from dts, dual_edge(%d)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) RK_CAMERA_MODULE_DUAL_EDGE, lt8619c->clk_ddrmode_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (of_property_read_u32(node, RK_CAMERA_MODULE_DVP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) <8619c->yuv_output_mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) lt8619c->yuv_output_mode = LT8619C_DEFAULT_DVP_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) dev_warn(dev, "can not get module %s from dts, use default(BT1120)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) RK_CAMERA_MODULE_DVP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) dev_info(dev, "get module %s from dts, dvp mode(%s)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) RK_CAMERA_MODULE_DVP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) (lt8619c->yuv_output_mode == BT656_OUTPUT) ? "BT656" : "BT1120");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) clk_disable_unprepare(lt8619c->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static int lt8619c_init_v4l2_ctrls(struct lt8619c *lt8619c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) sd = <8619c->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) ret = v4l2_ctrl_handler_init(<8619c->hdl, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) v4l2_ctrl_new_std(<8619c->hdl, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) 0, lt8619c_PIXEL_RATE, 1, lt8619c_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) lt8619c->detect_tx_5v_ctrl = v4l2_ctrl_new_std(<8619c->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) <8619c_ctrl_ops, V4L2_CID_DV_RX_POWER_PRESENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) 0, 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (lt8619c->detect_tx_5v_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) lt8619c->detect_tx_5v_ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (lt8619c->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) ret = lt8619c->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) v4l2_err(sd, "cfg v4l2 ctrls failed! ret:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) sd->ctrl_handler = <8619c->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (lt8619c_update_controls(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) v4l2_err(sd, "update v4l2 ctrls failed! ret:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) static int lt8619c_check_chip_id(struct lt8619c *lt8619c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) struct device *dev = <8619c->i2c_client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) u32 id_h, id_m, id_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) u32 chipid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) regmap_write(lt8619c->reg_map, BANK_REG, BANK_60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) ret = regmap_read(lt8619c->reg_map, CHIPID_REG_H, &id_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) ret |= regmap_read(lt8619c->reg_map, CHIPID_REG_M, &id_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) ret |= regmap_read(lt8619c->reg_map, CHIPID_REG_L, &id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) chipid = (id_h << 16) | (id_m << 8) | id_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) if (chipid != LT8619C_CHIPID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) "check chipid failed, read id:%#x, we expect:%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) chipid, LT8619C_CHIPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) dev_err(dev, "%s i2c trans failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static const struct regmap_range lt8619c_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) regmap_reg_range(0x00, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static const struct regmap_access_table lt8619c_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .yes_ranges = lt8619c_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .n_yes_ranges = ARRAY_SIZE(lt8619c_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) static const struct regmap_config lt8619c_hdmirx_regmap_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .name = "lt8619c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .reg_stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .max_register = LT8619C_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .rd_table = <8619c_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static int lt8619c_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) struct lt8619c *lt8619c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) lt8619c = devm_kzalloc(dev, sizeof(*lt8619c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if (!lt8619c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) sd = <8619c->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) lt8619c->i2c_client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) lt8619c->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) lt8619c->mbus_fmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) err = lt8619c_parse_of(lt8619c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) mutex_init(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) err = lt8619c_init_v4l2_ctrls(lt8619c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) client->flags |= I2C_CLIENT_SCCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) v4l2_i2c_subdev_init(sd, client, <8619c_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) sd->internal_ops = <8619c_subdev_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) lt8619c->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) err = media_entity_pads_init(&sd->entity, 1, <8619c->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) v4l2_err(sd, "media entity init failed! err:%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) lt8619c->reg_map = devm_regmap_init_i2c(client, <8619c_hdmirx_regmap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) lt8619c_power_on(lt8619c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) err = lt8619c_check_chip_id(lt8619c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) if (strcmp(lt8619c->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) lt8619c->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) LT8619C_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) err = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) v4l2_err(sd, "v4l2 register subdev failed! err:%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) goto err_subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) INIT_DELAYED_WORK(<8619c->delayed_work_enable_hotplug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) lt8619c_delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) INIT_DELAYED_WORK(<8619c->delayed_work_monitor_resolution,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) lt8619c_delayed_work_monitor_resolution);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) lt8619c_initial_setup(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) lt8619c->plugin_irq = gpiod_to_irq(lt8619c->plugin_det_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if (lt8619c->plugin_irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) dev_err(dev, "failed to get plugin det irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) err = lt8619c->plugin_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) goto err_work_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) err = devm_request_threaded_irq(dev, lt8619c->plugin_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) plugin_detect_irq, IRQF_TRIGGER_FALLING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) IRQF_TRIGGER_RISING | IRQF_ONESHOT, "lt8619c", lt8619c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) dev_err(dev, "failed to register plugin det irq (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) goto err_work_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) v4l2_err(sd, "v4l2 ctrl handler setup failed! err:%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) goto err_work_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) err_work_queues:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) cancel_delayed_work(<8619c->delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) cancel_delayed_work(<8619c->delayed_work_monitor_resolution);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) err_subdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) err_hdl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) v4l2_ctrl_handler_free(<8619c->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) mutex_destroy(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) clk_disable_unprepare(lt8619c->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) static int lt8619c_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) struct lt8619c *lt8619c = to_lt8619c(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) cancel_delayed_work(<8619c->delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) cancel_delayed_work(<8619c->delayed_work_monitor_resolution);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) v4l2_ctrl_handler_free(<8619c->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) mutex_destroy(<8619c->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) clk_disable_unprepare(lt8619c->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) static const struct of_device_id lt8619c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) { .compatible = "lontium,lt8619c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) MODULE_DEVICE_TABLE(of, lt8619c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) static struct i2c_driver lt8619c_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .name = LT8619C_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .of_match_table = of_match_ptr(lt8619c_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .probe = <8619c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .remove = <8619c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) static int __init lt8619c_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) return i2c_add_driver(<8619c_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) static void __exit lt8619c_driver_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) i2c_del_driver(<8619c_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) device_initcall_sync(lt8619c_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) module_exit(lt8619c_driver_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) MODULE_DESCRIPTION("Lontium LT8619C HDMI to BT656/BT1120 bridge driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) MODULE_AUTHOR("Dingxian Wen <shawn.wen@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags