^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * lt7911uxc type-c/DP to MIPI CSI-2 bridge driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Jianwei Fan <jianwei.fan@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X01 support DPHY 4K60.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X02 add CPHY support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * V0.0X01.0X03 add rk3588 dcphy param.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * V0.0X01.0X04 add 5K60 support for CPHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/hdmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-controls_rockchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <media/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MODULE_PARM_DESC(debug, "debug level (0-3)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2C_MAX_XFER_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define POLL_INTERVAL_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LT7911UXC_LINK_FREQ_HIGH 1250000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LT7911UXC_LINK_FREQ_LOW 400000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LT7911UXC_LINK_FREQ_700M 700000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LT7911UXC_PIXEL_RATE 800000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LT7911UXC_CHIPID 0x0119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CHIPID_REGH 0xe101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CHIPID_REGL 0xe100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I2C_EN_REG 0xe0ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define I2C_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define I2C_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HTOTAL_H 0xe088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HTOTAL_L 0xe089
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HACT_H 0xe08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HACT_L 0xe08d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VTOTAL_H 0xe08a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VTOTAL_L 0xe08b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VACT_H 0xe08e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VACT_L 0xe08f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCLK_H 0xe085
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCLK_M 0xe086
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCLK_L 0xe087
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BYTE_PCLK_H 0xe092
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BYTE_PCLK_M 0xe093
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BYTE_PCLK_L 0xe094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AUDIO_FS_VALUE_H 0xe090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AUDIO_FS_VALUE_L 0xe091
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) //CPHY timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLK_ZERO_REG 0xf9a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLK_PRE_REG 0xf9a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLK_POST_REG 0xf9a9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HS_LPX_REG 0xf9a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HS_PREP_REG 0xf9a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HS_TRAIL 0xf9a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HS_RQST_PRE_REG 0xf98a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define STREAM_CTL 0xe0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ENABLE_STREAM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DISABLE_STREAM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LT7911UXC_NAME "LT7911UXC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) LT7911UXC_LINK_FREQ_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) LT7911UXC_LINK_FREQ_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) LT7911UXC_LINK_FREQ_700M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct lt7911uxc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct v4l2_fwnode_bus_mipi_csi2 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct i2c_client *i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct mutex confctl_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct v4l2_ctrl *detect_tx_5v_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct v4l2_ctrl *audio_sampling_rate_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct v4l2_ctrl *audio_present_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct delayed_work delayed_work_hotplug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct delayed_work delayed_work_res_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct gpio_desc *plugin_det_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct work_struct work_i2c_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const struct lt7911uxc_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const struct lt7911uxc_mode *support_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_fwnode_endpoint bus_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bool nosignal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) bool enable_hdcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) bool is_audio_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int plugin_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 mbus_fmt_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 audio_sampling_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct v4l2_dv_timings_cap lt7911uxc_timings_cap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .type = V4L2_DV_BT_656_1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .reserved = { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 800000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) V4L2_DV_BT_CAP_REDUCED_BLANKING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) V4L2_DV_BT_CAP_CUSTOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct lt7911uxc_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct rkmodule_csi_dphy_param rk3588_dcphy_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .vendor = PHY_VENDOR_SAMSUNG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .lp_vol_ref = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .lp_hys_sw = {0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .lp_escclk_pol_sel = {1, 0, 1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .skew_data_cal_clk = {0, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .clk_hs_term_sel = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .data_hs_term_sel = {2, 2, 2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .reserved = {0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct lt7911uxc_mode supported_modes_dphy[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .width = 3840,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .height = 2160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .hts_def = 4400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .vts_def = 2250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .hts_def = 2200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .vts_def = 1125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .height = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .hts_def = 1650,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .vts_def = 750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .width = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .height = 576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .denominator = 500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .hts_def = 864,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .vts_def = 625,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .width = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .hts_def = 858,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .vts_def = 525,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct lt7911uxc_mode supported_modes_cphy[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .width = 5120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .height = 2160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .hts_def = 5500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .vts_def = 2250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .mipi_freq_idx = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .width = 3840,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .height = 2160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .hts_def = 4400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .vts_def = 2250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .hts_def = 2200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .vts_def = 1125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .height = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .hts_def = 1650,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .vts_def = 750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .width = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .height = 576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .denominator = 500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .hts_def = 864,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .vts_def = 625,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .width = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .hts_def = 858,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .vts_def = 525,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void lt7911uxc_format_change(struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int lt7911uxc_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int lt7911uxc_s_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct v4l2_dv_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static inline struct lt7911uxc *to_lt7911uxc(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return container_of(sd, struct lt7911uxc, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct i2c_client *client = lt7911uxc->i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u8 buf[2] = { 0xFF, reg >> 8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u8 reg_addr = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct i2c_msg msgs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) msgs[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) msgs[1].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) msgs[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) msgs[1].buf = ®_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) msgs[2].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) msgs[2].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) msgs[2].len = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) msgs[2].buf = values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (err != ARRAY_SIZE(msgs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) __func__, reg, client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (!debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) switch (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) v4l2_info(sd, "I2C read 0x%04x = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) reg, values[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) v4l2_info(sd, "I2C read 0x%04x = 0x%02x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) reg, values[1], values[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) v4l2_info(sd, "I2C read 0x%04x = 0x%02x%02x%02x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) reg, values[3], values[2], values[1], values[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) v4l2_info(sd, "I2C read %d bytes from address 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) n, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct i2c_client *client = lt7911uxc->i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u8 data[I2C_MAX_XFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u8 buf[2] = { 0xFF, reg >> 8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if ((1 + n) > I2C_MAX_XFER_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) n = I2C_MAX_XFER_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) reg, 1 + n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) msgs[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) msgs[1].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) msgs[1].len = 1 + n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) msgs[1].buf = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) data[0] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) for (i = 0; i < n; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) data[1 + i] = values[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) __func__, reg, client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (!debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) switch (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) v4l2_info(sd, "I2C write 0x%04x = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) reg, data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) reg, data[2], data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) reg, data[4], data[3], data[2], data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) n, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) i2c_rd(sd, reg, (u8 __force *)&val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) i2c_wr(sd, reg, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void lt7911uxc_i2c_enable(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) i2c_wr8(sd, I2C_EN_REG, I2C_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void lt7911uxc_i2c_disable(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) i2c_wr8(sd, I2C_EN_REG, I2C_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) bool ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int val, i, cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* if not use plugin det gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (!lt7911uxc->plugin_det_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) val = gpiod_get_value(lt7911uxc->plugin_det_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (val > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) usleep_range(500, 600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = (cnt >= 3) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) v4l2_dbg(1, debug, sd, "%s: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static inline bool no_signal(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) v4l2_dbg(1, debug, sd, "%s no signal:%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) lt7911uxc->nosignal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return lt7911uxc->nosignal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static inline bool audio_present(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return lt7911uxc->is_audio_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int get_audio_sampling_rate(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const int code_to_rate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (no_signal(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return code_to_rate[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static inline unsigned int fps_calc(const struct v4l2_bt_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return DIV_ROUND_CLOSEST((unsigned int)t->pixelclock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static bool lt7911uxc_rcv_supported_res(struct v4l2_subdev *sd, u32 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) for (i = 0; i < lt7911uxc->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if ((lt7911uxc->support_modes[i].width == width) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) (lt7911uxc->support_modes[i].height == height)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (i == lt7911uxc->cfg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) v4l2_err(sd, "%s do not support res wxh: %dx%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) width, height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int lt7911uxc_get_detected_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct v4l2_bt_timings *bt = &timings->bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u32 hact, vact, htotal, vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u32 pixel_clock, fps, halt_pix_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u8 clk_h, clk_m, clk_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 val_h, val_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 byte_clk, mipi_clk, mipi_data_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) memset(timings, 0, sizeof(struct v4l2_dv_timings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) clk_h = i2c_rd8(sd, PCLK_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) clk_m = i2c_rd8(sd, PCLK_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) clk_l = i2c_rd8(sd, PCLK_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) halt_pix_clk = ((clk_h << 16) | (clk_m << 8) | clk_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pixel_clock = halt_pix_clk * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) clk_h = i2c_rd8(sd, BYTE_PCLK_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) clk_m = i2c_rd8(sd, BYTE_PCLK_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) clk_l = i2c_rd8(sd, BYTE_PCLK_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) byte_clk = ((clk_h << 16) | (clk_m << 8) | clk_l) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mipi_clk = byte_clk * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mipi_data_rate = byte_clk * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) val_h = i2c_rd8(sd, HTOTAL_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) val_l = i2c_rd8(sd, HTOTAL_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) htotal = ((val_h << 8) | val_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) val_h = i2c_rd8(sd, VTOTAL_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) val_l = i2c_rd8(sd, VTOTAL_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) vtotal = (val_h << 8) | val_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) val_h = i2c_rd8(sd, HACT_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) val_l = i2c_rd8(sd, HACT_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) hact = ((val_h << 8) | val_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) val_h = i2c_rd8(sd, VACT_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) val_l = i2c_rd8(sd, VACT_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) vact = (val_h << 8) | val_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!lt7911uxc_rcv_supported_res(sd, hact, vact)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) lt7911uxc->nosignal = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) v4l2_err(sd, "%s: rcv err res, return no signal!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) lt7911uxc->nosignal = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) lt7911uxc->is_audio_present = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) timings->type = V4L2_DV_BT_656_1120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) bt->interlaced = V4L2_DV_PROGRESSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) bt->width = hact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) bt->height = vact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) bt->pixelclock = pixel_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) fps = pixel_clock / (htotal * vtotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) v4l2_info(sd, "act:%dx%d, total:%dx%d, pixclk:%d, fps:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) hact, vact, htotal, vtotal, pixel_clock, fps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) v4l2_info(sd, "byte_clk:%d, mipi_clk:%d, mipi_data_rate:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) byte_clk, mipi_clk, mipi_data_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) v4l2_info(sd, "inerlaced:%d\n", bt->interlaced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static void lt7911uxc_delayed_work_hotplug(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct delayed_work *dwork = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct lt7911uxc *lt7911uxc = container_of(dwork,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct lt7911uxc, delayed_work_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct v4l2_subdev *sd = <7911uxc->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) lt7911uxc_s_ctrl_detect_tx_5v(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static void lt7911uxc_delayed_work_res_change(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct delayed_work *dwork = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct lt7911uxc *lt7911uxc = container_of(dwork,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct lt7911uxc, delayed_work_res_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct v4l2_subdev *sd = <7911uxc->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) lt7911uxc_format_change(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int lt7911uxc_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return v4l2_ctrl_s_ctrl(lt7911uxc->detect_tx_5v_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) tx_5v_power_present(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int lt7911uxc_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return v4l2_ctrl_s_ctrl(lt7911uxc->audio_sampling_rate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) get_audio_sampling_rate(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int lt7911uxc_s_ctrl_audio_present(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return v4l2_ctrl_s_ctrl(lt7911uxc->audio_present_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) audio_present(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int lt7911uxc_update_controls(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret |= lt7911uxc_s_ctrl_detect_tx_5v(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ret |= lt7911uxc_s_ctrl_audio_sampling_rate(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret |= lt7911uxc_s_ctrl_audio_present(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static void lt7911uxc_cphy_timing_config(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (lt7911uxc->bus_cfg.bus_type == V4L2_MBUS_CSI2_CPHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) lt7911uxc_i2c_enable(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) while (i2c_rd8(sd, HS_RQST_PRE_REG) != 0x3c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) i2c_wr8(sd, HS_RQST_PRE_REG, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) usleep_range(500, 600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) // i2c_wr8(sd, HS_TRAIL, 0x0b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) lt7911uxc_i2c_disable(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) v4l2_dbg(1, debug, sd, "%s config timing succeed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static bool lt7911uxc_match_timings(const struct v4l2_dv_timings *t1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) const struct v4l2_dv_timings *t2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (t1->type != t2->type || t1->type != V4L2_DV_BT_656_1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (t1->bt.width == t2->bt.width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) t1->bt.height == t2->bt.height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) t1->bt.interlaced == t2->bt.interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) lt7911uxc_cphy_timing_config(<7911uxc->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) i2c_wr8(<7911uxc->sd, STREAM_CTL, ENABLE_STREAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) i2c_wr8(<7911uxc->sd, STREAM_CTL, DISABLE_STREAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) v4l2_dbg(2, debug, sd, "%s: %sable\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) __func__, enable ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static void lt7911uxc_format_change(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) const struct v4l2_event lt7911uxc_ev_fmt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .type = V4L2_EVENT_SOURCE_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (lt7911uxc_get_detected_timings(sd, &timings)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) v4l2_dbg(1, debug, sd, "%s: No signal\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!lt7911uxc_match_timings(<7911uxc->timings, &timings)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* automatically set timing rather than set by user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) lt7911uxc_s_dv_timings(sd, &timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) v4l2_print_dv_timings(sd->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) "Format_change: New format: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) &timings, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (sd->devnode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) v4l2_subdev_notify_event(sd, <7911uxc_ev_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int lt7911uxc_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) schedule_delayed_work(<7911uxc->delayed_work_res_change, HZ / 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static irqreturn_t lt7911uxc_res_change_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct lt7911uxc *lt7911uxc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) bool handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) lt7911uxc_isr(<7911uxc->sd, 0, &handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return handled ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static irqreturn_t plugin_detect_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct lt7911uxc *lt7911uxc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* control hpd output level after 25ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) schedule_delayed_work(<7911uxc->delayed_work_hotplug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) HZ / 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static void lt7911uxc_irq_poll_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct lt7911uxc *lt7911uxc = from_timer(lt7911uxc, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) schedule_work(<7911uxc->work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) mod_timer(<7911uxc->timer, jiffies + msecs_to_jiffies(POLL_INTERVAL_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static void lt7911uxc_work_i2c_poll(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct lt7911uxc *lt7911uxc = container_of(work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct lt7911uxc, work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct v4l2_subdev *sd = <7911uxc->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) lt7911uxc_format_change(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static int lt7911uxc_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct v4l2_event_subscription *sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) switch (sub->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) case V4L2_EVENT_SOURCE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) case V4L2_EVENT_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int lt7911uxc_g_input_status(struct v4l2_subdev *sd, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static int lt7911uxc_s_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (!timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) v4l2_print_dv_timings(sd->name, "s_dv_timings: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) timings, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (lt7911uxc_match_timings(<7911uxc->timings, timings)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (!v4l2_valid_dv_timings(timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) <7911uxc_timings_cap, NULL, NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) lt7911uxc->timings = *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int lt7911uxc_g_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) *timings = lt7911uxc->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int lt7911uxc_enum_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct v4l2_enum_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (timings->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return v4l2_enum_dv_timings_cap(timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) <7911uxc_timings_cap, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static int lt7911uxc_query_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) *timings = lt7911uxc->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) v4l2_print_dv_timings(sd->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) "query_dv_timings: ", timings, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (!v4l2_valid_dv_timings(timings, <7911uxc_timings_cap, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) v4l2_dbg(1, debug, sd, "%s: timings out of range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int lt7911uxc_dv_timings_cap(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct v4l2_dv_timings_cap *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (cap->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) *cap = lt7911uxc_timings_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static int lt7911uxc_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) unsigned int pad, struct v4l2_mbus_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 lane_num = lt7911uxc->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) val = 1 << (lane_num - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) cfg->type = lt7911uxc->bus_cfg.bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) cfg->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static int lt7911uxc_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) enable_stream(sd, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int lt7911uxc_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) switch (code->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) code->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static int lt7911uxc_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (fse->index >= lt7911uxc->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) fse->min_width = lt7911uxc->support_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) fse->max_width = lt7911uxc->support_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) fse->max_height = lt7911uxc->support_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) fse->min_height = lt7911uxc->support_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static int lt7911uxc_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) mutex_lock(<7911uxc->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) format->format.code = lt7911uxc->mbus_fmt_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) format->format.width = lt7911uxc->timings.bt.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) format->format.height = lt7911uxc->timings.bt.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) format->format.field =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) lt7911uxc->timings.bt.interlaced ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) format->format.colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) mutex_unlock(<7911uxc->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) v4l2_dbg(1, debug, sd, "%s: fmt code:%d, w:%d, h:%d, field code:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) __func__, format->format.code, format->format.width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) format->format.height, format->format.field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int lt7911uxc_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (fie->index >= lt7911uxc->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) fie->width = lt7911uxc->support_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) fie->height = lt7911uxc->support_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) fie->interval = lt7911uxc->support_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int lt7911uxc_get_reso_dist(const struct lt7911uxc_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static const struct lt7911uxc_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) lt7911uxc_find_best_fit(struct lt7911uxc *lt7911uxc, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) for (i = 0; i < lt7911uxc->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dist = lt7911uxc_get_reso_dist(<7911uxc->support_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return <7911uxc->support_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static int lt7911uxc_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) const struct lt7911uxc_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* is overwritten by get_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) u32 code = format->format.code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) int ret = lt7911uxc_get_fmt(sd, cfg, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) format->format.code = code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) switch (code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (format->which == V4L2_SUBDEV_FORMAT_TRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) lt7911uxc->mbus_fmt_code = format->format.code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) mode = lt7911uxc_find_best_fit(lt7911uxc, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) lt7911uxc->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) __v4l2_ctrl_s_ctrl_int64(lt7911uxc->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) LT7911UXC_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) __v4l2_ctrl_s_ctrl(lt7911uxc->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) dev_info(<7911uxc->i2c_client->dev, "%s: mode->mipi_freq_idx(%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) __func__, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static int lt7911uxc_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) const struct lt7911uxc_mode *mode = lt7911uxc->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) mutex_lock(<7911uxc->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) mutex_unlock(<7911uxc->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static void lt7911uxc_get_module_inf(struct lt7911uxc *lt7911uxc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) strscpy(inf->base.sensor, LT7911UXC_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) strscpy(inf->base.module, lt7911uxc->module_name, sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) strscpy(inf->base.lens, lt7911uxc->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static long lt7911uxc_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct rkmodule_csi_dphy_param *dphy_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) lt7911uxc_get_module_inf(lt7911uxc, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) case RKMODULE_GET_HDMI_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) *(int *)arg = RKMODULE_HDMIIN_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) case RKMODULE_SET_CSI_DPHY_PARAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dphy_param = (struct rkmodule_csi_dphy_param *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (dphy_param->vendor == rk3588_dcphy_param.vendor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) rk3588_dcphy_param = *dphy_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dev_dbg(<7911uxc->i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) "sensor set dphy param\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) case RKMODULE_GET_CSI_DPHY_PARAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dphy_param = (struct rkmodule_csi_dphy_param *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (dphy_param->vendor == rk3588_dcphy_param.vendor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) *dphy_param = rk3588_dcphy_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) dev_dbg(<7911uxc->i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) "sensor get dphy param\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static int lt7911uxc_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) mutex_lock(<7911uxc->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (lt7911uxc->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) lt7911uxc->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) lt7911uxc->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) mutex_unlock(<7911uxc->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static long lt7911uxc_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) int *seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct rkmodule_csi_dphy_param *dphy_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) ret = lt7911uxc_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) case RKMODULE_GET_HDMI_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) seq = kzalloc(sizeof(*seq), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (!seq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ret = lt7911uxc_ioctl(sd, cmd, seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) ret = copy_to_user(up, seq, sizeof(*seq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) kfree(seq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) case RKMODULE_SET_CSI_DPHY_PARAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (!dphy_param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ret = copy_from_user(dphy_param, up, sizeof(*dphy_param));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ret = lt7911uxc_ioctl(sd, cmd, dphy_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) kfree(dphy_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) case RKMODULE_GET_CSI_DPHY_PARAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (!dphy_param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) ret = lt7911uxc_ioctl(sd, cmd, dphy_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ret = copy_to_user(up, dphy_param, sizeof(*dphy_param));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) kfree(dphy_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static int lt7911uxc_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) const struct lt7911uxc_mode *def_mode = <7911uxc->support_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) mutex_lock(<7911uxc->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) try_fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) mutex_unlock(<7911uxc->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static const struct v4l2_subdev_internal_ops lt7911uxc_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .open = lt7911uxc_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static const struct v4l2_subdev_core_ops lt7911uxc_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .s_power = lt7911uxc_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .interrupt_service_routine = lt7911uxc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .subscribe_event = lt7911uxc_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .ioctl = lt7911uxc_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .compat_ioctl32 = lt7911uxc_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static const struct v4l2_subdev_video_ops lt7911uxc_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .g_input_status = lt7911uxc_g_input_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .s_dv_timings = lt7911uxc_s_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .g_dv_timings = lt7911uxc_g_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .query_dv_timings = lt7911uxc_query_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .s_stream = lt7911uxc_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .g_frame_interval = lt7911uxc_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static const struct v4l2_subdev_pad_ops lt7911uxc_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .enum_mbus_code = lt7911uxc_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .enum_frame_size = lt7911uxc_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .enum_frame_interval = lt7911uxc_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .set_fmt = lt7911uxc_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .get_fmt = lt7911uxc_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .enum_dv_timings = lt7911uxc_enum_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .dv_timings_cap = lt7911uxc_dv_timings_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .get_mbus_config = lt7911uxc_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static const struct v4l2_subdev_ops lt7911uxc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .core = <7911uxc_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .video = <7911uxc_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .pad = <7911uxc_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static const struct v4l2_ctrl_config lt7911uxc_ctrl_audio_sampling_rate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .id = RK_V4L2_CID_AUDIO_SAMPLING_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .name = "Audio sampling rate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .type = V4L2_CTRL_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .max = 768000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .def = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .flags = V4L2_CTRL_FLAG_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static const struct v4l2_ctrl_config lt7911uxc_ctrl_audio_present = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .id = RK_V4L2_CID_AUDIO_PRESENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .name = "Audio present",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .type = V4L2_CTRL_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .def = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .flags = V4L2_CTRL_FLAG_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static void lt7911uxc_reset(struct lt7911uxc *lt7911uxc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) gpiod_set_value(lt7911uxc->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) usleep_range(2000, 2100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) gpiod_set_value(lt7911uxc->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) usleep_range(120*1000, 121*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) gpiod_set_value(lt7911uxc->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) usleep_range(300*1000, 310*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static int lt7911uxc_init_v4l2_ctrls(struct lt7911uxc *lt7911uxc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) const struct lt7911uxc_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) mode = lt7911uxc->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) sd = <7911uxc->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ret = v4l2_ctrl_handler_init(<7911uxc->hdl, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) lt7911uxc->link_freq = v4l2_ctrl_new_int_menu(<7911uxc->hdl, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) ARRAY_SIZE(link_freq_menu_items) - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) lt7911uxc->pixel_rate = v4l2_ctrl_new_std(<7911uxc->hdl, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) 0, LT7911UXC_PIXEL_RATE, 1, LT7911UXC_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) lt7911uxc->detect_tx_5v_ctrl = v4l2_ctrl_new_std(<7911uxc->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) NULL, V4L2_CID_DV_RX_POWER_PRESENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) 0, 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) lt7911uxc->audio_sampling_rate_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) v4l2_ctrl_new_custom(<7911uxc->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) <7911uxc_ctrl_audio_sampling_rate, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) lt7911uxc->audio_present_ctrl = v4l2_ctrl_new_custom(<7911uxc->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) <7911uxc_ctrl_audio_present, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) sd->ctrl_handler = <7911uxc->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (lt7911uxc->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) ret = lt7911uxc->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) v4l2_err(sd, "cfg v4l2 ctrls failed! ret:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) __v4l2_ctrl_s_ctrl(lt7911uxc->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) __v4l2_ctrl_s_ctrl_int64(lt7911uxc->pixel_rate, LT7911UXC_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (lt7911uxc_update_controls(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) v4l2_err(sd, "update v4l2 ctrls failed! ret:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static int lt7911uxc_probe_of(struct lt7911uxc *lt7911uxc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) struct device *dev = <7911uxc->i2c_client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) struct device_node *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) <7911uxc->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) <7911uxc->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) <7911uxc->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) <7911uxc->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) lt7911uxc->power_gpio = devm_gpiod_get_optional(dev, "power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (IS_ERR(lt7911uxc->power_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) dev_err(dev, "failed to get power gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ret = PTR_ERR(lt7911uxc->power_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) lt7911uxc->reset_gpio = devm_gpiod_get_optional(dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (IS_ERR(lt7911uxc->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev_err(dev, "failed to get reset gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) ret = PTR_ERR(lt7911uxc->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) lt7911uxc->plugin_det_gpio = devm_gpiod_get_optional(dev, "plugin-det",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (IS_ERR(lt7911uxc->plugin_det_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) dev_err(dev, "failed to get plugin det gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) ret = PTR_ERR(lt7911uxc->plugin_det_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ep = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (!ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) dev_err(dev, "missing endpoint node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) <7911uxc->bus_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) dev_err(dev, "failed to parse endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) goto put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (lt7911uxc->bus_cfg.bus_type == V4L2_MBUS_CSI2_DPHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) lt7911uxc->support_modes = supported_modes_dphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) lt7911uxc->cfg_num = ARRAY_SIZE(supported_modes_dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) lt7911uxc->support_modes = supported_modes_cphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) lt7911uxc->cfg_num = ARRAY_SIZE(supported_modes_cphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) lt7911uxc->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (IS_ERR(lt7911uxc->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) dev_err(dev, "failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) goto put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) ret = clk_prepare_enable(lt7911uxc->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) dev_err(dev, "Failed! to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) goto put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) lt7911uxc->enable_hdcp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) gpiod_set_value(lt7911uxc->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) lt7911uxc_reset(lt7911uxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) of_node_put(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static inline int lt7911uxc_probe_of(struct lt7911uxc *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static int lt7911uxc_check_chip_id(struct lt7911uxc *lt7911uxc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct device *dev = <7911uxc->i2c_client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) struct v4l2_subdev *sd = <7911uxc->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) u8 id_h, id_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) u32 chipid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) lt7911uxc_i2c_enable(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) id_l = i2c_rd8(sd, CHIPID_REGL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) id_h = i2c_rd8(sd, CHIPID_REGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) lt7911uxc_i2c_disable(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) chipid = (id_h << 8) | id_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (chipid != LT7911UXC_CHIPID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) dev_err(dev, "chipid err, read:%#x, expect:%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) chipid, LT7911UXC_CHIPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) dev_info(dev, "check chipid ok, id:%#x", chipid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static int lt7911uxc_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct lt7911uxc *lt7911uxc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) lt7911uxc = devm_kzalloc(dev, sizeof(struct lt7911uxc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (!lt7911uxc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) sd = <7911uxc->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) lt7911uxc->i2c_client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) lt7911uxc->mbus_fmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) err = lt7911uxc_probe_of(lt7911uxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) v4l2_err(sd, "lt7911uxc_parse_of failed! err:%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) lt7911uxc->cur_mode = <7911uxc->support_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) err = lt7911uxc_check_chip_id(lt7911uxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) mutex_init(<7911uxc->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) err = lt7911uxc_init_v4l2_ctrls(lt7911uxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) goto err_free_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) client->flags |= I2C_CLIENT_SCCB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) v4l2_i2c_subdev_init(sd, client, <7911uxc_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) sd->internal_ops = <7911uxc_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) lt7911uxc->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) err = media_entity_pads_init(&sd->entity, 1, <7911uxc->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) v4l2_err(sd, "media entity init failed! err:%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) goto err_free_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (strcmp(lt7911uxc->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) lt7911uxc->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) LT7911UXC_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) err = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) v4l2_err(sd, "v4l2 register subdev failed! err:%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) INIT_DELAYED_WORK(<7911uxc->delayed_work_hotplug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) lt7911uxc_delayed_work_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) INIT_DELAYED_WORK(<7911uxc->delayed_work_res_change,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) lt7911uxc_delayed_work_res_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (lt7911uxc->i2c_client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) v4l2_dbg(1, debug, sd, "cfg lt7911uxc irq!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) err = devm_request_threaded_irq(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) lt7911uxc->i2c_client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) NULL, lt7911uxc_res_change_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) "lt7911uxc", lt7911uxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) v4l2_err(sd, "request irq failed! err:%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) goto err_work_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) v4l2_dbg(1, debug, sd, "no irq, cfg poll!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) INIT_WORK(<7911uxc->work_i2c_poll, lt7911uxc_work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) timer_setup(<7911uxc->timer, lt7911uxc_irq_poll_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) lt7911uxc->timer.expires = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) msecs_to_jiffies(POLL_INTERVAL_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) add_timer(<7911uxc->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) lt7911uxc->plugin_irq = gpiod_to_irq(lt7911uxc->plugin_det_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (lt7911uxc->plugin_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) dev_err(dev, "failed to get plugin det irq, maybe no use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) err = devm_request_threaded_irq(dev, lt7911uxc->plugin_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) plugin_detect_irq_handler, IRQF_TRIGGER_FALLING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) IRQF_TRIGGER_RISING | IRQF_ONESHOT, "lt7911uxc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) lt7911uxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dev_err(dev, "failed to register plugin det irq (%d), maybe no use\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) v4l2_err(sd, "v4l2 ctrl handler setup failed! err:%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) goto err_work_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) err_work_queues:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (!lt7911uxc->i2c_client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) flush_work(<7911uxc->work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) cancel_delayed_work(<7911uxc->delayed_work_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) cancel_delayed_work(<7911uxc->delayed_work_res_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) err_free_hdl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) v4l2_ctrl_handler_free(<7911uxc->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) mutex_destroy(<7911uxc->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static int lt7911uxc_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct lt7911uxc *lt7911uxc = to_lt7911uxc(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) if (!lt7911uxc->i2c_client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) del_timer_sync(<7911uxc->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) flush_work(<7911uxc->work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) cancel_delayed_work_sync(<7911uxc->delayed_work_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) cancel_delayed_work_sync(<7911uxc->delayed_work_res_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) v4l2_ctrl_handler_free(<7911uxc->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) mutex_destroy(<7911uxc->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) clk_disable_unprepare(lt7911uxc->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) static const struct of_device_id lt7911uxc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) { .compatible = "lontium,lt7911uxc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) MODULE_DEVICE_TABLE(of, lt7911uxc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static struct i2c_driver lt7911uxc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .name = LT7911UXC_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .of_match_table = of_match_ptr(lt7911uxc_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .probe = lt7911uxc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .remove = lt7911uxc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) static int __init lt7911uxc_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) return i2c_add_driver(<7911uxc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) static void __exit lt7911uxc_driver_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) i2c_del_driver(<7911uxc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) device_initcall_sync(lt7911uxc_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) module_exit(lt7911uxc_driver_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) MODULE_DESCRIPTION("Lontium lt7911uxc DP/type-c to CSI-2 bridge driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) MODULE_AUTHOR("Jianwei Fan <jianwei.fan@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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