Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: Dingxian Wen <shawn.wen@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _LT6911UXC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _LT6911UXC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define LT6911UXC_FW_VERSION	0x2005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define LT6911UXC_CHIPID	0x0417
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define I2C_ENABLE		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define I2C_DISABLE		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AD_LMTX_WRITE_CLK	0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RECEIVED_INT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) // -------------- regs ---------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define I2C_EN_REG		0x80EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CHIPID_H		0x8101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CHIPID_L		0x8100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FW_VER_A		0x86a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FW_VER_B		0x86a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FW_VER_C		0x86a9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FW_VER_D		0x86aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HTOTAL_H		0x867c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HTOTAL_L		0x867d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HACT_H			0x8680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HACT_L			0x8681
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VTOTAL_H		0x867a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VTOTAL_L		0x867b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VACT_H			0x867e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VACT_L			0x867f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HFP_H			0x8678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HFP_L			0x8679
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HS_H			0x8672
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HS_L			0x8673
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HBP_H			0x8676
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HBP_L			0x8677
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VBP			0x8674
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VFP			0x8675
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VS			0x8671
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HDMI_VERSION		0xb0a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TMDS_CLK_H		0x8750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TMDS_CLK_M		0x8751
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TMDS_CLK_L		0x8752
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MIPI_LANES		0x86a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FM1_DET_CLK_SRC_SEL	0x8540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FREQ_METER_H		0x8548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FREQ_METER_M		0x8549
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FREQ_METER_L		0x854a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define INT_COMPARE_REG		0x86a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define INT_STATUS_86A3		0x86a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define INT_STATUS_86A5		0x86a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AUDIO_IN_STATUS		0xb081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AUDIO_SAMPLE_RATAE_H	0xb0aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AUDIO_SAMPLE_RATAE_L	0xb0ab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif