^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Video Capture Driver (Video for Linux 1/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for the Matrox Marvel G200,G400 and Rainbow Runner-G series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This module is an interface to the KS0127 video decoder chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1999 Ryan Drake <stiletto@mediaone.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Modified and extended by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Mike Bernson <mike@mlb.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Gerard v.d. Horst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Leon van Stuivenberg <l.vanstuivenberg@chello.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Gernot Ziegler <gz@lysator.liu.se>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Version History:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * V1.0 Ryan Drake Initial version by Ryan Drake
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * V1.1 Gerard v.d. Horst Added some debugoutput, reset the video-standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "ks0127.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_DESCRIPTION("KS0127 video decoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_AUTHOR("Ryan Drake");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2C_KS0127_ADDON 0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2C_KS0127_ONBOARD 0xDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* ks0127 control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define KS_STAT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define KS_CMDA 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define KS_CMDB 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define KS_CMDC 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define KS_CMDD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define KS_HAVB 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define KS_HAVE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define KS_HS1B 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define KS_HS1E 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define KS_HS2B 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define KS_HS2E 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define KS_AGC 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define KS_HXTRA 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define KS_CDEM 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define KS_PORTAB 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define KS_LUMA 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define KS_CON 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define KS_BRT 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define KS_CHROMA 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define KS_CHROMB 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define KS_DEMOD 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define KS_SAT 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define KS_HUE 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define KS_VERTIA 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define KS_VERTIB 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define KS_VERTIC 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define KS_HSCLL 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define KS_HSCLH 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define KS_VSCLL 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define KS_VSCLH 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define KS_OFMTA 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define KS_OFMTB 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define KS_VBICTL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define KS_CCDAT2 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define KS_CCDAT1 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define KS_VBIL30 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define KS_VBIL74 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define KS_VBIL118 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define KS_VBIL1512 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define KS_TTFRAM 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define KS_TESTA 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define KS_UVOFFH 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define KS_UVOFFL 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define KS_UGAIN 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define KS_VGAIN 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define KS_VAVB 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define KS_VAVE 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define KS_CTRACK 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define KS_POLCTL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define KS_REFCOD 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define KS_INVALY 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define KS_INVALU 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define KS_INVALV 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define KS_UNUSEY 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define KS_UNUSEU 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define KS_UNUSEV 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define KS_USRSAV 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define KS_USREAV 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define KS_SHS1A 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define KS_SHS1B 0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define KS_SHS1C 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define KS_CMDE 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define KS_VSDEL 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define KS_CMDF 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define KS_GAMMA0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define KS_GAMMA1 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define KS_GAMMA2 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define KS_GAMMA3 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define KS_GAMMA4 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define KS_GAMMA5 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define KS_GAMMA6 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define KS_GAMMA7 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define KS_GAMMA8 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define KS_GAMMA9 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define KS_GAMMA10 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define KS_GAMMA11 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define KS_GAMMA12 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define KS_GAMMA13 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define KS_GAMMA14 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define KS_GAMMA15 0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define KS_GAMMA16 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define KS_GAMMA17 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define KS_GAMMA18 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define KS_GAMMA19 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define KS_GAMMA20 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define KS_GAMMA21 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define KS_GAMMA22 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define KS_GAMMA23 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define KS_GAMMA24 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define KS_GAMMA25 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define KS_GAMMA26 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define KS_GAMMA27 0x5b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define KS_GAMMA28 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define KS_GAMMA29 0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define KS_GAMMA30 0x5e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define KS_GAMMA31 0x5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define KS_GAMMAD0 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define KS_GAMMAD1 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define KS_GAMMAD2 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define KS_GAMMAD3 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define KS_GAMMAD4 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define KS_GAMMAD5 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define KS_GAMMAD6 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define KS_GAMMAD7 0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define KS_GAMMAD8 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define KS_GAMMAD9 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define KS_GAMMAD10 0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define KS_GAMMAD11 0x6b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define KS_GAMMAD12 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define KS_GAMMAD13 0x6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define KS_GAMMAD14 0x6e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define KS_GAMMAD15 0x6f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define KS_GAMMAD16 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define KS_GAMMAD17 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define KS_GAMMAD18 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define KS_GAMMAD19 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define KS_GAMMAD20 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define KS_GAMMAD21 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define KS_GAMMAD22 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define KS_GAMMAD23 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define KS_GAMMAD24 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define KS_GAMMAD25 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define KS_GAMMAD26 0x7a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define KS_GAMMAD27 0x7b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define KS_GAMMAD28 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define KS_GAMMAD29 0x7d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define KS_GAMMAD30 0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define KS_GAMMAD31 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * mga_dev : represents one ks0127 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct adjust {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int contrast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int bright;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int hue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int ugain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int vgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct ks0127 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) v4l2_std_id norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u8 regs[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline struct ks0127 *to_ks0127(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return container_of(sd, struct ks0127, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int debug; /* insmod parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) module_param(debug, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MODULE_PARM_DESC(debug, "Debug output");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static u8 reg_defaults[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void init_reg_defaults(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 *table = reg_defaults;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) initialized = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) table[KS_CMDA] = 0x2c; /* VSE=0, CCIR 601, autodetect standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) table[KS_CMDB] = 0x12; /* VALIGN=0, AGC control and input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) table[KS_CMDC] = 0x00; /* Test options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* clock & input select, write 1 to PORTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) table[KS_CMDD] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) table[KS_HAVB] = 0x00; /* HAV Start Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) table[KS_HAVE] = 0x00; /* HAV End Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) table[KS_HS1B] = 0x10; /* HS1 Start Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) table[KS_HS1E] = 0x00; /* HS1 End Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) table[KS_HS2B] = 0x00; /* HS2 Start Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) table[KS_HS2E] = 0x00; /* HS2 End Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) table[KS_AGC] = 0x53; /* Manual setting for AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) table[KS_HXTRA] = 0x00; /* Extra Bits for HAV and HS1/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) table[KS_CDEM] = 0x00; /* Chroma Demodulation Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) table[KS_PORTAB] = 0x0f; /* port B is input, port A output GPPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) table[KS_LUMA] = 0x01; /* Luma control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) table[KS_CON] = 0x00; /* Contrast Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) table[KS_BRT] = 0x00; /* Brightness Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) table[KS_CHROMA] = 0x2a; /* Chroma control A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) table[KS_CHROMB] = 0x90; /* Chroma control B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) table[KS_DEMOD] = 0x00; /* Chroma Demodulation Control & Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) table[KS_SAT] = 0x00; /* Color Saturation Control*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) table[KS_HUE] = 0x00; /* Hue Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) table[KS_VERTIA] = 0x00; /* Vertical Processing Control A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Vertical Processing Control B, luma 1 line delayed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) table[KS_VERTIB] = 0x12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) table[KS_VERTIC] = 0x0b; /* Vertical Processing Control C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) table[KS_HSCLL] = 0x00; /* Horizontal Scaling Ratio Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) table[KS_HSCLH] = 0x00; /* Horizontal Scaling Ratio High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) table[KS_VSCLL] = 0x00; /* Vertical Scaling Ratio Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) table[KS_VSCLH] = 0x00; /* Vertical Scaling Ratio High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* 16 bit YCbCr 4:2:2 output; I can't make the bt866 like 8 bit /Sam */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) table[KS_OFMTA] = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) table[KS_OFMTB] = 0x00; /* Output Control B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* VBI Decoder Control; 4bit fmt: avoid Y overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) table[KS_VBICTL] = 0x5d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) table[KS_CCDAT2] = 0x00; /* Read Only register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) table[KS_CCDAT1] = 0x00; /* Read Only register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) table[KS_VBIL30] = 0xa8; /* VBI data decoding options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) table[KS_VBIL74] = 0xaa; /* VBI data decoding options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) table[KS_VBIL118] = 0x2a; /* VBI data decoding options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) table[KS_VBIL1512] = 0x00; /* VBI data decoding options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) table[KS_TTFRAM] = 0x00; /* Teletext frame alignment pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) table[KS_TESTA] = 0x00; /* test register, shouldn't be written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) table[KS_UVOFFH] = 0x00; /* UV Offset Adjustment High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) table[KS_UVOFFL] = 0x00; /* UV Offset Adjustment Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) table[KS_UGAIN] = 0x00; /* U Component Gain Adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) table[KS_VGAIN] = 0x00; /* V Component Gain Adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) table[KS_VAVB] = 0x07; /* VAV Begin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) table[KS_VAVE] = 0x00; /* VAV End */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) table[KS_CTRACK] = 0x00; /* Chroma Tracking Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) table[KS_POLCTL] = 0x41; /* Timing Signal Polarity Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) table[KS_REFCOD] = 0x80; /* Reference Code Insertion Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) table[KS_INVALY] = 0x10; /* Invalid Y Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) table[KS_INVALU] = 0x80; /* Invalid U Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) table[KS_INVALV] = 0x80; /* Invalid V Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) table[KS_UNUSEY] = 0x10; /* Unused Y Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) table[KS_UNUSEU] = 0x80; /* Unused U Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) table[KS_UNUSEV] = 0x80; /* Unused V Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) table[KS_USRSAV] = 0x00; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) table[KS_USREAV] = 0x00; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) table[KS_SHS1A] = 0x00; /* User Defined SHS1 A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* User Defined SHS1 B, ALT656=1 on 0127B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) table[KS_SHS1B] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) table[KS_SHS1C] = 0x00; /* User Defined SHS1 C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) table[KS_CMDE] = 0x00; /* Command Register E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) table[KS_VSDEL] = 0x00; /* VS Delay Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Command Register F, update -immediately- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* (there might come no vsync)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) table[KS_CMDF] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* We need to manually read because of a bug in the KS0127 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * An explanation from kayork@mail.utexas.edu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * During I2C reads, the KS0127 only samples for a stop condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * during the place where the acknowledge bit should be. Any standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * I2C implementation (correctly) throws in another clock transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * at the 9th bit, and the KS0127 will not recognize the stop condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * and will continue to clock out data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * So we have to do the read ourself. Big deal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * workaround in i2c-algo-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static u8 ks0127_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) char val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct i2c_msg msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .len = sizeof(reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .buf = ®
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .flags = I2C_M_RD | I2C_M_NO_RD_ACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .len = sizeof(val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .buf = &val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) v4l2_dbg(1, debug, sd, "read error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static void ks0127_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct ks0127 *ks = to_ks0127(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) char msg[] = { reg, val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (i2c_master_send(client, msg, sizeof(msg)) != sizeof(msg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) v4l2_dbg(1, debug, sd, "write error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ks->regs[reg] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* generic bit-twiddling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void ks0127_and_or(struct v4l2_subdev *sd, u8 reg, u8 and_v, u8 or_v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct ks0127 *ks = to_ks0127(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u8 val = ks->regs[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) val = (val & and_v) | or_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ks0127_write(sd, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * ks0127 private api
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void ks0127_init(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 *table = reg_defaults;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) v4l2_dbg(1, debug, sd, "reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* initialize all registers to known values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* (except STAT, 0x21, 0x22, TEST and 0x38,0x39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) for (i = 1; i < 33; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ks0127_write(sd, i, table[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) for (i = 35; i < 40; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ks0127_write(sd, i, table[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) for (i = 41; i < 56; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ks0127_write(sd, i, table[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) for (i = 58; i < 64; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ks0127_write(sd, i, table[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if ((ks0127_read(sd, KS_STAT) & 0x80) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) v4l2_dbg(1, debug, sd, "ks0122s found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) switch (ks0127_read(sd, KS_CMDE) & 0x0f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) v4l2_dbg(1, debug, sd, "ks0127 found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) v4l2_dbg(1, debug, sd, "ks0127B Revision A found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) v4l2_dbg(1, debug, sd, "unknown revision\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int ks0127_s_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct ks0127 *ks = to_ks0127(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) switch (input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case KS_INPUT_COMPOSITE_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case KS_INPUT_COMPOSITE_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case KS_INPUT_COMPOSITE_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case KS_INPUT_COMPOSITE_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case KS_INPUT_COMPOSITE_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case KS_INPUT_COMPOSITE_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "s_routing %d: Composite\n", input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* autodetect 50/60 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ks0127_and_or(sd, KS_CMDA, 0xfc, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* VSE=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ks0127_and_or(sd, KS_CMDA, ~0x40, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* set input line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ks0127_and_or(sd, KS_CMDB, 0xb0, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* non-freerunning mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ks0127_and_or(sd, KS_CMDC, 0x70, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* analog input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ks0127_and_or(sd, KS_CMDD, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* enable chroma demodulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* chroma trap, HYBWR=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ks0127_and_or(sd, KS_LUMA, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) (reg_defaults[KS_LUMA])|0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* scaler fullbw, luma comb off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ks0127_and_or(sd, KS_VERTIA, 0x08, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* manual chroma comb .25 .5 .25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ks0127_and_or(sd, KS_VERTIC, 0x0f, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* chroma path delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ks0127_and_or(sd, KS_CHROMB, 0x0f, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ks0127_write(sd, KS_UGAIN, reg_defaults[KS_UGAIN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ks0127_write(sd, KS_VGAIN, reg_defaults[KS_VGAIN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ks0127_write(sd, KS_UVOFFH, reg_defaults[KS_UVOFFH]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ks0127_write(sd, KS_UVOFFL, reg_defaults[KS_UVOFFL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case KS_INPUT_SVIDEO_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case KS_INPUT_SVIDEO_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) case KS_INPUT_SVIDEO_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "s_routing %d: S-Video\n", input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* autodetect 50/60 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ks0127_and_or(sd, KS_CMDA, 0xfc, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* VSE=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ks0127_and_or(sd, KS_CMDA, ~0x40, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* set input line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ks0127_and_or(sd, KS_CMDB, 0xb0, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* non-freerunning mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ks0127_and_or(sd, KS_CMDC, 0x70, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* analog input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ks0127_and_or(sd, KS_CMDD, 0x03, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* enable chroma demodulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ks0127_and_or(sd, KS_LUMA, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) reg_defaults[KS_LUMA]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* disable luma comb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ks0127_and_or(sd, KS_VERTIA, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) (reg_defaults[KS_VERTIA]&0xf0)|0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ks0127_and_or(sd, KS_VERTIC, 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) reg_defaults[KS_VERTIC]&0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ks0127_and_or(sd, KS_CHROMB, 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) reg_defaults[KS_CHROMB]&0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ks0127_write(sd, KS_UGAIN, reg_defaults[KS_UGAIN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ks0127_write(sd, KS_VGAIN, reg_defaults[KS_VGAIN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ks0127_write(sd, KS_UVOFFH, reg_defaults[KS_UVOFFH]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ks0127_write(sd, KS_UVOFFL, reg_defaults[KS_UVOFFL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case KS_INPUT_YUV656:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) v4l2_dbg(1, debug, sd, "s_routing 15: YUV656\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (ks->norm & V4L2_STD_525_60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* force 60 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ks0127_and_or(sd, KS_CMDA, 0xfc, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* force 50 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ks0127_and_or(sd, KS_CMDA, 0xfc, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ks0127_and_or(sd, KS_CMDA, 0xff, 0x40); /* VSE=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* set input line and VALIGN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ks0127_and_or(sd, KS_CMDB, 0xb0, (input | 0x40));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* freerunning mode, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* TSTGEN = 1 TSTGFR=11 TSTGPH=0 TSTGPK=0 VMEM=1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ks0127_and_or(sd, KS_CMDC, 0x70, 0x87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* digital input, SYNDIR = 0 INPSL=01 CLKDIR=0 EAV=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ks0127_and_or(sd, KS_CMDD, 0x03, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* disable chroma demodulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* HYPK =01 CTRAP = 0 HYBWR=0 PED=1 RGBH=1 UNIT=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ks0127_and_or(sd, KS_LUMA, 0x00, 0x71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ks0127_and_or(sd, KS_VERTIC, 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) reg_defaults[KS_VERTIC]&0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* scaler fullbw, luma comb off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ks0127_and_or(sd, KS_VERTIA, 0x08, 0x81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ks0127_and_or(sd, KS_CHROMB, 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) reg_defaults[KS_CHROMB]&0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ks0127_and_or(sd, KS_CON, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ks0127_and_or(sd, KS_BRT, 0x00, 32); /* spec: 34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* spec: 229 (e5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ks0127_and_or(sd, KS_SAT, 0x00, 0xe8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ks0127_and_or(sd, KS_HUE, 0x00, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ks0127_and_or(sd, KS_UGAIN, 0x00, 238);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ks0127_and_or(sd, KS_VGAIN, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /*UOFF:0x30, VOFF:0x30, TSTCGN=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ks0127_and_or(sd, KS_UVOFFH, 0x00, 0x4f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ks0127_and_or(sd, KS_UVOFFL, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) "s_routing: Unknown input %d\n", input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* hack: CDMLPF sometimes spontaneously switches on; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* force back off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ks0127_write(sd, KS_DEMOD, reg_defaults[KS_DEMOD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int ks0127_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct ks0127 *ks = to_ks0127(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Set to automatic SECAM/Fsc mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ks->norm = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (std & V4L2_STD_NTSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) "s_std: NTSC_M\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) } else if (std & V4L2_STD_PAL_N) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) "s_std: NTSC_N (fixme)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) } else if (std & V4L2_STD_PAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) "s_std: PAL_N\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } else if (std & V4L2_STD_PAL_M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) "s_std: PAL_M (fixme)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) } else if (std & V4L2_STD_SECAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) "s_std: SECAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* set to secam autodetection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ks0127_and_or(sd, KS_CHROMA, 0xdf, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) schedule_timeout_interruptible(HZ/10+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* did it autodetect? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (!(ks0127_read(sd, KS_DEMOD) & 0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* force to secam mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) v4l2_dbg(1, debug, sd, "s_std: Unknown norm %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) (unsigned long long)std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int ks0127_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) v4l2_dbg(1, debug, sd, "s_stream(%d)\n", enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* All output pins on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ks0127_and_or(sd, KS_OFMTA, 0xcf, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Obey the OEN pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ks0127_and_or(sd, KS_CDEM, 0x7f, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Video output pins off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ks0127_and_or(sd, KS_OFMTA, 0xcf, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* Ignore the OEN pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ks0127_and_or(sd, KS_CDEM, 0x7f, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int ks0127_status(struct v4l2_subdev *sd, u32 *pstatus, v4l2_std_id *pstd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int stat = V4L2_IN_ST_NO_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) v4l2_std_id std = pstd ? *pstd : V4L2_STD_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) status = ks0127_read(sd, KS_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (!(status & 0x20)) /* NOVID not set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (!(status & 0x01)) { /* CLOCK set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) stat |= V4L2_IN_ST_NO_COLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) std = V4L2_STD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if ((status & 0x08)) /* PALDET set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) std &= V4L2_STD_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) std &= V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if ((status & 0x10)) /* PALDET set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) std &= V4L2_STD_525_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) std &= V4L2_STD_625_50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (pstd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) *pstd = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (pstatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) *pstatus = stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int ks0127_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) v4l2_dbg(1, debug, sd, "querystd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return ks0127_status(sd, NULL, std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int ks0127_g_input_status(struct v4l2_subdev *sd, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) v4l2_dbg(1, debug, sd, "g_input_status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return ks0127_status(sd, status, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static const struct v4l2_subdev_video_ops ks0127_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .s_std = ks0127_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .s_routing = ks0127_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .s_stream = ks0127_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .querystd = ks0127_querystd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .g_input_status = ks0127_g_input_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const struct v4l2_subdev_ops ks0127_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .video = &ks0127_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int ks0127_probe(struct i2c_client *client, const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct ks0127 *ks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) v4l_info(client, "%s chip found @ 0x%x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) client->addr == (I2C_KS0127_ADDON >> 1) ? "addon" : "on-board",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ks = devm_kzalloc(&client->dev, sizeof(*ks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ks == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) sd = &ks->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) v4l2_i2c_subdev_init(sd, client, &ks0127_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) init_reg_defaults();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ks0127_write(sd, KS_CMDA, 0x2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* reset the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ks0127_init(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int ks0127_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ks0127_write(sd, KS_OFMTA, 0x20); /* tristate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ks0127_write(sd, KS_CMDA, 0x2c | 0x80); /* power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static const struct i2c_device_id ks0127_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) { "ks0127", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) { "ks0127b", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) { "ks0122s", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) MODULE_DEVICE_TABLE(i2c, ks0127_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static struct i2c_driver ks0127_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .name = "ks0127",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .probe = ks0127_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .remove = ks0127_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .id_table = ks0127_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) module_i2c_driver(ks0127_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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