^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * jx_k17 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add function g_mbus_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define JX_K17_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define JX_K17_LINK_FREQ 198000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define JX_K17_PIXEL_RATE (JX_K17_LINK_FREQ * 2 * JX_K17_LANES / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define JX_K17_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CHIP_ID_H 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CHIP_ID_L 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define JX_K17_PIDH_ADDR 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define JX_K17_PIDL_ADDR 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define JX_K17_REG_CTRL_MODE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define JX_K17_MODE_SW_STANDBY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define JX_K17_MODE_STREAMING 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define JX_K17_AEC_PK_LONG_EXPO_HIGH_REG 0x02 /* Exposure Bits 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define JX_K17_AEC_PK_LONG_EXPO_LOW_REG 0x01 /* Exposure Bits 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define JX_K17_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define JX_K17_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define JX_K17_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define JX_K17_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define JX_K17_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define JX_K17_AEC_PK_LONG_GAIN_REG 0x00 /* Bits 0 -7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ANALOG_GAIN_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ANALOG_GAIN_MAX 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ANALOG_GAIN_DEFAULT 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define JX_K17_DIGI_GAIN_L_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define JX_K17_DIGI_GAIN_H_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define JX_K17_DIGI_GAIN_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define JX_K17_DIGI_GAIN_MAX (0x4000 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define JX_K17_DIGI_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define JX_K17_DIGI_GAIN_DEFAULT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define JX_K17_REG_TEST_PATTERN 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define JX_K17_TEST_PATTERN_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define JX_K17_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define JX_K17_REG_HIGH_VTS 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define JX_K17_REG_LOW_VTS 0X22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define JX_K17_FETCH_HIGH_BYTE_VTS(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define JX_K17_FETCH_LOW_BYTE_VTS(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define JX_K17_FLIP_MIRROR_REG 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define REG_NULL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define REG_DELAY 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define JX_K17_NAME "jx_k17"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const char * const jx_k17_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define JX_K17_NUM_SUPPLIES ARRAY_SIZE(jx_k17_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct jx_k17_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct jx_k17 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct regulator_bulk_data supplies[JX_K17_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct jx_k17_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define to_jx_k17(sd) container_of(sd, struct jx_k17, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct regval jx_k17_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * lane 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * linelength 880(0x370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * framelength 1500(0x5dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * grabwindow_width 2560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * grabwindow_height 1440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * mipi_datarate per lane 396Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct regval jx_k17_2560x1440_2lane_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x12, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x48, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x48, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x0E, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x0F, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x10, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x11, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x0D, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x57, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x58, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x5F, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x60, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x61, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x07, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x20, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x21, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x22, 0xDC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x23, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x24, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x25, 0xA0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x26, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x27, 0x6C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x28, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x29, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x2A, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x2B, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x2C, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x2D, 0x1D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x2E, 0x8B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x2F, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x41, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x42, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x46, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x47, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x80, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0xAF, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0xBD, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0xBE, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x1D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x1E, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x6C, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x70, 0xD1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x71, 0x8B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x72, 0x6D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x73, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x75, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x74, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x89, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x0C, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x6B, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x86, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x9E, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x78, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x30, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x31, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x32, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x33, 0xA8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x34, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x35, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3A, 0xA0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x56, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x59, 0xAC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x85, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x8A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x91, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x9F, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0xBB, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x5B, 0xA4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x5C, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x5D, 0xE4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x5E, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x64, 0xE0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x65, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x66, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x67, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x68, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x69, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x6A, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x7A, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x82, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x8F, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x9D, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x97, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x13, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x96, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x4A, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x7E, 0xC9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0xA7, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x50, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x49, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x7B, 0x4A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x7C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x7F, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x62, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x8C, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x8D, 0xC7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x8E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x8B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0xBF, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x4E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0xBF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0xA3, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0xA0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0xA2, 0x8D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x81, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x19, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const struct jx_k17_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .width = 2560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .height = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .exp_def = 0x001f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .hts_def = 0x0370 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .vts_def = 0x05dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .reg_list = jx_k17_2560x1440_2lane_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) JX_K17_LINK_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const char * const jx_k17_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static inline u32 jx_k17_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return DIV_ROUND_UP(cycles, JX_K17_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int jx_k17_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "jx_k17 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int jx_k17_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 i, delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (regs[i].addr == REG_DELAY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) delay_us = jx_k17_cal_delay(500 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = jx_k17_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int jx_k17_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "jx_k17 read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int jx_k17_get_reso_dist(const struct jx_k17_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct jx_k17_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) jx_k17_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dist = jx_k17_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int jx_k17_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct jx_k17 *jx_k17 = to_jx_k17(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) const struct jx_k17_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mutex_lock(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) mode = jx_k17_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mutex_unlock(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) jx_k17->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) __v4l2_ctrl_modify_range(jx_k17->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) __v4l2_ctrl_modify_range(jx_k17->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) JX_K17_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) mutex_unlock(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int jx_k17_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct jx_k17 *jx_k17 = to_jx_k17(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) const struct jx_k17_mode *mode = jx_k17->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mutex_lock(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) mutex_unlock(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) mutex_unlock(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int jx_k17_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct jx_k17 *jx_k17 = to_jx_k17(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) code->code = jx_k17->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int jx_k17_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int jx_k17_enable_test_pattern(struct jx_k17 *jx_k17, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) jx_k17_read_reg(jx_k17->client, JX_K17_REG_TEST_PATTERN, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) val |= (pattern - 1) | JX_K17_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) val &= ~JX_K17_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return jx_k17_write_reg(jx_k17->client, JX_K17_REG_TEST_PATTERN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int jx_k17_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct jx_k17 *jx_k17 = to_jx_k17(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) const struct jx_k17_mode *mode = jx_k17->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mutex_lock(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) mutex_unlock(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int jx_k17_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct jx_k17 *jx_k17 = to_jx_k17(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) const struct jx_k17_mode *mode = jx_k17->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) val = 1 << (JX_K17_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static void jx_k17_get_module_inf(struct jx_k17 *jx_k17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) strscpy(inf->base.sensor, JX_K17_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) strscpy(inf->base.module, jx_k17->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) strscpy(inf->base.lens, jx_k17->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static long jx_k17_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct jx_k17 *jx_k17 = to_jx_k17(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) jx_k17_get_module_inf(jx_k17, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) hdr->hdr_mode = jx_k17->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) w = jx_k17->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) h = jx_k17->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) jx_k17->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dev_err(&jx_k17->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) w = jx_k17->cur_mode->hts_def - jx_k17->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) h = jx_k17->cur_mode->vts_def - jx_k17->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) __v4l2_ctrl_modify_range(jx_k17->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) __v4l2_ctrl_modify_range(jx_k17->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) JX_K17_VTS_MAX - jx_k17->cur_mode->height, 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = jx_k17_write_reg(jx_k17->client, JX_K17_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) JX_K17_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = jx_k17_write_reg(jx_k17->client, JX_K17_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) JX_K17_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static long jx_k17_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ret = jx_k17_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret = jx_k17_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = jx_k17_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ret = jx_k17_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = jx_k17_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int __jx_k17_start_stream(struct jx_k17 *jx_k17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = jx_k17_write_array(jx_k17->client, jx_k17->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ret = __v4l2_ctrl_handler_setup(&jx_k17->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ret = jx_k17_write_reg(jx_k17->client, JX_K17_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) JX_K17_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int __jx_k17_stop_stream(struct jx_k17 *jx_k17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return jx_k17_write_reg(jx_k17->client, JX_K17_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) JX_K17_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int jx_k17_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct jx_k17 *jx_k17 = to_jx_k17(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct i2c_client *client = jx_k17->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) mutex_lock(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (on == jx_k17->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ret = __jx_k17_start_stream(jx_k17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) __jx_k17_stop_stream(jx_k17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) jx_k17->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mutex_unlock(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int jx_k17_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct jx_k17 *jx_k17 = to_jx_k17(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct i2c_client *client = jx_k17->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mutex_lock(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (jx_k17->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ret = jx_k17_write_array(jx_k17->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) jx_k17_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) jx_k17->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) jx_k17->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) mutex_unlock(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static int __jx_k17_power_on(struct jx_k17 *jx_k17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct device *dev = &jx_k17->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (!IS_ERR_OR_NULL(jx_k17->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ret = pinctrl_select_state(jx_k17->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) jx_k17->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ret = clk_set_rate(jx_k17->xvclk, JX_K17_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (clk_get_rate(jx_k17->xvclk) != JX_K17_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ret = clk_prepare_enable(jx_k17->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (!IS_ERR(jx_k17->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) gpiod_set_value_cansleep(jx_k17->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (!IS_ERR(jx_k17->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) gpiod_set_value_cansleep(jx_k17->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) usleep_range(2 * 1000, 3 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (!IS_ERR(jx_k17->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) gpiod_set_value_cansleep(jx_k17->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ret = regulator_bulk_enable(JX_K17_NUM_SUPPLIES, jx_k17->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* According to datasheet, at least 10ms for reset duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) usleep_range(10 * 1000, 15 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (!IS_ERR(jx_k17->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) gpiod_set_value_cansleep(jx_k17->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) usleep_range(2000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (!IS_ERR(jx_k17->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) gpiod_set_value_cansleep(jx_k17->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (!IS_ERR(jx_k17->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) usleep_range(6000, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) usleep_range(12000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) delay_us = jx_k17_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) clk_disable_unprepare(jx_k17->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static void __jx_k17_power_off(struct jx_k17 *jx_k17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct device *dev = &jx_k17->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (!IS_ERR(jx_k17->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) gpiod_set_value_cansleep(jx_k17->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) clk_disable_unprepare(jx_k17->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (!IS_ERR(jx_k17->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) gpiod_set_value_cansleep(jx_k17->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (!IS_ERR_OR_NULL(jx_k17->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ret = pinctrl_select_state(jx_k17->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) jx_k17->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) regulator_bulk_disable(JX_K17_NUM_SUPPLIES, jx_k17->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int jx_k17_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct jx_k17 *jx_k17 = to_jx_k17(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return __jx_k17_power_on(jx_k17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static int jx_k17_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct jx_k17 *jx_k17 = to_jx_k17(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) __jx_k17_power_off(jx_k17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static int jx_k17_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct jx_k17 *jx_k17 = to_jx_k17(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) const struct jx_k17_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) mutex_lock(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) mutex_unlock(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static int jx_k17_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static const struct dev_pm_ops jx_k17_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) SET_RUNTIME_PM_OPS(jx_k17_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) jx_k17_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static const struct v4l2_subdev_internal_ops jx_k17_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .open = jx_k17_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static const struct v4l2_subdev_core_ops jx_k17_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .s_power = jx_k17_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .ioctl = jx_k17_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .compat_ioctl32 = jx_k17_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static const struct v4l2_subdev_video_ops jx_k17_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .s_stream = jx_k17_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .g_frame_interval = jx_k17_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static const struct v4l2_subdev_pad_ops jx_k17_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .enum_mbus_code = jx_k17_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .enum_frame_size = jx_k17_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .enum_frame_interval = jx_k17_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .get_fmt = jx_k17_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .set_fmt = jx_k17_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .get_mbus_config = jx_k17_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static const struct v4l2_subdev_ops jx_k17_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .core = &jx_k17_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .video = &jx_k17_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .pad = &jx_k17_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static int jx_k17_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct jx_k17 *jx_k17 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct jx_k17, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct i2c_client *client = jx_k17->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) max = jx_k17->cur_mode->height + ctrl->val - 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) __v4l2_ctrl_modify_range(jx_k17->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) jx_k17->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) jx_k17->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) jx_k17->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dev_dbg(&client->dev, "set expo: val: %d\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ret = jx_k17_write_reg(jx_k17->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) JX_K17_AEC_PK_LONG_EXPO_HIGH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) JX_K17_FETCH_HIGH_BYTE_EXP(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ret |= jx_k17_write_reg(jx_k17->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) JX_K17_AEC_PK_LONG_EXPO_LOW_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) JX_K17_FETCH_LOW_BYTE_EXP(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dev_dbg(&client->dev, "set a-gain: val: %d\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ret |= jx_k17_write_reg(jx_k17->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) JX_K17_AEC_PK_LONG_GAIN_REG, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dev_dbg(&client->dev, "set vblank: val: %d\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ret |= jx_k17_write_reg(jx_k17->client, JX_K17_REG_HIGH_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) JX_K17_FETCH_HIGH_BYTE_VTS((ctrl->val + jx_k17->cur_mode->height)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ret |= jx_k17_write_reg(jx_k17->client, JX_K17_REG_LOW_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) JX_K17_FETCH_LOW_BYTE_VTS((ctrl->val + jx_k17->cur_mode->height)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret = jx_k17_enable_test_pattern(jx_k17, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static const struct v4l2_ctrl_ops jx_k17_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .s_ctrl = jx_k17_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static int jx_k17_initialize_controls(struct jx_k17 *jx_k17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) const struct jx_k17_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) handler = &jx_k17->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) mode = jx_k17->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ret = v4l2_ctrl_handler_init(handler, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) handler->lock = &jx_k17->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) 0, JX_K17_PIXEL_RATE, 1, JX_K17_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) jx_k17->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (jx_k17->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) jx_k17->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) jx_k17->vblank = v4l2_ctrl_new_std(handler, &jx_k17_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) JX_K17_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) exposure_max = mode->vts_def - 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) jx_k17->exposure = v4l2_ctrl_new_std(handler, &jx_k17_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) V4L2_CID_EXPOSURE, JX_K17_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) exposure_max, JX_K17_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) jx_k17->anal_gain = v4l2_ctrl_new_std(handler, &jx_k17_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) jx_k17->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) &jx_k17_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ARRAY_SIZE(jx_k17_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) 0, 0, jx_k17_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dev_err(&jx_k17->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) jx_k17->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static int jx_k17_check_sensor_id(struct jx_k17 *jx_k17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct device *dev = &jx_k17->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) u8 id_h = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) u8 id_l = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ret = jx_k17_read_reg(client, JX_K17_PIDH_ADDR, &id_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ret |= jx_k17_read_reg(client, JX_K17_PIDL_ADDR, &id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (id_h != CHIP_ID_H && id_l != CHIP_ID_L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dev_err(dev, "Wrong camera sensor id(0x%02x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) id_h, id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev_info(dev, "Detected jx_k17 (0x%02x%02x) sensor\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) id_h, id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static int jx_k17_configure_regulators(struct jx_k17 *jx_k17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) for (i = 0; i < JX_K17_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) jx_k17->supplies[i].supply = jx_k17_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return devm_regulator_bulk_get(&jx_k17->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) JX_K17_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) jx_k17->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static int jx_k17_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct jx_k17 *jx_k17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) jx_k17 = devm_kzalloc(dev, sizeof(*jx_k17), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (!jx_k17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) &jx_k17->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) &jx_k17->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) &jx_k17->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) &jx_k17->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) jx_k17->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) jx_k17->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) jx_k17->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (IS_ERR(jx_k17->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) jx_k17->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (IS_ERR(jx_k17->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) jx_k17->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (IS_ERR(jx_k17->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) jx_k17->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (!IS_ERR(jx_k17->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) jx_k17->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) pinctrl_lookup_state(jx_k17->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (IS_ERR(jx_k17->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) jx_k17->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) pinctrl_lookup_state(jx_k17->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (IS_ERR(jx_k17->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) ret = jx_k17_configure_regulators(jx_k17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) mutex_init(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) sd = &jx_k17->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) v4l2_i2c_subdev_init(sd, client, &jx_k17_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ret = jx_k17_initialize_controls(jx_k17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ret = __jx_k17_power_on(jx_k17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ret = jx_k17_check_sensor_id(jx_k17, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) sd->internal_ops = &jx_k17_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) jx_k17->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ret = media_entity_pads_init(&sd->entity, 1, &jx_k17->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (strcmp(jx_k17->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) jx_k17->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) JX_K17_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) __jx_k17_power_off(jx_k17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) v4l2_ctrl_handler_free(&jx_k17->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) mutex_destroy(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static int jx_k17_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct jx_k17 *jx_k17 = to_jx_k17(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) v4l2_ctrl_handler_free(&jx_k17->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) mutex_destroy(&jx_k17->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) __jx_k17_power_off(jx_k17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static const struct of_device_id jx_k17_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) { .compatible = "soi,jx_k17" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) MODULE_DEVICE_TABLE(of, jx_k17_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static const struct i2c_device_id jx_k17_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) { "soi,jx_k17", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static struct i2c_driver jx_k17_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .name = JX_K17_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .pm = &jx_k17_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .of_match_table = of_match_ptr(jx_k17_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .probe = &jx_k17_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .remove = &jx_k17_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .id_table = jx_k17_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return i2c_add_driver(&jx_k17_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) i2c_del_driver(&jx_k17_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) MODULE_DESCRIPTION("SOI jx_k17 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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