^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * jx_h65 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add function g_mbus_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define JX_H65_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CHIP_ID_H 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CHIP_ID_L 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define JX_H65_PIDH_ADDR 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define JX_H65_PIDL_ADDR 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define JX_H65_REG_CTRL_MODE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define JX_H65_MODE_SW_STANDBY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define JX_H65_MODE_STREAMING 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define JX_H65_AEC_PK_LONG_EXPO_HIGH_REG 0x02 /* Exposure Bits 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define JX_H65_AEC_PK_LONG_EXPO_LOW_REG 0x01 /* Exposure Bits 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define JX_H65_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define JX_H65_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define JX_H65_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define JX_H65_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define JX_H65_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define JX_H65_AEC_PK_LONG_GAIN_REG 0x00 /* Bits 0 -7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ANALOG_GAIN_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ANALOG_GAIN_MAX 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ANALOG_GAIN_DEFAULT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define JX_H65_DIGI_GAIN_L_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define JX_H65_DIGI_GAIN_H_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define JX_H65_DIGI_GAIN_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define JX_H65_DIGI_GAIN_MAX (0x4000 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define JX_H65_DIGI_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define JX_H65_DIGI_GAIN_DEFAULT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define JX_H65_REG_TEST_PATTERN 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define JX_H65_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define JX_H65_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define JX_H65_REG_HIGH_VTS 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define JX_H65_REG_LOW_VTS 0X22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define JX_H65_FETCH_HIGH_BYTE_VTS(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define JX_H65_FETCH_LOW_BYTE_VTS(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_NULL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_DELAY 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define JX_H65_NAME "jx_h65"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define JX_H65_LANES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const char * const jx_h65_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "vcc2v8_dvp", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "vcc1v8_dvp", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "vdd1v5_dvp", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define JX_H65_NUM_SUPPLIES ARRAY_SIZE(jx_h65_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct jx_h65_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct jx_h65 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct regulator_bulk_data supplies[JX_H65_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const struct jx_h65_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define to_jx_h65(sd) container_of(sd, struct jx_h65, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Pclk 45Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * linelength 672(0x2a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * framelength 2232(0x8b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * grabwindow_width 1280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * grabwindow_height 720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * mipi_datarate per lane 216Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct regval jx_h65_1280x720_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x12, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x0E, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x0F, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x10, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0x11, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x5F, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x60, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x19, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x48, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x20, 0xD0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x21, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x22, 0xE8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x23, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x24, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x25, 0xD0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x26, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x27, 0x5C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x28, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x29, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x2A, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x2B, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x2C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x2D, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x2E, 0xF9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x2F, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x41, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x42, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x39, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x1D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x1E, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x6C, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x70, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x71, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x72, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x73, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x74, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x75, 0x2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x76, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x77, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x78, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x6E, 0x2C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x1F, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x31, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x32, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x33, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x34, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x36, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x38, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3A, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3B, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3C, 0xA0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x40, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x0D, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x5A, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x5B, 0xB3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x5C, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x5D, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x5E, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x62, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x67, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x6A, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x68, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x8F, 0x9F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x0C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x59, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x4A, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x50, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x47, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x7E, 0xCD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x8D, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x49, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x7F, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x8E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x8C, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x8B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x57, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x94, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x95, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x63, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x7B, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x7C, 0x2D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x79, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x13, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x45, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x93, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {REG_DELAY, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x45, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x1F, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x17, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x16, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {REG_NULL, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct regval jx_h65_1280x960_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x12, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x0E, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x0F, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x10, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x11, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x5F, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x60, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x19, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x48, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x20, 0xD0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x21, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x22, 0xE8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x23, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x24, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x25, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x26, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x27, 0x5C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x28, 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x29, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x2A, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x2B, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x2C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x2D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x2E, 0xF9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x2F, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x41, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x42, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x39, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x1D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x1E, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x6C, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x70, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x71, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x72, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x73, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x74, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x75, 0x2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x76, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x77, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x78, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x6E, 0x2C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x1F, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x31, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x32, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x33, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x34, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x36, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x38, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3A, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x3B, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x3C, 0xA0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x40, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x0D, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x5A, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x5B, 0xB3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x5C, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x5D, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x5E, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x62, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x67, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x6A, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x68, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x8F, 0x9F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x0C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x59, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x4A, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x50, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x47, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x7E, 0xCD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x8D, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x49, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x7F, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x8E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x8C, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x8B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x57, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x94, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x95, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x63, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x7B, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x7C, 0x2D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x79, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x13, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x12, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x45, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x93, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {REG_DELAY, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x45, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x1F, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {REG_NULL, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct jx_h65_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .height = 960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .exp_def = 0x0384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .hts_def = 0x02d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .vts_def = 0x03e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .reg_list = jx_h65_1280x960_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .height = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .exp_def = 0x0384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .hts_def = 0x02d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .vts_def = 0x03e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .reg_list = jx_h65_1280x720_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define JX_H65_LINK_FREQ_420MHZ 216000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define JX_H65_PIXEL_RATE (JX_H65_LINK_FREQ_420MHZ * 2 * 1 / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) JX_H65_LINK_FREQ_420MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const char * const jx_h65_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static inline u32 jx_h65_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return DIV_ROUND_UP(cycles, JX_H65_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int jx_h65_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "jx_h65 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int jx_h65_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 i, delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (regs[i].addr == REG_DELAY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) delay_us = jx_h65_cal_delay(500 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = jx_h65_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int jx_h65_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "jx_h65 read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int jx_h65_get_reso_dist(const struct jx_h65_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static const struct jx_h65_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) jx_h65_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dist = jx_h65_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int jx_h65_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct jx_h65 *jx_h65 = to_jx_h65(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) const struct jx_h65_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) mutex_lock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) mode = jx_h65_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) mutex_unlock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) jx_h65->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) __v4l2_ctrl_modify_range(jx_h65->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) __v4l2_ctrl_modify_range(jx_h65->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) JX_H65_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mutex_unlock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static int jx_h65_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct jx_h65 *jx_h65 = to_jx_h65(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) const struct jx_h65_mode *mode = jx_h65->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mutex_lock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mutex_unlock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mutex_unlock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int jx_h65_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static int jx_h65_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int jx_h65_enable_test_pattern(struct jx_h65 *jx_h65, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) val = (pattern - 1) | JX_H65_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) val = JX_H65_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return jx_h65_write_reg(jx_h65->client, JX_H65_REG_TEST_PATTERN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static void jx_h65_get_module_inf(struct jx_h65 *jx_h65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) strlcpy(inf->base.sensor, JX_H65_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) strlcpy(inf->base.module, jx_h65->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) strlcpy(inf->base.lens, jx_h65->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static long jx_h65_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct jx_h65 *jx_h65 = to_jx_h65(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) jx_h65_get_module_inf(jx_h65, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ret = jx_h65_write_reg(jx_h65->client, JX_H65_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) JX_H65_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ret = jx_h65_write_reg(jx_h65->client, JX_H65_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) JX_H65_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static long jx_h65_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret = jx_h65_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret = jx_h65_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ret = jx_h65_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static int jx_h65_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct jx_h65 *jx_h65 = to_jx_h65(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) const struct jx_h65_mode *mode = jx_h65->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) mutex_lock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) mutex_unlock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static int __jx_h65_start_stream(struct jx_h65 *jx_h65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return jx_h65_write_reg(jx_h65->client, JX_H65_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) JX_H65_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static int __jx_h65_stop_stream(struct jx_h65 *jx_h65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return jx_h65_write_reg(jx_h65->client, JX_H65_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) JX_H65_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static int jx_h65_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct jx_h65 *jx_h65 = to_jx_h65(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct i2c_client *client = jx_h65->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mutex_lock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (on == jx_h65->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ret = __jx_h65_start_stream(jx_h65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) __jx_h65_stop_stream(jx_h65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) jx_h65->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) mutex_unlock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int jx_h65_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct jx_h65 *jx_h65 = to_jx_h65(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct i2c_client *client = jx_h65->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) mutex_lock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (jx_h65->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ret = jx_h65_write_array(jx_h65->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) jx_h65->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * Enter sleep state to make sure not mipi output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * during rkisp init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) __jx_h65_stop_stream(jx_h65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mutex_unlock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = v4l2_ctrl_handler_setup(&jx_h65->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) mutex_lock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) jx_h65->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) jx_h65->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) mutex_unlock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static int __jx_h65_power_on(struct jx_h65 *jx_h65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct device *dev = &jx_h65->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret = clk_set_rate(jx_h65->xvclk, JX_H65_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (clk_get_rate(jx_h65->xvclk) != JX_H65_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret = clk_prepare_enable(jx_h65->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (!IS_ERR(jx_h65->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) gpiod_set_value_cansleep(jx_h65->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = regulator_bulk_enable(JX_H65_NUM_SUPPLIES, jx_h65->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* According to datasheet, at least 10ms for reset duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) usleep_range(10 * 1000, 15 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!IS_ERR(jx_h65->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) gpiod_set_value_cansleep(jx_h65->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (!IS_ERR(jx_h65->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) gpiod_set_value_cansleep(jx_h65->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) delay_us = jx_h65_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) clk_disable_unprepare(jx_h65->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static void __jx_h65_power_off(struct jx_h65 *jx_h65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (!IS_ERR(jx_h65->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) gpiod_set_value_cansleep(jx_h65->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) clk_disable_unprepare(jx_h65->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (!IS_ERR(jx_h65->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) gpiod_set_value_cansleep(jx_h65->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) regulator_bulk_disable(JX_H65_NUM_SUPPLIES, jx_h65->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static int jx_h65_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct jx_h65 *jx_h65 = to_jx_h65(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return __jx_h65_power_on(jx_h65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static int jx_h65_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct jx_h65 *jx_h65 = to_jx_h65(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) __jx_h65_power_off(jx_h65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static int jx_h65_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct jx_h65 *jx_h65 = to_jx_h65(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) const struct jx_h65_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) mutex_lock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mutex_unlock(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static int jx_h65_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static int jx_h65_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) val = 1 << (JX_H65_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) config->type = V4L2_MBUS_CSI2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static const struct dev_pm_ops jx_h65_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) SET_RUNTIME_PM_OPS(jx_h65_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) jx_h65_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static const struct v4l2_subdev_internal_ops jx_h65_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .open = jx_h65_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static const struct v4l2_subdev_core_ops jx_h65_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .s_power = jx_h65_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .ioctl = jx_h65_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .compat_ioctl32 = jx_h65_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static const struct v4l2_subdev_video_ops jx_h65_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .s_stream = jx_h65_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .g_frame_interval = jx_h65_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .g_mbus_config = jx_h65_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static const struct v4l2_subdev_pad_ops jx_h65_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .enum_mbus_code = jx_h65_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .enum_frame_size = jx_h65_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .enum_frame_interval = jx_h65_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .get_fmt = jx_h65_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .set_fmt = jx_h65_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static const struct v4l2_subdev_ops jx_h65_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .core = &jx_h65_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .video = &jx_h65_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .pad = &jx_h65_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static int jx_h65_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct jx_h65 *jx_h65 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct jx_h65, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct i2c_client *client = jx_h65->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) max = jx_h65->cur_mode->height + ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) __v4l2_ctrl_modify_range(jx_h65->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) jx_h65->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) jx_h65->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) jx_h65->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dev_dbg(&client->dev, "set expo: val: %d\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ret = jx_h65_write_reg(jx_h65->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) JX_H65_AEC_PK_LONG_EXPO_HIGH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) JX_H65_FETCH_HIGH_BYTE_EXP(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ret |= jx_h65_write_reg(jx_h65->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) JX_H65_AEC_PK_LONG_EXPO_LOW_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) JX_H65_FETCH_LOW_BYTE_EXP(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dev_dbg(&client->dev, "set a-gain: val: %d\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ret |= jx_h65_write_reg(jx_h65->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) JX_H65_AEC_PK_LONG_GAIN_REG, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) case V4L2_CID_DIGITAL_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) dev_dbg(&client->dev, "set vblank: val: %d\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ret |= jx_h65_write_reg(jx_h65->client, JX_H65_REG_HIGH_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) JX_H65_FETCH_HIGH_BYTE_VTS((ctrl->val + jx_h65->cur_mode->height)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret |= jx_h65_write_reg(jx_h65->client, JX_H65_REG_LOW_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) JX_H65_FETCH_LOW_BYTE_VTS((ctrl->val + jx_h65->cur_mode->height)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ret = jx_h65_enable_test_pattern(jx_h65, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static const struct v4l2_ctrl_ops jx_h65_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .s_ctrl = jx_h65_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static int jx_h65_initialize_controls(struct jx_h65 *jx_h65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) const struct jx_h65_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) handler = &jx_h65->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) mode = jx_h65->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) handler->lock = &jx_h65->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) 0, JX_H65_PIXEL_RATE, 1, JX_H65_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) jx_h65->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (jx_h65->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) jx_h65->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) jx_h65->vblank = v4l2_ctrl_new_std(handler, &jx_h65_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) JX_H65_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) exposure_max = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) jx_h65->exposure = v4l2_ctrl_new_std(handler, &jx_h65_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) V4L2_CID_EXPOSURE, JX_H65_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) exposure_max, JX_H65_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) jx_h65->anal_gain = v4l2_ctrl_new_std(handler, &jx_h65_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* Digital gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) jx_h65->digi_gain = v4l2_ctrl_new_std(handler, &jx_h65_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) V4L2_CID_DIGITAL_GAIN, JX_H65_DIGI_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) JX_H65_DIGI_GAIN_MAX, JX_H65_DIGI_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) JX_H65_DIGI_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) jx_h65->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) &jx_h65_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ARRAY_SIZE(jx_h65_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) 0, 0, jx_h65_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dev_err(&jx_h65->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) jx_h65->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static int jx_h65_check_sensor_id(struct jx_h65 *jx_h65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct device *dev = &jx_h65->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) u8 id_h = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) u8 id_l = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = jx_h65_read_reg(client, JX_H65_PIDH_ADDR, &id_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ret |= jx_h65_read_reg(client, JX_H65_PIDL_ADDR, &id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (id_h != CHIP_ID_H && id_l != CHIP_ID_L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) dev_err(dev, "Wrong camera sensor id(0x%02x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) id_h, id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) dev_info(dev, "Detected jx_h65 (0x%02x%02x) sensor\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) id_h, id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static int jx_h65_configure_regulators(struct jx_h65 *jx_h65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) for (i = 0; i < JX_H65_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) jx_h65->supplies[i].supply = jx_h65_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return devm_regulator_bulk_get(&jx_h65->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) JX_H65_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) jx_h65->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static int jx_h65_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct jx_h65 *jx_h65;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) jx_h65 = devm_kzalloc(dev, sizeof(*jx_h65), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (!jx_h65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) &jx_h65->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) &jx_h65->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) &jx_h65->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) &jx_h65->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) jx_h65->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) jx_h65->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) jx_h65->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (IS_ERR(jx_h65->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) jx_h65->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (IS_ERR(jx_h65->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) jx_h65->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (IS_ERR(jx_h65->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ret = jx_h65_configure_regulators(jx_h65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) mutex_init(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) sd = &jx_h65->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) v4l2_i2c_subdev_init(sd, client, &jx_h65_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = jx_h65_initialize_controls(jx_h65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ret = __jx_h65_power_on(jx_h65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ret = jx_h65_check_sensor_id(jx_h65, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) sd->internal_ops = &jx_h65_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) jx_h65->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ret = media_entity_pads_init(&sd->entity, 1, &jx_h65->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (strcmp(jx_h65->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) jx_h65->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) JX_H65_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ret = v4l2_async_register_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) __jx_h65_power_off(jx_h65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) v4l2_ctrl_handler_free(&jx_h65->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) mutex_destroy(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static int jx_h65_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct jx_h65 *jx_h65 = to_jx_h65(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) v4l2_ctrl_handler_free(&jx_h65->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) mutex_destroy(&jx_h65->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) __jx_h65_power_off(jx_h65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static const struct of_device_id jx_h65_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) { .compatible = "soi,jx_h65" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) MODULE_DEVICE_TABLE(of, jx_h65_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static const struct i2c_device_id jx_h65_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) { "soi,jx_h65", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static struct i2c_driver jx_h65_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .name = JX_H65_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .pm = &jx_h65_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .of_match_table = of_match_ptr(jx_h65_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .probe = &jx_h65_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .remove = &jx_h65_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .id_table = jx_h65_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) return i2c_add_driver(&jx_h65_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) i2c_del_driver(&jx_h65_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) MODULE_DESCRIPTION("SOI jx_h65 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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