^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * jx_h62 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 init version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 add function g_mbus_config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define JX_H62_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CHIP_ID_H 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CHIP_ID_L 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define JX_H62_PIDH_ADDR 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define JX_H62_PIDL_ADDR 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define JX_H62_REG_CTRL_MODE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define JX_H62_MODE_SW_STANDBY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define JX_H62_MODE_STREAMING 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define JX_H62_AEC_PK_LONG_EXPO_HIGH_REG 0x02 /* Exposure Bits 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define JX_H62_AEC_PK_LONG_EXPO_LOW_REG 0x01 /* Exposure Bits 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define JX_H62_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define JX_H62_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define JX_H62_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define JX_H62_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define JX_H62_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define JX_H62_AEC_PK_LONG_GAIN_REG 0x00 /* Bits 0 -7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ANALOG_GAIN_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ANALOG_GAIN_MAX 0xf8 /* 15.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ANALOG_GAIN_DEFAULT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define JX_H62_DIGI_GAIN_L_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define JX_H62_DIGI_GAIN_H_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define JX_H62_DIGI_GAIN_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define JX_H62_DIGI_GAIN_MAX (0x4000 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define JX_H62_DIGI_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define JX_H62_DIGI_GAIN_DEFAULT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define JX_H62_REG_TEST_PATTERN 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define JX_H62_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define JX_H62_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define JX_H62_REG_HIGH_VTS 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define JX_H62_REG_LOW_VTS 0X22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define JX_H62_FETCH_HIGH_BYTE_VTS(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define JX_H62_FETCH_LOW_BYTE_VTS(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define REG_NULL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define REG_DELAY 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define JX_H62_NAME "jx_h62"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define JX_H62_MEDIA_BUS_FMT MEDIA_BUS_FMT_SBGGR10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define JX_H62_LANES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const char * const jx_h62_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "vcc2v8_dvp", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "vcc1v8_dvp", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "vdd1v5_dvp", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define JX_H62_NUM_SUPPLIES ARRAY_SIZE(jx_h62_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct jx_h62_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct jx_h62 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct regulator_bulk_data supplies[JX_H62_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const struct jx_h62_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 old_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define to_jx_h62(sd) container_of(sd, struct jx_h62, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Pclk 45Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * linelength 672(0x2a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * framelength 2232(0x8b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * grabwindow_width 1280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * grabwindow_height 720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * mipi_datarate per lane 216Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct regval jx_h62_1280x720_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 0x12, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { 0x0E, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { 0x0F, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { 0x10, 0x1E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 0x11, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 0x19, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 0x20, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { 0x21, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { 0x22, 0xEE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 0x23, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 0x24, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 0x25, 0xD0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 0x26, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 0x27, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 0x28, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 0x29, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { 0x2A, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { 0x2B, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { 0x2C, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { 0x2D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { 0x2E, 0xBB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { 0x2F, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { 0x41, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { 0x42, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { 0x39, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { 0x1D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { 0x1E, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 0x7A, 0x4C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 0x70, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 0x71, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 0x72, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 0x73, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 0x74, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 0x75, 0x2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 0x76, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 0x77, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { 0x78, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { 0x66, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { 0x1F, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { 0x30, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { 0x31, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { 0x32, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { 0x33, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { 0x34, 0x4B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { 0x35, 0xA3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { 0x36, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { 0x38, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 0x3A, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 0x56, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 0x60, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { 0x0D, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { 0x57, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { 0x58, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { 0x5A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { 0x5B, 0xB6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { 0x5C, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { 0x5D, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { 0x5E, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { 0x5F, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { 0x66, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { 0x67, 0xF8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { 0x68, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { 0x69, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { 0x6A, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { 0x63, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { 0x6C, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { 0x6E, 0x5C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { 0x82, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { 0x0C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { 0x46, 0xC2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 0x48, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 0x62, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { 0x7D, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { 0x7E, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 0x80, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 0x4A, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 0x49, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 0x13, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 0x59, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 0x12, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 0x47, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {REG_DELAY, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { 0x47, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 0x1F, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {REG_NULL, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const struct jx_h62_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .height = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .exp_def = 0x02D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .hts_def = 0x0640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .vts_def = 0x02ee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .reg_list = jx_h62_1280x720_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MIPI_FREQ 180000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define JX_H62_PIXEL_RATE (MIPI_FREQ * 2 * 1 / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MIPI_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const char * const jx_h62_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static inline u32 jx_h62_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return DIV_ROUND_UP(cycles, JX_H62_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int jx_h62_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "jx_h62 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int jx_h62_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 i, delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (regs[i].addr == REG_DELAY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) delay_us = jx_h62_cal_delay(500 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = jx_h62_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int jx_h62_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "jx_h62 read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int jx_h62_get_reso_dist(const struct jx_h62_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const struct jx_h62_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) jx_h62_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dist = jx_h62_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int jx_h62_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct jx_h62 *jx_h62 = to_jx_h62(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) const struct jx_h62_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mutex_lock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mode = jx_h62_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) fmt->format.code = JX_H62_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) mutex_unlock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) jx_h62->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) __v4l2_ctrl_modify_range(jx_h62->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) __v4l2_ctrl_modify_range(jx_h62->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) JX_H62_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) mutex_unlock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int jx_h62_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct jx_h62 *jx_h62 = to_jx_h62(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) const struct jx_h62_mode *mode = jx_h62->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mutex_lock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mutex_unlock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) fmt->format.code = JX_H62_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mutex_unlock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int jx_h62_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) code->code = JX_H62_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int jx_h62_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (fse->code != JX_H62_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int jx_h62_enable_test_pattern(struct jx_h62 *jx_h62, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) val = (pattern - 1) | JX_H62_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) val = JX_H62_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return jx_h62_write_reg(jx_h62->client, JX_H62_REG_TEST_PATTERN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static void jx_h62_get_module_inf(struct jx_h62 *jx_h62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) strlcpy(inf->base.sensor, JX_H62_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) strlcpy(inf->base.module, jx_h62->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) strlcpy(inf->base.lens, jx_h62->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static long jx_h62_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct jx_h62 *jx_h62 = to_jx_h62(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) jx_h62_get_module_inf(jx_h62, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ret = jx_h62_write_reg(jx_h62->client, JX_H62_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) JX_H62_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = jx_h62_write_reg(jx_h62->client, JX_H62_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) JX_H62_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static long jx_h62_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = jx_h62_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = jx_h62_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = jx_h62_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int jx_h62_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct jx_h62 *jx_h62 = to_jx_h62(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) const struct jx_h62_mode *mode = jx_h62->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mutex_lock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) mutex_unlock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int __jx_h62_start_stream(struct jx_h62 *jx_h62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return jx_h62_write_reg(jx_h62->client, JX_H62_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) JX_H62_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static int __jx_h62_stop_stream(struct jx_h62 *jx_h62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return jx_h62_write_reg(jx_h62->client, JX_H62_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) JX_H62_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int jx_h62_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct jx_h62 *jx_h62 = to_jx_h62(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct i2c_client *client = jx_h62->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) mutex_lock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (on == jx_h62->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) jx_h62->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) jx_h62->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) DIV_ROUND_CLOSEST(jx_h62->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) jx_h62->cur_mode->max_fps.numerator));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = __jx_h62_start_stream(jx_h62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) v4l2_err(sd, " jx_h62 start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) __jx_h62_stop_stream(jx_h62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) jx_h62->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) mutex_unlock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static int jx_h62_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct jx_h62 *jx_h62 = to_jx_h62(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct i2c_client *client = jx_h62->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) mutex_lock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (jx_h62->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret = jx_h62_write_array(jx_h62->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) jx_h62->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * Enter sleep state to make sure not mipi output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * during rkisp init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) __jx_h62_stop_stream(jx_h62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mutex_unlock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ret = v4l2_ctrl_handler_setup(&jx_h62->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) mutex_lock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) jx_h62->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) jx_h62->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) mutex_unlock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static int __jx_h62_power_on(struct jx_h62 *jx_h62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct device *dev = &jx_h62->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = clk_set_rate(jx_h62->xvclk, JX_H62_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (clk_get_rate(jx_h62->xvclk) != JX_H62_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = clk_prepare_enable(jx_h62->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (!IS_ERR(jx_h62->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) gpiod_set_value_cansleep(jx_h62->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret = regulator_bulk_enable(JX_H62_NUM_SUPPLIES, jx_h62->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* According to datasheet, at least 10ms for reset duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) usleep_range(10 * 1000, 15 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (!IS_ERR(jx_h62->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) gpiod_set_value_cansleep(jx_h62->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (!IS_ERR(jx_h62->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) gpiod_set_value_cansleep(jx_h62->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) delay_us = jx_h62_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) clk_disable_unprepare(jx_h62->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static void __jx_h62_power_off(struct jx_h62 *jx_h62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!IS_ERR(jx_h62->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) gpiod_set_value_cansleep(jx_h62->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) clk_disable_unprepare(jx_h62->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (!IS_ERR(jx_h62->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) gpiod_set_value_cansleep(jx_h62->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) regulator_bulk_disable(JX_H62_NUM_SUPPLIES, jx_h62->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static int jx_h62_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct jx_h62 *jx_h62 = to_jx_h62(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return __jx_h62_power_on(jx_h62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static int jx_h62_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct jx_h62 *jx_h62 = to_jx_h62(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) __jx_h62_power_off(jx_h62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static int jx_h62_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct jx_h62 *jx_h62 = to_jx_h62(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) const struct jx_h62_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) mutex_lock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) try_fmt->code = JX_H62_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) mutex_unlock(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int jx_h62_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (fie->code != JX_H62_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static int jx_h62_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) val = 1 << (JX_H62_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) config->type = V4L2_MBUS_CSI2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static const struct dev_pm_ops jx_h62_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) SET_RUNTIME_PM_OPS(jx_h62_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) jx_h62_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static const struct v4l2_subdev_internal_ops jx_h62_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .open = jx_h62_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static const struct v4l2_subdev_core_ops jx_h62_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .s_power = jx_h62_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .ioctl = jx_h62_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .compat_ioctl32 = jx_h62_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static const struct v4l2_subdev_video_ops jx_h62_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .s_stream = jx_h62_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .g_frame_interval = jx_h62_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .g_mbus_config = jx_h62_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static const struct v4l2_subdev_pad_ops jx_h62_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .enum_mbus_code = jx_h62_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .enum_frame_size = jx_h62_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .enum_frame_interval = jx_h62_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .get_fmt = jx_h62_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .set_fmt = jx_h62_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static const struct v4l2_subdev_ops jx_h62_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .core = &jx_h62_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .video = &jx_h62_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .pad = &jx_h62_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int jx_h62_set_ctrl_gain(struct jx_h62 *jx_h62, u32 a_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 coarse_again, fine_again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* Total gain = 2^PGA[5:4]*(1+PGA[3:0]/16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if ( a_gain != jx_h62->old_gain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (a_gain <= 0x20) { /*1x ~ 2x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) fine_again = a_gain - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) coarse_again = (0x00 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) } else if (a_gain <= 0x40) { /*2x ~ 4x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) fine_again = (a_gain >> 1) - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) coarse_again = 0x01 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) } else if (a_gain <= 0x80) { /*4x ~ 8x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) fine_again = (a_gain >> 2) - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) coarse_again = 0x2 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) } else { /*8x ~ 15.5x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) fine_again = (a_gain >> 3) - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) coarse_again = 0x03 << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ret = jx_h62_write_reg(jx_h62->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) JX_H62_AEC_PK_LONG_GAIN_REG, coarse_again | fine_again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) jx_h62->old_gain = a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int jx_h62_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct jx_h62 *jx_h62 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct jx_h62, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct i2c_client *client = jx_h62->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) max = jx_h62->cur_mode->height + ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) __v4l2_ctrl_modify_range(jx_h62->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) jx_h62->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) jx_h62->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) jx_h62->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (pm_runtime_get(&client->dev) <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev_dbg(&client->dev, "set expo: val: %d\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ret = jx_h62_write_reg(jx_h62->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) JX_H62_AEC_PK_LONG_EXPO_HIGH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) JX_H62_FETCH_HIGH_BYTE_EXP(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ret |= jx_h62_write_reg(jx_h62->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) JX_H62_AEC_PK_LONG_EXPO_LOW_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) JX_H62_FETCH_LOW_BYTE_EXP(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dev_dbg(&client->dev, "set a-gain: val: %d\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret = jx_h62_set_ctrl_gain(jx_h62, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) case V4L2_CID_DIGITAL_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) dev_dbg(&client->dev, "set vblank: val: %d\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ret |= jx_h62_write_reg(jx_h62->client, JX_H62_REG_HIGH_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) JX_H62_FETCH_HIGH_BYTE_VTS((ctrl->val + jx_h62->cur_mode->height)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ret |= jx_h62_write_reg(jx_h62->client, JX_H62_REG_LOW_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) JX_H62_FETCH_LOW_BYTE_VTS((ctrl->val + jx_h62->cur_mode->height)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ret = jx_h62_enable_test_pattern(jx_h62, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static const struct v4l2_ctrl_ops jx_h62_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .s_ctrl = jx_h62_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static int jx_h62_initialize_controls(struct jx_h62 *jx_h62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) const struct jx_h62_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) handler = &jx_h62->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) mode = jx_h62->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) handler->lock = &jx_h62->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) 0, jx_h62->pixel_rate, 1, jx_h62->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) jx_h62->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (jx_h62->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) jx_h62->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) jx_h62->vblank = v4l2_ctrl_new_std(handler, &jx_h62_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) JX_H62_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) exposure_max = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) //exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) jx_h62->exposure = v4l2_ctrl_new_std(handler, &jx_h62_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) V4L2_CID_EXPOSURE, JX_H62_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) exposure_max, JX_H62_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) jx_h62->anal_gain = v4l2_ctrl_new_std(handler, &jx_h62_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* Digital gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) jx_h62->digi_gain = v4l2_ctrl_new_std(handler, &jx_h62_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) V4L2_CID_DIGITAL_GAIN, JX_H62_DIGI_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) JX_H62_DIGI_GAIN_MAX, JX_H62_DIGI_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) JX_H62_DIGI_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) jx_h62->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) &jx_h62_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ARRAY_SIZE(jx_h62_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) 0, 0, jx_h62_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) dev_err(&jx_h62->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) jx_h62->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) jx_h62->old_gain = ANALOG_GAIN_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static int jx_h62_check_sensor_id(struct jx_h62 *jx_h62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct device *dev = &jx_h62->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) u8 id_h = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) u8 id_l = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret = jx_h62_read_reg(client, JX_H62_PIDH_ADDR, &id_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ret |= jx_h62_read_reg(client, JX_H62_PIDL_ADDR, &id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (id_h != CHIP_ID_H && id_l != CHIP_ID_L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) dev_err(dev, "Wrong camera sensor id(0x%02x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) id_h, id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) dev_info(dev, "Detected jx_h62 (0x%02x%02x) sensor\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) id_h, id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static int jx_h62_configure_regulators(struct jx_h62 *jx_h62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) for (i = 0; i < JX_H62_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) jx_h62->supplies[i].supply = jx_h62_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return devm_regulator_bulk_get(&jx_h62->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) JX_H62_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) jx_h62->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static int jx_h62_parse_of(struct jx_h62 *jx_h62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct device *dev = &jx_h62->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) fwnode = of_fwnode_handle(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (rval <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) dev_warn(dev, " Get mipi lane num failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) jx_h62->lane_num = rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (1 == jx_h62->lane_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) jx_h62->pixel_rate = MIPI_FREQ * 2U * jx_h62->lane_num / 10U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) jx_h62->lane_num, jx_h62->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) dev_err(dev, "unsupported lane_num(%d)\n", jx_h62->lane_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static int jx_h62_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct jx_h62 *jx_h62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) jx_h62 = devm_kzalloc(dev, sizeof(*jx_h62), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (!jx_h62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) &jx_h62->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) &jx_h62->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) &jx_h62->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) &jx_h62->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) jx_h62->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) jx_h62->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) jx_h62->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (IS_ERR(jx_h62->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) jx_h62->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (IS_ERR(jx_h62->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) jx_h62->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (IS_ERR(jx_h62->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ret = jx_h62_configure_regulators(jx_h62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ret = jx_h62_parse_of(jx_h62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) jx_h62->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (!IS_ERR(jx_h62->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) jx_h62->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) pinctrl_lookup_state(jx_h62->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (IS_ERR(jx_h62->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) jx_h62->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) pinctrl_lookup_state(jx_h62->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (IS_ERR(jx_h62->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) mutex_init(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) sd = &jx_h62->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) v4l2_i2c_subdev_init(sd, client, &jx_h62_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ret = jx_h62_initialize_controls(jx_h62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ret = __jx_h62_power_on(jx_h62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ret = jx_h62_check_sensor_id(jx_h62, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) sd->internal_ops = &jx_h62_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) jx_h62->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ret = media_entity_pads_init(&sd->entity, 1, &jx_h62->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (strcmp(jx_h62->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) jx_h62->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) JX_H62_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ret = v4l2_async_register_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) __jx_h62_power_off(jx_h62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) v4l2_ctrl_handler_free(&jx_h62->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) mutex_destroy(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static int jx_h62_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct jx_h62 *jx_h62 = to_jx_h62(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) v4l2_ctrl_handler_free(&jx_h62->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) mutex_destroy(&jx_h62->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) __jx_h62_power_off(jx_h62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) static const struct of_device_id jx_h62_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) { .compatible = "soi,jx_h62" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) MODULE_DEVICE_TABLE(of, jx_h62_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static const struct i2c_device_id jx_h62_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) { "soi,jx_h62", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static struct i2c_driver jx_h62_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .name = JX_H62_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .pm = &jx_h62_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .of_match_table = of_match_ptr(jx_h62_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .probe = &jx_h62_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .remove = &jx_h62_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .id_table = jx_h62_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return i2c_add_driver(&jx_h62_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) i2c_del_driver(&jx_h62_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) MODULE_DESCRIPTION("SOI jx_h62 sensor driver by steven.ou");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags