^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * jx_f37 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * v0.0x01.0x04 support mirror/flip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define JX_F37_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define JX_F37_LANES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CHIP_ID_H 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CHIP_ID_L 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define JX_F37_PIDH_ADDR 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define JX_F37_PIDL_ADDR 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define JX_F37_REG_CTRL_MODE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define JX_F37_MODE_SLEEP_MODE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define JX_F37_MAX_SMPL_START 0x8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define JX_F37_SHORT_EXPO_REG 0x05 /* Exposure Bits 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define JX_F37_LONG_EXPO_HIGH_REG 0x02 /* Exposure Bits 8-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define JX_F37_LONG_EXPO_LOW_REG 0x01 /* Exposure Bits 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define JX_F37_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define JX_F37_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define JX_F37_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define JX_F37_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define JX_F37_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define JX_F37_SMPL_START_S_REG 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define JX_F37_SMPL_START_S_VAL 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define JX_F37_LONG_GAIN_REG 0x00 /* Bits 0 -7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ANALOG_GAIN_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ANALOG_GAIN_MAX 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ANALOG_GAIN_DEFAULT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define JX_F37_REG_HIGH_VTS 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define JX_F37_REG_LOW_VTS 0X22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define JX_F37_FETCH_HIGH_BYTE_VTS(VAL) (((VAL) >> 8) & 0xFF) /* 8-15 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define JX_F37_FETCH_LOW_BYTE_VTS(VAL) ((VAL) & 0xFF) /* 0-7 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define JX_F37_FLIP_MIRROR_REG 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_NULL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_DELAY 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define JX_F37_NAME "jx_f37"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const char * const jx_f37_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "vcc2v8_dvp", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "vcc1v8_dvp", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define JX_F37_NUM_SUPPLIES ARRAY_SIZE(jx_f37_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct jx_f37_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct jx_f37 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct regulator_bulk_data supplies[JX_F37_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const struct jx_f37_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define to_jx_f37(sd) container_of(sd, struct jx_f37, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct regval jx_f37_1080p_linear_1lane_30fps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {0x12, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {0x48, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {0x48, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0x0E, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0x0F, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0x10, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0x11, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x0D, 0xF0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x5F, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x60, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x58, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0x57, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x9D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x20, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x21, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x22, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x23, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x24, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x25, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x26, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x27, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x28, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x29, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x2A, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x2B, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x2C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x2D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x2E, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x2F, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x41, 0xC8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x42, 0x3B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x47, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x76, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x77, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x1D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x1E, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x6C, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x6E, 0x2C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x70, 0xD0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x71, 0xD3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x72, 0xD4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x73, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x74, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x78, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x89, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x6B, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x86, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x31, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x32, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x33, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x34, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x35, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3A, 0xAF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3C, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3D, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3E, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3F, 0xA8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x40, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x56, 0xB2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x59, 0x9E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x5A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x85, 0x4D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x8A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x91, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x9B, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x9C, 0xE1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0xA9, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x5B, 0xB0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x5C, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x5D, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x5E, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x62, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x63, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x64, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x65, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x67, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x66, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x68, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x69, 0x7C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x6A, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x7A, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x82, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x8F, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0xAE, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x13, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x96, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x4A, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x7E, 0xCD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x50, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x49, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0xAF, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x80, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x7B, 0x4A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x7C, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x7F, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x8C, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x8D, 0xC7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x8E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x8B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x0C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x81, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x19, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x46, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x12, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x48, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x48, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {REG_NULL, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const struct regval jx_f37_1080p_hdr_1lane_15fps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x12, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x48, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x48, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x0E, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x0F, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x10, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x11, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x0D, 0xF0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x5F, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x60, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x58, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x57, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x9D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x20, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x21, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x22, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x23, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x24, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x25, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x26, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x27, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x28, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x29, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x2A, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x2B, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x2C, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x2D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x2E, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x2F, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x41, 0xC5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x42, 0x3B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x47, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x76, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x77, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x80, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0xAF, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0xAB, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x46, 0x14}, /* Short frame use the same gain as long frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x1D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x1E, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x6C, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x6E, 0x2C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x70, 0xD0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x71, 0xD3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x72, 0xD4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x73, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x74, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x78, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x89, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x6B, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x86, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x31, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x32, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x33, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x34, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x35, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x3A, 0xAF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x3B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3C, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3D, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3E, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3F, 0xA8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x40, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x56, 0xB2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x59, 0x9E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x5A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x85, 0x4D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x8A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x91, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x9B, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x9C, 0xE1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0xA9, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x5B, 0xB0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x5C, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x5D, 0xF6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x5E, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x62, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x63, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x64, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x65, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x67, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x66, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x68, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x69, 0x7C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x6A, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x7A, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x82, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x8F, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0xAE, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x13, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x96, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x4A, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x7E, 0xCD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x50, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x49, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0xAF, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x7B, 0x4A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x7C, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x7F, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x8C, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x8D, 0xC7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x8E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x8B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x0C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x81, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x19, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x07, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x1B, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x06, JX_F37_MAX_SMPL_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x03, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x04, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x12, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x48, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x48, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {REG_NULL, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const struct jx_f37_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .exp_def = 0x00ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .hts_def = 0x0500 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .vts_def = 0x0465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .reg_list = jx_f37_1080p_linear_1lane_30fps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .denominator = 150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .exp_def = 0x00ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .hts_def = 0x0500 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .vts_def = 0x08ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .reg_list = jx_f37_1080p_hdr_1lane_15fps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define JX_F37_LINK_FREQ_432MHZ (432000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define JX_F37_PIXEL_RATE (JX_F37_LINK_FREQ_432MHZ * 2 * JX_F37_LANES / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) JX_F37_LINK_FREQ_432MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static inline u32 jx_f37_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return DIV_ROUND_UP(cycles, JX_F37_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int jx_f37_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) //dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) // "jx_f37 write reg(0x%x val:0x%x)\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) "jx_f37 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int jx_f37_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 i, delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (regs[i].addr == REG_DELAY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) delay_us = jx_f37_cal_delay(500 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = jx_f37_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int jx_f37_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) "jx_f37 read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static void jx_f37_update_cur_mode_locked(struct jx_f37 *jx_f37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) const struct jx_f37_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) jx_f37->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) __v4l2_ctrl_modify_range(jx_f37->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) __v4l2_ctrl_modify_range(jx_f37->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) JX_F37_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int jx_f37_set_hdr_mode_locked(struct jx_f37 *jx_f37, u32 hdr_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * found the first one that match hdr_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * the fmt size shall hand over to .set_fmt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (supported_modes[i].hdr_mode != hdr_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) jx_f37_update_cur_mode_locked(jx_f37, &supported_modes[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static ssize_t set_hdr_mode(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct jx_f37 *jx_f37 = to_jx_f37(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) mutex_lock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = kstrtoint(buf, 0, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ret = jx_f37_set_hdr_mode_locked(jx_f37, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev_err(dev, "hdr_mode(%d) is not supported\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_info(dev, "Set hdr mode to: %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mutex_unlock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static ssize_t show_hdr_mode(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct jx_f37 *jx_f37 = to_jx_f37(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return sprintf(buf, "%u\n", jx_f37->cur_mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static struct device_attribute attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) __ATTR(cam_hdr_mode, 0600, show_hdr_mode, set_hdr_mode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int add_sysfs_interfaces(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) for (i = 0; i < ARRAY_SIZE(attributes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (device_create_file(dev, attributes + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) goto undo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) undo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) for (i--; i >= 0 ; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) device_remove_file(dev, attributes + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev_err(dev, "%s: failed to create sysfs interface\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int jx_f37_get_reso_dist(const struct jx_f37_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static const struct jx_f37_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) jx_f37_find_best_fit(struct jx_f37 *jx_f37, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 cur_hdr_mode = jx_f37->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Do not change the hdr_mode setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (supported_modes[i].hdr_mode != cur_hdr_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dist = jx_f37_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int jx_f37_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct jx_f37 *jx_f37 = to_jx_f37(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) const struct jx_f37_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) mutex_lock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mode = jx_f37_find_best_fit(jx_f37, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) mutex_unlock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) jx_f37_update_cur_mode_locked(jx_f37, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) mutex_unlock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int jx_f37_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct jx_f37 *jx_f37 = to_jx_f37(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) const struct jx_f37_mode *mode = jx_f37->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) mutex_lock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) mutex_unlock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) mutex_unlock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int jx_f37_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static int jx_f37_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static void jx_f37_get_module_inf(struct jx_f37 *jx_f37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) strlcpy(inf->base.sensor, JX_F37_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) strlcpy(inf->base.module, jx_f37->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) strlcpy(inf->base.lens, jx_f37->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int jx_f37_set_hdrae(struct jx_f37 *jx_f37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct i2c_client *client = jx_f37->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u32 fh, l_exp_max, l_exp_min, s_exp_max, s_exp_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u32 l_a_gain, m_a_gain, s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!jx_f37->has_init_exp && !jx_f37->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) jx_f37->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) jx_f37->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_dbg(&client->dev, "jx_f37 don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* The frame height, vts, default value is: 0x08ca */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) fh = jx_f37->vblank->cur.val + jx_f37->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * Restriction:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * Short / Long exp line shall be odd value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * 0x00 <= Reg_saec1 * 2 < Smpl_Start_S * 2 - 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * 0x00 <= Reg_saec1 <= Smpl_Start_S - 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * 0x01 <= short_exp = Reg_saec1 * 2 + 1 <= Smpl_Start_S * 2 - 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * 0x01 <= long_exp < fh - Smpl_Start_S * 2 - 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * short_exp + long_exp < fh - 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) l_a_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) m_a_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) s_a_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) "hdrae req: exp (0x%x, 0x%x, 0x%x), gain(0x%x: 0x%x, 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) l_exp_time, m_exp_time, s_exp_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) l_a_gain, m_a_gain, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (jx_f37->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) //2 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) l_a_gain = m_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) //s_exp_time = clamp_val(s_exp_time, 1, MAX_SMPL_START * 2 - 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) //smpl_start = (s_exp_time + 3) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) //jx_f37_write_reg(client, 0xc0, JX_F37_SMPL_START_S_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) //jx_f37_write_reg(client, 0xc1, smpl_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) s_exp_min = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) s_exp_max = JX_F37_MAX_SMPL_START * 2 - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) s_exp_time = clamp_val(s_exp_time, s_exp_min, s_exp_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) s_exp_time |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) jx_f37_write_reg(client, 0xc0, JX_F37_SHORT_EXPO_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) jx_f37_write_reg(client, 0xc1, (s_exp_time - 1) / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) l_exp_min = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) l_exp_max = fh - JX_F37_MAX_SMPL_START * 2 - 6 - 1; /* Make it odd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) l_exp_time = clamp_val(l_exp_time, l_exp_min, l_exp_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) l_exp_time |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) jx_f37_write_reg(client, 0xc2, JX_F37_LONG_EXPO_HIGH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) jx_f37_write_reg(client, 0xc3, JX_F37_FETCH_HIGH_BYTE_EXP(l_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) jx_f37_write_reg(client, 0xc4, JX_F37_LONG_EXPO_LOW_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) jx_f37_write_reg(client, 0xc5, JX_F37_FETCH_LOW_BYTE_EXP(l_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Short frame gain is ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) jx_f37_write_reg(client, 0xc6, JX_F37_LONG_GAIN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) jx_f37_write_reg(client, 0xc7, l_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* Trigger group write function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) jx_f37_write_reg(client, 0x1f, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) "hdrae final: smpl_start: %d, exp (0x%x, 0x%x), gain(0x%x: 0x%x)\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) " l_exp[%d, %d], s_exp[%d, %d], fh = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) JX_F37_MAX_SMPL_START, l_exp_time, s_exp_time, l_a_gain, s_a_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) l_exp_min, l_exp_max, s_exp_min, s_exp_max, fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static long jx_f37_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct jx_f37 *jx_f37 = to_jx_f37(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = jx_f37_set_hdrae(jx_f37, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) jx_f37_get_module_inf(jx_f37, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) hdr->hdr_mode = jx_f37->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) w = jx_f37->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) h = jx_f37->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) jx_f37_update_cur_mode_locked(jx_f37, &supported_modes[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dev_err(&jx_f37->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static long jx_f37_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ret = jx_f37_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ret = jx_f37_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ret = jx_f37_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ret = jx_f37_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static int jx_f37_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct jx_f37 *jx_f37 = to_jx_f37(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) const struct jx_f37_mode *mode = jx_f37->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) mutex_lock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) mutex_unlock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static int jx_f37_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct jx_f37 *jx_f37 = to_jx_f37(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) const struct jx_f37_mode *mode = jx_f37->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) val = 1 << (JX_F37_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) else if (mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) val = 1 << (JX_F37_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) config->type = V4L2_MBUS_CSI2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static int __jx_f37_start_stream(struct jx_f37 *jx_f37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ret = jx_f37_write_array(jx_f37->client, jx_f37->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) mutex_unlock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ret = v4l2_ctrl_handler_setup(&jx_f37->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) mutex_lock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (jx_f37->has_init_exp && jx_f37->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ret = jx_f37_ioctl(&jx_f37->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) &jx_f37->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) dev_err(&jx_f37->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) jx_f37->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static int __jx_f37_stop_stream(struct jx_f37 *jx_f37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ret = jx_f37_read_reg(jx_f37->client, JX_F37_REG_CTRL_MODE, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dev_err(&jx_f37->client->dev, "%s: read reg failed, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return jx_f37_write_reg(jx_f37->client, JX_F37_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) val | JX_F37_MODE_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static int jx_f37_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct jx_f37 *jx_f37 = to_jx_f37(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct i2c_client *client = jx_f37->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) mutex_lock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (on == jx_f37->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret = __jx_f37_start_stream(jx_f37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) dev_info(&client->dev, "hdr_mode %d\n", jx_f37->cur_mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) __jx_f37_stop_stream(jx_f37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) jx_f37->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) mutex_unlock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static int jx_f37_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct jx_f37 *jx_f37 = to_jx_f37(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct i2c_client *client = jx_f37->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) mutex_lock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (jx_f37->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * Enter sleep state to make sure not mipi output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * during rkisp init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) __jx_f37_stop_stream(jx_f37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) jx_f37->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) jx_f37->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) mutex_unlock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static int __jx_f37_power_on(struct jx_f37 *jx_f37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct device *dev = &jx_f37->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ret = clk_set_rate(jx_f37->xvclk, JX_F37_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (clk_get_rate(jx_f37->xvclk) != JX_F37_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ret = clk_prepare_enable(jx_f37->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (!IS_ERR(jx_f37->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) gpiod_set_value_cansleep(jx_f37->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ret = regulator_bulk_enable(JX_F37_NUM_SUPPLIES, jx_f37->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* According to datasheet, at least 10ms for reset duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) usleep_range(10 * 1000, 15 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (!IS_ERR(jx_f37->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) gpiod_set_value_cansleep(jx_f37->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (!IS_ERR(jx_f37->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) gpiod_set_value_cansleep(jx_f37->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) delay_us = jx_f37_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) clk_disable_unprepare(jx_f37->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static void __jx_f37_power_off(struct jx_f37 *jx_f37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (!IS_ERR(jx_f37->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) gpiod_set_value_cansleep(jx_f37->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) clk_disable_unprepare(jx_f37->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (!IS_ERR(jx_f37->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) gpiod_set_value_cansleep(jx_f37->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) regulator_bulk_disable(JX_F37_NUM_SUPPLIES, jx_f37->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static int jx_f37_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct jx_f37 *jx_f37 = to_jx_f37(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return __jx_f37_power_on(jx_f37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static int jx_f37_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct jx_f37 *jx_f37 = to_jx_f37(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) __jx_f37_power_off(jx_f37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static int jx_f37_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct jx_f37 *jx_f37 = to_jx_f37(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) const struct jx_f37_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) mutex_lock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) mutex_unlock(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) static int jx_f37_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) fie->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static const struct dev_pm_ops jx_f37_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) SET_RUNTIME_PM_OPS(jx_f37_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) jx_f37_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static const struct v4l2_subdev_internal_ops jx_f37_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .open = jx_f37_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static const struct v4l2_subdev_core_ops jx_f37_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .s_power = jx_f37_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .ioctl = jx_f37_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .compat_ioctl32 = jx_f37_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static const struct v4l2_subdev_video_ops jx_f37_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .s_stream = jx_f37_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .g_frame_interval = jx_f37_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .g_mbus_config = jx_f37_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static const struct v4l2_subdev_pad_ops jx_f37_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .enum_mbus_code = jx_f37_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .enum_frame_size = jx_f37_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .enum_frame_interval = jx_f37_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .get_fmt = jx_f37_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .set_fmt = jx_f37_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static const struct v4l2_subdev_ops jx_f37_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .core = &jx_f37_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .video = &jx_f37_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .pad = &jx_f37_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static int jx_f37_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct jx_f37 *jx_f37 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct jx_f37, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct i2c_client *client = jx_f37->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) max = jx_f37->cur_mode->height + ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) __v4l2_ctrl_modify_range(jx_f37->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) jx_f37->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) jx_f37->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) jx_f37->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev_dbg(&client->dev, "set expo: val: %d\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ret = jx_f37_write_reg(jx_f37->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) JX_F37_LONG_EXPO_HIGH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) JX_F37_FETCH_HIGH_BYTE_EXP(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ret |= jx_f37_write_reg(jx_f37->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) JX_F37_LONG_EXPO_LOW_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) JX_F37_FETCH_LOW_BYTE_EXP(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dev_dbg(&client->dev, "set a-gain: val: %d\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ret |= jx_f37_write_reg(jx_f37->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) JX_F37_LONG_GAIN_REG, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) case V4L2_CID_DIGITAL_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ret = jx_f37_read_reg(jx_f37->client, JX_F37_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) val |= BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) val &= ~BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) ret |= jx_f37_write_reg(jx_f37->client, JX_F37_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ret = jx_f37_read_reg(jx_f37->client, JX_F37_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) val |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) val &= ~BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ret |= jx_f37_write_reg(jx_f37->client, JX_F37_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dev_dbg(&client->dev, "set vblank: val: %d\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ret |= jx_f37_write_reg(jx_f37->client, JX_F37_REG_HIGH_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) JX_F37_FETCH_HIGH_BYTE_VTS((ctrl->val + jx_f37->cur_mode->height)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ret |= jx_f37_write_reg(jx_f37->client, JX_F37_REG_LOW_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) JX_F37_FETCH_LOW_BYTE_VTS((ctrl->val + jx_f37->cur_mode->height)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static const struct v4l2_ctrl_ops jx_f37_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .s_ctrl = jx_f37_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static int jx_f37_initialize_controls(struct jx_f37 *jx_f37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) const struct jx_f37_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) handler = &jx_f37->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) mode = jx_f37->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) handler->lock = &jx_f37->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) 0, JX_F37_PIXEL_RATE, 1, JX_F37_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) jx_f37->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (jx_f37->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) jx_f37->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) jx_f37->vblank = v4l2_ctrl_new_std(handler, &jx_f37_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) JX_F37_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) exposure_max = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) jx_f37->exposure = v4l2_ctrl_new_std(handler, &jx_f37_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) V4L2_CID_EXPOSURE, JX_F37_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) exposure_max, JX_F37_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) jx_f37->anal_gain = v4l2_ctrl_new_std(handler, &jx_f37_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) v4l2_ctrl_new_std(handler, &jx_f37_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) v4l2_ctrl_new_std(handler, &jx_f37_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev_err(&jx_f37->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) jx_f37->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static int jx_f37_check_sensor_id(struct jx_f37 *jx_f37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) struct device *dev = &jx_f37->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) u8 id_h = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) u8 id_l = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) ret = jx_f37_read_reg(client, JX_F37_PIDH_ADDR, &id_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) ret |= jx_f37_read_reg(client, JX_F37_PIDL_ADDR, &id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (id_h != CHIP_ID_H && id_l != CHIP_ID_L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) dev_err(dev, "Wrong camera sensor id(0x%02x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) id_h, id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) dev_info(dev, "Detected jx_f37 (0x%02x%02x) sensor\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) id_h, id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static int jx_f37_configure_regulators(struct jx_f37 *jx_f37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) for (i = 0; i < JX_F37_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) jx_f37->supplies[i].supply = jx_f37_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return devm_regulator_bulk_get(&jx_f37->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) JX_F37_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) jx_f37->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static int jx_f37_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) struct jx_f37 *jx_f37;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) jx_f37 = devm_kzalloc(dev, sizeof(*jx_f37), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (!jx_f37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) &jx_f37->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) &jx_f37->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) &jx_f37->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) &jx_f37->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) jx_f37->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (ret || (jx_f37_set_hdr_mode_locked(jx_f37, hdr_mode))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) jx_f37->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) dev_warn(dev, "Bad dts hdr_mode value! Use default mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) jx_f37->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (IS_ERR(jx_f37->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) jx_f37->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (IS_ERR(jx_f37->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) jx_f37->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (IS_ERR(jx_f37->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) ret = jx_f37_configure_regulators(jx_f37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) mutex_init(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) sd = &jx_f37->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) v4l2_i2c_subdev_init(sd, client, &jx_f37_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) ret = jx_f37_initialize_controls(jx_f37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) ret = __jx_f37_power_on(jx_f37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) ret = jx_f37_check_sensor_id(jx_f37, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) sd->internal_ops = &jx_f37_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) jx_f37->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) ret = media_entity_pads_init(&sd->entity, 1, &jx_f37->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (strcmp(jx_f37->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) jx_f37->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) JX_F37_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) add_sysfs_interfaces(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) dev_info(dev, "probe successful\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) __jx_f37_power_off(jx_f37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) v4l2_ctrl_handler_free(&jx_f37->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) mutex_destroy(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) dev_err(dev, "probe failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static int jx_f37_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) struct jx_f37 *jx_f37 = to_jx_f37(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) v4l2_ctrl_handler_free(&jx_f37->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) mutex_destroy(&jx_f37->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) __jx_f37_power_off(jx_f37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static const struct of_device_id jx_f37_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) { .compatible = "soi,jx_f37" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) MODULE_DEVICE_TABLE(of, jx_f37_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) static const struct i2c_device_id jx_f37_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) { "soi,jx_f37", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) static struct i2c_driver jx_f37_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .name = JX_F37_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .pm = &jx_f37_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .of_match_table = of_match_ptr(jx_f37_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .probe = &jx_f37_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .remove = &jx_f37_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .id_table = jx_f37_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return i2c_add_driver(&jx_f37_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) i2c_del_driver(&jx_f37_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) MODULE_DESCRIPTION("SOI jx_f37 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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