^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * imx586 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * V0.0X01.0X00 init version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) //#define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "otp_eeprom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX586_LINK_FREQ_400 400000000 // 800Mbps per lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX586_LINK_FREQ_625 625000000 // 1250Mbps per lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX586_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PIXEL_RATE_WITH_848M_10BIT (IMX586_LINK_FREQ_400 * 2 / 10 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PIXEL_RATE_WITH_848M_12BIT (IMX586_LINK_FREQ_400 * 2 / 12 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX586_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CHIP_ID 0x0586
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX586_REG_CHIP_ID_H 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX586_REG_CHIP_ID_L 0x0017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX586_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX586_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX586_MODE_STREAMING 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX586_REG_EXPOSURE_H 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX586_REG_EXPOSURE_L 0x0203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX586_EXPOSURE_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX586_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX586_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX586_REG_GAIN_H 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX586_REG_GAIN_L 0x0205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX586_GAIN_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX586_GAIN_MAX 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX586_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX586_GAIN_DEFAULT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX586_REG_DGAIN 0x3130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX586_DGAIN_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX586_REG_DGAINGR_H 0x020e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX586_REG_DGAINGR_L 0x020f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX586_REG_DGAINR_H 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX586_REG_DGAINR_L 0x0211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX586_REG_DGAINB_H 0x0212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX586_REG_DGAINB_L 0x0213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX586_REG_DGAINGB_H 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX586_REG_DGAINGB_L 0x0215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX586_REG_GAIN_GLOBAL_H 0x3ffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX586_REG_GAIN_GLOBAL_L 0x3ffd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) //#define IMX586_REG_TEST_PATTERN_H 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX586_REG_TEST_PATTERN 0x0601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX586_TEST_PATTERN_ENABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX586_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX586_REG_VTS_H 0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX586_REG_VTS_L 0x0341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX586_FLIP_MIRROR_REG 0x0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX586_MIRROR_BIT_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMX586_FLIP_BIT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX586_FETCH_EXP_H(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX586_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX586_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX586_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX586_FETCH_DGAIN_H(VAL) (((VAL) >> 8) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX586_FETCH_DGAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX586_FETCH_RHS1_H(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX586_FETCH_RHS1_M(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX586_FETCH_RHS1_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX586_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX586_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX586_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX586_NAME "imx586"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const char * const imx586_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX586_NUM_SUPPLIES ARRAY_SIZE(imx586_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct other_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 data_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 data_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct imx586_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) const struct regval *global_reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const struct other_data *spd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct imx586 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct regulator_bulk_data supplies[IMX586_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct v4l2_ctrl *h_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct v4l2_ctrl *v_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const struct imx586_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 cur_pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 cur_link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct otp_info *otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 spd_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define to_imx586(sd) container_of(sd, struct imx586, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *IMX586LQR All-pixel scan CSI-2_4lane 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *AD:10bit Output:10bit 1696Mbps Master Mode 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct regval imx586_linear_10bit_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* External Clock Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x0136, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x0137, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Register version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3C7E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3C7F, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Signaling mode setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x0111, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*Global Setting*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x380C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3C00, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3C01, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3C02, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3C03, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3C04, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3C05, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3C06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3C07, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3C08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3C09, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3C0A, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3C0B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3C0C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3C0D, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3C0E, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3C0F, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3F88, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3F8E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x5282, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x9004, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x9200, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x9201, 0xA7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x9202, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x9203, 0xAA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x9204, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x9205, 0xAD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x9206, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x9207, 0xB0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x9208, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x9209, 0xB3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x920A, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x920B, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x920C, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x920D, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x920E, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x920F, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x9210, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x9211, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x9212, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x9213, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x9214, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x9215, 0x3A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x9216, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x9217, 0x3C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x9218, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x9219, 0x3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x921A, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x921B, 0x3E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x921C, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x921D, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x921E, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x921F, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x9222, 0xC4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x9223, 0x4B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x9224, 0xC4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x9225, 0x4C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x9226, 0xC4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x9227, 0x4D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x9810, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x9814, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x99B2, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x99B3, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x99B4, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x99B5, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x99B6, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x99E4, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x99E5, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x99E6, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x99E7, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x99E8, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x99E9, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x99EA, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x99EB, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x99EC, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x99ED, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0xA569, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0xA679, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0xC020, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0xC61D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0xC625, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0xC638, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0xC63B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0xE286, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0xE2A6, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0xE2C6, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0xBCF1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*Image Quality adjustment setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x9852, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x9954, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0xA7AD, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0xA7CB, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0xAE09, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0xAE0A, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0xAE12, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0xAE13, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0xAE15, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0xAE16, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0xAF05, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0xB07C, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const struct regval imx586_linear_10bit_4000x3000_30fps_nopd_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* MIPI output setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x0112, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x0113, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Line Length PCK Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x0342, 0x23}, // 8976
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x0343, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Frame Length Lines Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x0340, 0x0B}, // 3064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x0341, 0xF8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* ROI Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x0348, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x0349, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x034A, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x034B, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Mode Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x0220, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x0222, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x0900, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x0901, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x0902, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x3140, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x3246, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x3247, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x3F15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Digital Crop & Scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x040A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x040B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x040C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x040D, 0xA0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x040E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x040F, 0xB8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Output Size Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x034C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x034D, 0xA0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x034E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x034F, 0xB8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Clock Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x0303, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x0305, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x0306, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x0307, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x030B, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x030D, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x030E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x030F, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x0310, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Other Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x3620, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x3621, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x3C11, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x3C12, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x3C13, 0x2D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x3F0C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x3F14, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x3F80, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x3F81, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x3F8C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x3F8D, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x3FF8, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x3FF9, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x3FFE, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x3FFF, 0x6C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Integration Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x0202, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x0203, 0xC4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x0224, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x0225, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x3FE0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3FE1, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Gain Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x0204, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x0205, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x0216, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x0217, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x0218, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x0219, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x020E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x020F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x0210, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x0212, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x0213, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x0214, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x0215, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x3FE2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x3FE3, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x3FE4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x3FE5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* PDAF TYPE1 Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3E20, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3E37, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const struct regval imx586_linear_10bit_full_raw_6fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* MIPI output setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x0112, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x0113, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Line Length PCK Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x0342, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x0343, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Frame Length Lines Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x0340, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x0341, 0xAC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* ROI Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x0348, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x0349, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x034A, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x034B, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Mode Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x0220, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x0222, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x0900, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x0901, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x0902, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x3140, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x3246, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3247, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x3F15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Digital Crop & Scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x040A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x040B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x040C, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x040D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x040E, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x040F, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Output Size Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x034C, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x034D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x034E, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x034F, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Clock Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x0303, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x0305, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x0306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x0307, 0xEE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x030B, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x030D, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x030E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x030F, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x0310, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Other Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x3620, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x3621, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x3C11, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x3C12, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x3C13, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x3F0C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x3F14, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x3F80, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x3F81, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x3F8C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x3F8D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x3FF8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x3FF9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x3FFE, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x3FFF, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Integration Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x0202, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x0203, 0x7C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x0224, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x0225, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x3FE0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x3FE1, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Gain Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x0204, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x0205, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x0216, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x0217, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x0218, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x0219, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x020E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x020F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x0210, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x0212, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x0213, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x0214, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x0215, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x3FE2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x3FE3, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x3FE4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x3FE5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* PDAF TYPE1 Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x3E20, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x3E37, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const struct regval imx586_linear_10bit_full_remosaic_6fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* MIPI output setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x0112, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x0113, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Line Length PCK Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x0342, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x0343, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Frame Length Lines Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x0340, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x0341, 0xAC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* ROI Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x0348, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x0349, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x034A, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x034B, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Mode Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x0220, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x0222, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x0900, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x0901, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x0902, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x3140, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x3246, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x3247, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x3F15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Digital Crop & Scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x040A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x040B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x040C, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x040D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x040E, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x040F, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Output Size Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x034C, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x034D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x034E, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x034F, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Clock Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0x0303, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x0305, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x0306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x0307, 0xEE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x030B, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x030D, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x030E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x030F, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x0310, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Other Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x3620, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x3621, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x3C11, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x3C12, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x3C13, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x3F0C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x3F14, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x3F80, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x3F81, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x3F8C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x3F8D, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x3FF8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x3FF9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {0x3FFE, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {0x3FFF, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Integration Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {0x0202, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {0x0203, 0x7C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {0x0224, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {0x0225, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {0x3FE0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0x3FE1, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Gain Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {0x0204, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {0x0205, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {0x0216, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {0x0217, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {0x0218, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {0x0219, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {0x020E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {0x020F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {0x0210, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x0212, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x0213, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x0214, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x0215, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {0x3FE2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {0x3FE3, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {0x3FE4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {0x3FE5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* PDAF TYPE1 Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {0x3E20, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {0x3E37, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static const struct regval imx586_linear_10bit_full_remosaic_10fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* MIPI output setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {0x0112, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {0x0113, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* Line Length PCK Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {0x0342, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {0x0343, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Frame Length Lines Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {0x0340, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {0x0341, 0xAC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* ROI Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {0x0348, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {0x0349, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {0x034A, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {0x034B, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* Mode Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {0x0220, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {0x0222, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {0x0900, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {0x0901, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {0x0902, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {0x3140, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {0x3246, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {0x3247, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {0x3F15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* Digital Crop & Scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {0x040A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {0x040B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {0x040C, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {0x040D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {0x040E, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {0x040F, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Output Size Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {0x034C, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {0x034D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {0x034E, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {0x034F, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Clock Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {0x0303, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {0x0305, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {0x0306, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {0x0307, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0x030B, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0x030D, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0x030E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0x030F, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {0x0310, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Other Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {0x3620, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {0x3621, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {0x3C11, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {0x3C12, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {0x3C13, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {0x3F0C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {0x3F14, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {0x3F80, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {0x3F81, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0x3F8C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {0x3F8D, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {0x3FF8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {0x3FF9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {0x3FFE, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {0x3FFF, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* Integration Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {0x0202, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {0x0203, 0x7C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {0x0224, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {0x0225, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {0x3FE0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {0x3FE1, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Gain Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {0x0204, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {0x0205, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {0x0216, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {0x0217, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {0x0218, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {0x0219, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {0x020E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {0x020F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {0x0210, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {0x0212, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {0x0213, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {0x0214, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {0x0215, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {0x3FE2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {0x3FE3, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {0x3FE4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {0x3FE5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* PDAF TYPE1 Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {0x3E20, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {0x3E37, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static const struct imx586_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .width = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .height = 3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .exp_def = 0x0B00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .hts_def = 0x2310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .vts_def = 0x0BF8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .global_reg_list = imx586_linear_10bit_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .reg_list = imx586_linear_10bit_4000x3000_30fps_nopd_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .width = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .height = 6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .denominator = 64100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .exp_def = 0x0B00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .hts_def = 0x3970,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .vts_def = 0x17AC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .global_reg_list = imx586_linear_10bit_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .reg_list = imx586_linear_10bit_full_raw_6fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .width = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .height = 6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .denominator = 64100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .exp_def = 0x0B00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .hts_def = 0x3970,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .vts_def = 0x17AC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .global_reg_list = imx586_linear_10bit_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .reg_list = imx586_linear_10bit_full_remosaic_6fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .width = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .height = 6000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .denominator = 97000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .exp_def = 0x0B00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .hts_def = 0x3970,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .vts_def = 0x17AC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .global_reg_list = imx586_linear_10bit_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .reg_list = imx586_linear_10bit_full_remosaic_10fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static const s64 link_freq_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) IMX586_LINK_FREQ_400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) IMX586_LINK_FREQ_625,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static const char * const imx586_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) "Solid color",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) "100% color bars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) "Fade to grey color bars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) "PN9"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static int imx586_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) int len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static int imx586_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (unlikely(regs[i].addr == REG_DELAY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) usleep_range(regs[i].val, regs[i].val * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ret = imx586_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) IMX586_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static int imx586_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (ret == ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (ret != ARRAY_SIZE(msgs) && i == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int imx586_get_reso_dist(const struct imx586_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static const struct imx586_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) imx586_find_best_fit(struct imx586 *imx586, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) for (i = 0; i < imx586->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dist = imx586_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static int imx586_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct imx586 *imx586 = to_imx586(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) const struct imx586_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) mutex_lock(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) mode = imx586_find_best_fit(imx586, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) mutex_unlock(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) imx586->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) __v4l2_ctrl_modify_range(imx586->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) __v4l2_ctrl_modify_range(imx586->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) IMX586_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) __v4l2_ctrl_s_ctrl(imx586->vblank, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) __v4l2_ctrl_s_ctrl(imx586->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / 10 * 2 * IMX586_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) __v4l2_ctrl_s_ctrl_int64(imx586->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dev_info(&imx586->client->dev, "%s: mode->mipi_freq_idx(%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) __func__, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) mutex_unlock(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static int imx586_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct imx586 *imx586 = to_imx586(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) const struct imx586_mode *mode = imx586->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) mutex_lock(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) mutex_unlock(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (imx586->flip & IMX586_MIRROR_BIT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (imx586->flip & IMX586_FLIP_BIT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) } else if (imx586->flip & IMX586_FLIP_BIT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) fmt->format.code = MEDIA_BUS_FMT_SGBRG10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) mutex_unlock(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static int imx586_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct imx586 *imx586 = to_imx586(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) code->code = imx586->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static int imx586_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct imx586 *imx586 = to_imx586(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (fse->index >= imx586->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static int imx586_enable_test_pattern(struct imx586 *imx586, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) val = (pattern - 1) | IMX586_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) val = IMX586_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return imx586_write_reg(imx586->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) IMX586_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) IMX586_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static int imx586_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct imx586 *imx586 = to_imx586(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) const struct imx586_mode *mode = imx586->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) mutex_lock(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) mutex_unlock(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static int imx586_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct imx586 *imx586 = to_imx586(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) const struct imx586_mode *mode = imx586->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) val = 1 << (IMX586_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) val = 1 << (IMX586_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static void imx586_get_otp(struct otp_info *otp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) u32 i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) u32 w, h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* awb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (otp->awb_data.flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) inf->awb.flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) inf->awb.r_value = otp->awb_data.r_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) inf->awb.b_value = otp->awb_data.b_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) inf->awb.gr_value = otp->awb_data.g_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) inf->awb.gb_value = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) inf->awb.golden_r_value = otp->awb_data.r_golden;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) inf->awb.golden_b_value = otp->awb_data.b_golden;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) inf->awb.golden_gr_value = otp->awb_data.g_golden;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) inf->awb.golden_gb_value = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* lsc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (otp->lsc_data.flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) inf->lsc.flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) inf->lsc.width = otp->basic_data.size.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) inf->lsc.height = otp->basic_data.size.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) inf->lsc.table_size = otp->lsc_data.table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) for (i = 0; i < 289; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) inf->lsc.lsc_r[i] = (otp->lsc_data.data[i * 2] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) otp->lsc_data.data[i * 2 + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) inf->lsc.lsc_gr[i] = (otp->lsc_data.data[i * 2 + 578] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) otp->lsc_data.data[i * 2 + 579];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) inf->lsc.lsc_gb[i] = (otp->lsc_data.data[i * 2 + 1156] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) otp->lsc_data.data[i * 2 + 1157];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) inf->lsc.lsc_b[i] = (otp->lsc_data.data[i * 2 + 1734] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) otp->lsc_data.data[i * 2 + 1735];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* pdaf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (otp->pdaf_data.flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) inf->pdaf.flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) inf->pdaf.gainmap_width = otp->pdaf_data.gainmap_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) inf->pdaf.gainmap_height = otp->pdaf_data.gainmap_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) inf->pdaf.dcc_mode = otp->pdaf_data.dcc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) inf->pdaf.dcc_dir = otp->pdaf_data.dcc_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) inf->pdaf.dccmap_width = otp->pdaf_data.dccmap_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) inf->pdaf.dccmap_height = otp->pdaf_data.dccmap_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) w = otp->pdaf_data.gainmap_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) h = otp->pdaf_data.gainmap_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) for (i = 0; i < h; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) for (j = 0; j < w; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) inf->pdaf.gainmap[i * w + j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) (otp->pdaf_data.gainmap[(i * w + j) * 2] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) otp->pdaf_data.gainmap[(i * w + j) * 2 + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) w = otp->pdaf_data.dccmap_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) h = otp->pdaf_data.dccmap_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) for (i = 0; i < h; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) for (j = 0; j < w; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) inf->pdaf.dccmap[i * w + j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) (otp->pdaf_data.dccmap[(i * w + j) * 2] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) otp->pdaf_data.dccmap[(i * w + j) * 2 + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /* af */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (otp->af_data.flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) inf->af.flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) inf->af.dir_cnt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) inf->af.af_otp[0].vcm_start = otp->af_data.af_inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) inf->af.af_otp[0].vcm_end = otp->af_data.af_macro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) inf->af.af_otp[0].vcm_dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static void imx586_get_module_inf(struct imx586 *imx586,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct otp_info *otp = imx586->otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) strscpy(inf->base.sensor, IMX586_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) strscpy(inf->base.module, imx586->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) strscpy(inf->base.lens, imx586->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (otp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) imx586_get_otp(otp, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static int imx586_get_channel_info(struct imx586 *imx586, struct rkmodule_channel_info *ch_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) const struct imx586_mode *mode = imx586->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (ch_info->index == imx586->spd_id && mode->spd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) ch_info->vc = V4L2_MBUS_CSI2_CHANNEL_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ch_info->width = mode->spd->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) ch_info->height = mode->spd->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ch_info->bus_fmt = mode->spd->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ch_info->data_type = mode->spd->data_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ch_info->data_bit = mode->spd->data_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ch_info->vc = imx586->cur_mode->vc[ch_info->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) ch_info->width = imx586->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) ch_info->height = imx586->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ch_info->bus_fmt = imx586->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static long imx586_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct imx586 *imx586 = to_imx586(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) imx586_get_module_inf(imx586, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) hdr->hdr_mode = imx586->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) w = imx586->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) h = imx586->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) for (i = 0; i < imx586->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) imx586->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (i == imx586->cfg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) dev_err(&imx586->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) w = imx586->cur_mode->hts_def -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) imx586->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) h = imx586->cur_mode->vts_def -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) imx586->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) __v4l2_ctrl_modify_range(imx586->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) __v4l2_ctrl_modify_range(imx586->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) IMX586_VTS_MAX -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) imx586->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (imx586->cur_mode->bus_fmt ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) MEDIA_BUS_FMT_SRGGB10_1X10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) imx586->cur_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) imx586->cur_pixel_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) PIXEL_RATE_WITH_848M_10BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) } else if (imx586->cur_mode->bus_fmt ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) MEDIA_BUS_FMT_SRGGB12_1X12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) imx586->cur_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) imx586->cur_pixel_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) PIXEL_RATE_WITH_848M_12BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) __v4l2_ctrl_s_ctrl_int64(imx586->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) imx586->cur_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) __v4l2_ctrl_s_ctrl(imx586->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) imx586->cur_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) ret = imx586_write_reg(imx586->client, IMX586_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) IMX586_REG_VALUE_08BIT, IMX586_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) ret = imx586_write_reg(imx586->client, IMX586_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) IMX586_REG_VALUE_08BIT, IMX586_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) ch_info = (struct rkmodule_channel_info *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ret = imx586_get_channel_info(imx586, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static long imx586_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ret = imx586_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) ret = imx586_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) ret = imx586_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ret = imx586_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ret = imx586_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) ret = imx586_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (!ch_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) ret = imx586_ioctl(sd, cmd, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) ret = copy_to_user(up, ch_info, sizeof(*ch_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) kfree(ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static int imx586_set_flip(struct imx586 *imx586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ret = imx586_read_reg(imx586->client, IMX586_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) IMX586_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (imx586->flip & IMX586_MIRROR_BIT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) val |= IMX586_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) val &= ~IMX586_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (imx586->flip & IMX586_FLIP_BIT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) val |= IMX586_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) val &= ~IMX586_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) ret |= imx586_write_reg(imx586->client, IMX586_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) IMX586_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static int __imx586_start_stream(struct imx586 *imx586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) ret = imx586_write_array(imx586->client, imx586->cur_mode->global_reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ret = imx586_write_array(imx586->client, imx586->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) imx586->cur_vts = imx586->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) ret = __v4l2_ctrl_handler_setup(&imx586->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (imx586->has_init_exp && imx586->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) ret = imx586_ioctl(&imx586->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) &imx586->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) dev_err(&imx586->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) imx586_set_flip(imx586);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return imx586_write_reg(imx586->client, IMX586_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) IMX586_REG_VALUE_08BIT, IMX586_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static int __imx586_stop_stream(struct imx586 *imx586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) return imx586_write_reg(imx586->client, IMX586_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) IMX586_REG_VALUE_08BIT, IMX586_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) static int imx586_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) struct imx586 *imx586 = to_imx586(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) struct i2c_client *client = imx586->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) imx586->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) imx586->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) DIV_ROUND_CLOSEST(imx586->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) imx586->cur_mode->max_fps.numerator));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) mutex_lock(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (on == imx586->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) ret = __imx586_start_stream(imx586);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) __imx586_stop_stream(imx586);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) imx586->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) mutex_unlock(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) static int imx586_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) struct imx586 *imx586 = to_imx586(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) struct i2c_client *client = imx586->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) mutex_lock(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (imx586->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) imx586->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) imx586->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) mutex_unlock(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static inline u32 imx586_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return DIV_ROUND_UP(cycles, IMX586_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) static int __imx586_power_on(struct imx586 *imx586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) struct device *dev = &imx586->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) ret = clk_set_rate(imx586->xvclk, IMX586_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (clk_get_rate(imx586->xvclk) != IMX586_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) dev_warn(dev, "xvclk mismatched, modes are based on 37.125MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ret = clk_prepare_enable(imx586->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (!IS_ERR(imx586->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) gpiod_set_value_cansleep(imx586->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ret = regulator_bulk_enable(IMX586_NUM_SUPPLIES, imx586->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if (!IS_ERR(imx586->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) gpiod_set_value_cansleep(imx586->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /* need wait 8ms to set register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) usleep_range(8000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (!IS_ERR(imx586->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) gpiod_set_value_cansleep(imx586->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) delay_us = imx586_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) clk_disable_unprepare(imx586->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static void __imx586_power_off(struct imx586 *imx586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) if (!IS_ERR(imx586->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) gpiod_set_value_cansleep(imx586->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) clk_disable_unprepare(imx586->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (!IS_ERR(imx586->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) gpiod_set_value_cansleep(imx586->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) regulator_bulk_disable(IMX586_NUM_SUPPLIES, imx586->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static int imx586_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) struct imx586 *imx586 = to_imx586(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return __imx586_power_on(imx586);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) static int imx586_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct imx586 *imx586 = to_imx586(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) __imx586_power_off(imx586);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static int imx586_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) struct imx586 *imx586 = to_imx586(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) const struct imx586_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) mutex_lock(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) mutex_unlock(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static int imx586_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) struct imx586 *imx586 = to_imx586(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (fie->index >= imx586->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) static const struct dev_pm_ops imx586_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) SET_RUNTIME_PM_OPS(imx586_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) imx586_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) static const struct v4l2_subdev_internal_ops imx586_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .open = imx586_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static const struct v4l2_subdev_core_ops imx586_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .s_power = imx586_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .ioctl = imx586_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .compat_ioctl32 = imx586_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) static const struct v4l2_subdev_video_ops imx586_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .s_stream = imx586_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .g_frame_interval = imx586_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) static const struct v4l2_subdev_pad_ops imx586_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .enum_mbus_code = imx586_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .enum_frame_size = imx586_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .enum_frame_interval = imx586_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .get_fmt = imx586_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .set_fmt = imx586_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .get_mbus_config = imx586_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static const struct v4l2_subdev_ops imx586_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .core = &imx586_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .video = &imx586_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .pad = &imx586_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) static int imx586_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) struct imx586 *imx586 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) struct imx586, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) struct i2c_client *client = imx586->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) u32 again = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) max = imx586->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) __v4l2_ctrl_modify_range(imx586->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) imx586->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) imx586->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) imx586->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) ret = imx586_write_reg(imx586->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) IMX586_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) IMX586_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) IMX586_FETCH_EXP_H(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) ret |= imx586_write_reg(imx586->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) IMX586_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) IMX586_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) IMX586_FETCH_EXP_L(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) dev_dbg(&client->dev, "set exposure 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) /* gain_reg = 1024 - 1024 / gain_ana
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * manual multiple 16 to add accuracy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) * then formula change to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) * gain_reg = 1024 - 1024 * 16 / (gain_ana * 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) if (ctrl->val > 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) ctrl->val = 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (ctrl->val < 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ctrl->val = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) again = 1024 - 1024 * 16 / ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) ret = imx586_write_reg(imx586->client, IMX586_REG_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) IMX586_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) IMX586_FETCH_AGAIN_H(again));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) ret |= imx586_write_reg(imx586->client, IMX586_REG_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) IMX586_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) IMX586_FETCH_AGAIN_L(again));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) dev_dbg(&client->dev, "set analog gain 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) ret = imx586_write_reg(imx586->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) IMX586_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) IMX586_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) (ctrl->val + imx586->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) ret |= imx586_write_reg(imx586->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) IMX586_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) IMX586_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) (ctrl->val + imx586->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) imx586->cur_vts = ctrl->val + imx586->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) dev_dbg(&client->dev, "set vblank 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) imx586->flip |= IMX586_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) imx586->flip &= ~IMX586_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) dev_dbg(&client->dev, "set hflip 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) imx586->flip |= IMX586_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) imx586->flip &= ~IMX586_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) dev_dbg(&client->dev, "set vflip 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) dev_dbg(&client->dev, "set testpattern 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) ret = imx586_enable_test_pattern(imx586, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) static const struct v4l2_ctrl_ops imx586_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .s_ctrl = imx586_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static int imx586_initialize_controls(struct imx586 *imx586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) const struct imx586_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) handler = &imx586->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) mode = imx586->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) handler->lock = &imx586->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) imx586->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ARRAY_SIZE(link_freq_items) - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) link_freq_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (imx586->cur_mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) imx586->cur_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) imx586->cur_pixel_rate = PIXEL_RATE_WITH_848M_10BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) } else if (imx586->cur_mode->bus_fmt == MEDIA_BUS_FMT_SRGGB12_1X12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) imx586->cur_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) imx586->cur_pixel_rate = PIXEL_RATE_WITH_848M_12BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) imx586->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) 0, PIXEL_RATE_WITH_848M_10BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) 1, imx586->cur_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) v4l2_ctrl_s_ctrl(imx586->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) imx586->cur_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) imx586->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) if (imx586->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) imx586->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) imx586->vblank = v4l2_ctrl_new_std(handler, &imx586_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) IMX586_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) imx586->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) imx586->exposure = v4l2_ctrl_new_std(handler, &imx586_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) V4L2_CID_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) IMX586_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) exposure_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) IMX586_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) imx586->anal_gain = v4l2_ctrl_new_std(handler, &imx586_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) V4L2_CID_ANALOGUE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) IMX586_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) IMX586_GAIN_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) IMX586_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) IMX586_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) imx586->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) &imx586_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) ARRAY_SIZE(imx586_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) 0, 0, imx586_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) imx586->h_flip = v4l2_ctrl_new_std(handler, &imx586_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) imx586->v_flip = v4l2_ctrl_new_std(handler, &imx586_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) imx586->flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) dev_err(&imx586->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) "Failed to init controls( %d )\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) imx586->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) imx586->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) static int imx586_check_sensor_id(struct imx586 *imx586,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) struct device *dev = &imx586->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) u16 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) u32 reg_H = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) u32 reg_L = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) ret = imx586_read_reg(client, IMX586_REG_CHIP_ID_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) IMX586_REG_VALUE_08BIT, ®_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) ret |= imx586_read_reg(client, IMX586_REG_CHIP_ID_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) IMX586_REG_VALUE_08BIT, ®_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) if (!(reg_H == (CHIP_ID >> 8) || reg_L == (CHIP_ID & 0xff))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) dev_info(dev, "detected imx586 %04x sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) static int imx586_configure_regulators(struct imx586 *imx586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) for (i = 0; i < IMX586_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) imx586->supplies[i].supply = imx586_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) return devm_regulator_bulk_get(&imx586->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) IMX586_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) imx586->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) static int imx586_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) struct imx586 *imx586;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) struct device_node *eeprom_ctrl_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) struct i2c_client *eeprom_ctrl_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) struct v4l2_subdev *eeprom_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) struct otp_info *otp_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) imx586 = devm_kzalloc(dev, sizeof(*imx586), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) if (!imx586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) &imx586->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) &imx586->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) &imx586->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) &imx586->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) hdr_mode = NO_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) dev_warn(dev, " Get hdr mode failed! no hdr default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) imx586->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) imx586->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) for (i = 0; i < imx586->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) imx586->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if (i == imx586->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) imx586->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) imx586->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (IS_ERR(imx586->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) imx586->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) if (IS_ERR(imx586->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) imx586->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) if (IS_ERR(imx586->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) ret = of_property_read_u32(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) "rockchip,spd-id",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) &imx586->spd_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) imx586->spd_id = PAD_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) "failed get spd_id, will not to use spd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) ret = imx586_configure_regulators(imx586);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) mutex_init(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) sd = &imx586->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) v4l2_i2c_subdev_init(sd, client, &imx586_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) ret = imx586_initialize_controls(imx586);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) ret = __imx586_power_on(imx586);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) ret = imx586_check_sensor_id(imx586, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) eeprom_ctrl_node = of_parse_phandle(node, "eeprom-ctrl", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) if (eeprom_ctrl_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) eeprom_ctrl_client =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) of_find_i2c_device_by_node(eeprom_ctrl_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) of_node_put(eeprom_ctrl_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) if (IS_ERR_OR_NULL(eeprom_ctrl_client)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) dev_err(dev, "can not get node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) goto continue_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) eeprom_ctrl = i2c_get_clientdata(eeprom_ctrl_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) if (IS_ERR_OR_NULL(eeprom_ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) dev_err(dev, "can not get eeprom i2c client\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) otp_ptr = devm_kzalloc(dev, sizeof(*otp_ptr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) if (!otp_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) ret = v4l2_subdev_call(eeprom_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) core, ioctl, 0, otp_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) imx586->otp = otp_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) imx586->otp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) devm_kfree(dev, otp_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) continue_probe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) sd->internal_ops = &imx586_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) imx586->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) ret = media_entity_pads_init(&sd->entity, 1, &imx586->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (strcmp(imx586->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) imx586->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) IMX586_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) __imx586_power_off(imx586);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) v4l2_ctrl_handler_free(&imx586->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) mutex_destroy(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) static int imx586_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) struct imx586 *imx586 = to_imx586(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) v4l2_ctrl_handler_free(&imx586->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) mutex_destroy(&imx586->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) __imx586_power_off(imx586);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) static const struct of_device_id imx586_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) { .compatible = "sony,imx586" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) MODULE_DEVICE_TABLE(of, imx586_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) static const struct i2c_device_id imx586_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) { "sony,imx586", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) static struct i2c_driver imx586_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .name = IMX586_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .pm = &imx586_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .of_match_table = of_match_ptr(imx586_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .probe = &imx586_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .remove = &imx586_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .id_table = imx586_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) return i2c_add_driver(&imx586_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) i2c_del_driver(&imx586_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) MODULE_DESCRIPTION("Sony imx586 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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