^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * imx577 camera driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 add full size 30fps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X02 fix gain and exposure setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 1.support 10bit HDR DOL2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * 2.4032*3040 @ 25fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * V0.0X01.0X04 add dgain ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) // #define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX577_LINK_FREQ_1050MHZ 1050000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX577_LINK_FREQ_498MHZ 498000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX577_PIXEL_RATE_1050M_10BIT (IMX577_LINK_FREQ_1050MHZ * 2LL * 4LL / 10LL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX577_PIXEL_RATE_1050M_12BIT (IMX577_LINK_FREQ_1050MHZ * 2LL * 4LL / 12LL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX577_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CHIP_ID 0x0577
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX577_REG_CHIP_ID 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX577_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX577_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX577_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX577_REG_EXPOSURE_H 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX577_REG_EXPOSURE_L 0x0203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX577_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX577_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX577_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX577_REG_GAIN_H 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX577_REG_GAIN_L 0x0205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX577_GAIN_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX577_GAIN_MAX 0x1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX577_GAIN_STEP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX577_GAIN_DEFAULT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX577_REG_DGAIN 0x3ff9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX577_DGAIN_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX577_REG_DGAINGR_H 0x020e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX577_REG_DGAINGR_L 0x020f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX577_REG_DGAINR_H 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX577_REG_DGAINR_L 0x0211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX577_REG_DGAINB_H 0x0212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX577_REG_DGAINB_L 0x0213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX577_REG_DGAINGB_H 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX577_REG_DGAINGB_L 0x0215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX577_LF_GAIN_REG_H 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX577_LF_GAIN_REG_L 0x00f1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX577_SEF1_GAIN_REG_H 0x00f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX577_SEF1_GAIN_REG_L 0x00f3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX577_SEF2_GAIN_REG_H 0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IMX577_SEF2_GAIN_REG_L 0x00f5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX577_LF_DGAIN_REG_H 0x00f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IMX577_LF_DGAIN_REG_L 0x00f7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX577_SEF1_DGAIN_REG_H 0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX577_SEF1_DGAIN_REG_L 0x00f9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMX577_SEF2_DGAIN_REG_H 0x00fa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX577_SEF2_DGAIN_REG_L 0x00fb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX577_LF_EXPO_REG_H 0x00ea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX577_LF_EXPO_REG_L 0x00eb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX577_SEF1_EXPO_REG_H 0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX577_SEF1_EXPO_REG_L 0x00ed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX577_SEF2_EXPO_REG_H 0x00ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX577_SEF2_EXPO_REG_L 0x00ef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX577_RHS1_REG_H 0x00e6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX577_RHS1_REG_L 0x00e7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX577_RHS2_REG_H 0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX577_RHS2_REG_L 0x00e9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX577_REG_TEST_PATTERN 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX577_TEST_PATTERN_ENABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX577_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX577_REG_VTS 0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX577_FETCH_EXP_H(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX577_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX577_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX577_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX577_FETCH_DGAIN_H(VAL) (((VAL) >> 8) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX577_FETCH_DGAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX577_FETCH_GAIN_H(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX577_FETCH_GAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX577_FETCH_RHS1_H(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX577_FETCH_RHS1_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX577_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX577_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IMX577_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX577_GROUP_HOLD_REG 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX577_GROUP_HOLD_START 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX577_GROUP_HOLD_END 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Basic Readout Lines. Number of necessary readout lines in sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define BRL_FULL 3077
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CIT_MARGIN 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX577_NAME "imx577"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const char * const imx577_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IMX577_NUM_SUPPLIES ARRAY_SIZE(imx577_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct imx577_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 link_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct imx577 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct regulator_bulk_data supplies[IMX577_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) const struct imx577_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 cur_pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 cur_link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct v4l2_fwnode_endpoint bus_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct rkmodule_awb_cfg awb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct rkmodule_lsc_cfg lsc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define to_imx577(sd) container_of(sd, struct imx577, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static __maybe_unused const struct regval imx577_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x0136, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x0137, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3C7E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3C7F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x38A8, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x38A9, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x38AA, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x38AB, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x55D4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x55D5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x55D6, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x55D7, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x55E8, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x55E9, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x55EA, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x55EB, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x575C, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x575D, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x575E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x575F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x5764, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x5765, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x5766, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x5767, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x5974, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x5975, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x5F10, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x5F11, 0x92},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x5F12, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x5F13, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x5F14, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x5F15, 0xBA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x5F17, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x5F18, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x5F19, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x5F1A, 0xE3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x5F1B, 0xAD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x5F1C, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x5F2D, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x5F5C, 0xD0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x6A22, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x6A23, 0x1D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x7BA8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x7BA9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x886B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x9002, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x9004, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x9214, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x9215, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x9216, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x9217, 0x6B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x9218, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x9219, 0x6D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x921A, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x921B, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x921C, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x921D, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x921E, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x921F, 0x5A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x9220, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x9221, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x9222, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x9223, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x9224, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x9225, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x9226, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x9227, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x9228, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x9229, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x922A, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x922B, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x922C, 0xB2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x922D, 0xDB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x922E, 0xB2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x922F, 0xDC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x9230, 0xB2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x9231, 0xDD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x9232, 0xB2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x9233, 0xE1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x9234, 0xB2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x9235, 0xE2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x9236, 0xB2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x9237, 0xE3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x9238, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x9239, 0xB9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x923A, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x923B, 0xBB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x923C, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x923D, 0xBC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x923E, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x923F, 0xC5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x9240, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x9241, 0xC7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x9242, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x9243, 0xC9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x9244, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x9245, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x9246, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x9247, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x9380, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x9381, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x9382, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x9383, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x9384, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x9385, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x9388, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x9389, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x938A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x938B, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x938C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x938D, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static __maybe_unused const struct regval imx577_linear_10bit_4056x3040_60fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x0112, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x0113, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x0342, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x0343, 0xA0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x0340, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x0341, 0x1E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x3210, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x0348, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x0349, 0xD7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x034A, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x034B, 0xDF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x00E3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x00E4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x00E5, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x00FC, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x00FD, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x00FE, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x00FF, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0xE013, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x0220, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x0221, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x0381, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x0383, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x0385, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x0387, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x0900, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x0901, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x0902, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x3140, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x3241, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x3250, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3E10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3E11, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x3F0D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x3F42, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x3F43, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x040A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x040B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x040C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x040D, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x040E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x040F, 0xE0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x034C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x034D, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x034E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x034F, 0xE0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x0303, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x0305, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x0306, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x0307, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x0309, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x030B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x030D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x030E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x030F, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x0310, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x0820, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x0821, 0xD0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x0822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x0823, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x3E20, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x3E37, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x3F50, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x3F56, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x3F57, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3C0A, 0x5A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x3C0B, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x3C0C, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x3C0D, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x3C0E, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x3C0F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3C10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x3C11, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x3C12, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3C13, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3C14, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3C15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3C16, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3C17, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x3C18, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x3C19, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x3C1A, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x3C1B, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x3C1C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x3C1D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x3C1E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x3C1F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x3C20, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3C21, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3C22, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x3C23, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x3E35, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x3F4A, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x3F4B, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x3F26, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x0202, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x0203, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x0204, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x0205, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x020E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x020F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x0210, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x0212, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x0213, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x0214, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x0215, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static __maybe_unused const struct regval imx577_linear_10bit_4056x3040_30fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x0112, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x0113, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x0342, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x0343, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x0340, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x0341, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x3210, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x0348, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x0349, 0xD7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x034A, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x034B, 0xDF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x00E3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x00E4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x00E5, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x00FC, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x00FD, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x00FE, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x00FF, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x0220, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x0221, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x0381, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x0383, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x0385, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x0387, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x0900, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x0901, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x0902, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x3140, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x3241, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3250, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x3E10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x3E11, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x3F0D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x3F42, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x3F43, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x040A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x040B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x040C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x040D, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x040E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x040F, 0xE0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x034C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x034D, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x034E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x034F, 0xE0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x0303, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x0305, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x0306, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x0307, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x0309, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x030B, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x030D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x030E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x030F, 0xA6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x0310, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x0820, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x0821, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x0822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x0823, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x3E20, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x3E37, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x3F50, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x3F56, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x3F57, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x3C0A, 0x5A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x3C0B, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x3C0C, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x3C0D, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x3C0E, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x3C0F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x3C10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x3C11, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x3C12, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x3C13, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x3C14, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x3C15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x3C16, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x3C17, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x3C18, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x3C19, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x3C1A, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x3C1B, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x3C1C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x3C1D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x3C1E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x3C1F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x3C20, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x3C21, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x3C22, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x3C23, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x3E35, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x3F4A, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x3F4B, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x3F26, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x0202, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x0203, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x0204, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x0205, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x020E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x020F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x0210, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x0212, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x0213, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x0214, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x0215, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static __maybe_unused const struct regval imx577_hdr2_10bit_4056x3040_15fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x0112, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x0113, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x0342, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x0343, 0xA0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x0340, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x0341, 0x3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x3210, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x0348, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x0349, 0xD7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x034A, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x034B, 0xDF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x00E3, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x00E4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x00E5, 0x00},//vc:0 LI:1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x00FC, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x00FD, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x00FE, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x00FF, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0xE013, 0x01},//VC:1 LI:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x0220, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x0221, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x0381, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x0383, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x0385, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x0387, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x0900, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x0901, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x0902, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x3140, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x3241, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {0x3250, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0x3E10, 0x01},//VC:1 LI:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x3E11, 0x02},//VC:2 LI:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x3F0D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x3F42, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x3F43, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x040A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x040B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x040C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x040D, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x040E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x040F, 0xE0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x034C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x034D, 0xDC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x034E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x034F, 0xE0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x0303, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x0305, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x0306, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {0x0307, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {0x0309, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {0x030B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {0x030D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {0x030E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {0x030F, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {0x0310, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {0x0820, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {0x0821, 0xD0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0x0822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {0x0823, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {0x3E20, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {0x3E37, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {0x3F50, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {0x3F56, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {0x3F57, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {0x3C0A, 0x5A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {0x3C0B, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {0x3C0C, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {0x3C0D, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {0x3C0E, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x3C0F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x3C10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x3C11, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x3C12, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x3C13, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {0x3C14, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {0x3C15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {0x3C16, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {0x3C17, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {0x3C18, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {0x3C19, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {0x3C1A, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {0x3C1B, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {0x3C1C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {0x3C1D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {0x3C1E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {0x3C1F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {0x3C20, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {0x3C21, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {0x3C22, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {0x3C23, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {0x3E35, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {0x3F4A, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {0x3F4B, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {0x3F26, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {0x0202, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {0x0203, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {0x0204, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {0x0205, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {0x020E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {0x020F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {0x0210, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {0x0212, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {0x0213, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {0x0214, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {0x0215, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static __maybe_unused const struct regval imx577_hdr2_10bit_4056x3040_30fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {0x0112, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {0x0113, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {0x0342, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {0x0343, 0xA0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {0x0340, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {0x0341, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {0x3210, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {0x0348, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {0x0349, 0xD7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {0x034A, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {0x034B, 0xDF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {0x00E3, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {0x00E4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {0x00E5, 0x00},//vc:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {0x00FC, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {0x00FD, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {0x00FE, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {0x00FF, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {0xE013, 0x01},//vc:1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {0x0220, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {0x0221, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {0x0381, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {0x0383, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {0x0385, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {0x0387, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {0x0900, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {0x0901, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {0x0902, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {0x3140, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {0x3241, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {0x3250, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0x3E10, 0x01},//vc:1 li:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0x3E11, 0x02},//vc:2 li:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0x3F0D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0x3F42, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {0x3F43, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {0x040A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {0x040B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {0x040C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {0x040D, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {0x040E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {0x040F, 0xE0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0x034C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {0x034D, 0xDC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {0x034E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {0x034F, 0xE0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {0x0303, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {0x0305, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {0x0306, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {0x0307, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {0x0309, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {0x030B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {0x030D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {0x030E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {0x030F, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {0x0310, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {0x0820, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {0x0821, 0xD0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {0x0822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {0x0823, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {0x3E20, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {0x3E37, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {0x3F50, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {0x3F56, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {0x3F57, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {0x3C0A, 0x5A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {0x3C0B, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {0x3C0C, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {0x3C0D, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {0x3C0E, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {0x3C0F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {0x3C10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {0x3C11, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {0x3C12, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {0x3C13, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {0x3C14, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {0x3C15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {0x3C16, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {0x3C17, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {0x3C18, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {0x3C19, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {0x3C1A, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {0x3C1B, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {0x3C1C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {0x3C1D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {0x3C1E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {0x3C1F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {0x3C20, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {0x3C21, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {0x3C22, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {0x3C23, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {0x3E35, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {0x3F4A, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {0x3F4B, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {0x3F26, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {0x0202, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {0x0203, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {0x0204, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {0x0205, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {0x020E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {0x020F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {0x0210, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {0x0212, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {0x0213, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {0x0214, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {0x0215, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static __maybe_unused const struct regval imx577_linear_12bit_4056x3040_40fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {0x0112, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {0x0113, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {0x0342, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {0x0343, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {0x0340, 0x0D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {0x0341, 0x2E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {0x3210, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {0x0348, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {0x0349, 0xD7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {0x034A, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {0x034B, 0xDF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {0x00E3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {0x00E4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {0x00E5, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {0x00FC, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {0x00FD, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {0x00FE, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {0x00FF, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {0xE013, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {0x0220, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {0x0221, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {0x0381, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {0x0383, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {0x0385, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {0x0387, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {0x0900, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {0x0901, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {0x0902, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {0x3140, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {0x3241, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {0x3250, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {0x3E10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {0x3E11, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {0x3F0D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {0x3F42, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {0x3F43, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {0x040A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {0x040B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {0x040C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {0x040D, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {0x040E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {0x040F, 0xE0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {0x034C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {0x034D, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {0x034E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {0x034F, 0xE0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {0x0303, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {0x0305, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {0x0306, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {0x0307, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {0x0309, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {0x030B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {0x030D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {0x030E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {0x030F, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {0x0310, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {0x0820, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {0x0821, 0xD0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {0x0822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {0x0823, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {0x3E20, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {0x3E37, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {0x3F50, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {0x3F56, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {0x3F57, 0xB2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {0x3C0A, 0x5A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {0x3C0B, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {0x3C0C, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {0x3C0D, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {0x3C0E, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {0x3C0F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {0x3C10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {0x3C11, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {0x3C12, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {0x3C13, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {0x3C14, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {0x3C15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {0x3C16, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {0x3C17, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {0x3C18, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {0x3C19, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {0x3C1A, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {0x3C1B, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {0x3C1C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {0x3C1D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {0x3C1E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {0x3C1F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {0x3C20, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {0x3C21, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {0x3C22, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {0x3C23, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {0x3E35, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {0x3F4A, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {0x3F4B, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {0x3F26, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {0x0202, 0x0D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {0x0203, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {0x0204, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {0x0205, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {0x020E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {0x020F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {0x0210, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {0x0212, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {0x0213, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {0x0214, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {0x0215, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static const struct imx577_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .width = 4056,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .height = 3040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .exp_def = 0x0c10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .hts_def = 0x2318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .vts_def = 0x0c2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .reg_list = imx577_linear_10bit_4056x3040_30fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .link_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .width = 4056,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .height = 3040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .exp_def = 0x0c10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .hts_def = 0x11a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .vts_def = 0x0e8a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .reg_list = imx577_hdr2_10bit_4056x3040_30fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .width = 4056,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .height = 3040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .exp_def = 0x0c10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .hts_def = 0x11a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .vts_def = 0x0c1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .reg_list = imx577_linear_10bit_4056x3040_60fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .width = 4056,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .height = 3040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .denominator = 400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .exp_def = 0x0c10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .hts_def = 0x11a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .vts_def = 0x0d2e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .bpp = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .reg_list = imx577_linear_12bit_4056x3040_40fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static const s64 link_freq_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) IMX577_LINK_FREQ_1050MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) IMX577_LINK_FREQ_498MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static const char * const imx577_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) "Vertical Color Bar Type 3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static int imx577_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static int imx577_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ret = imx577_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static int imx577_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static int imx577_get_reso_dist(const struct imx577_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static const struct imx577_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) imx577_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) dist = imx577_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static int imx577_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) struct imx577 *imx577 = to_imx577(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) const struct imx577_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) u32 lane_num = imx577->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) mutex_lock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) mode = imx577_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) mutex_unlock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) imx577->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) imx577->cur_vts = imx577->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) __v4l2_ctrl_modify_range(imx577->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) __v4l2_ctrl_modify_range(imx577->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) IMX577_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) __v4l2_ctrl_s_ctrl_int64(imx577->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) __v4l2_ctrl_s_ctrl(imx577->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) mode->link_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) mutex_unlock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static int imx577_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct imx577 *imx577 = to_imx577(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) const struct imx577_mode *mode = imx577->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) mutex_lock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) mutex_unlock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) mutex_unlock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static int imx577_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) struct imx577 *imx577 = to_imx577(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) code->code = imx577->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static int imx577_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static int imx577_enable_test_pattern(struct imx577 *imx577, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) val = (pattern - 1) | IMX577_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) val = IMX577_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) return imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) IMX577_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static int imx577_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct imx577 *imx577 = to_imx577(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) const struct imx577_mode *mode = imx577->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) mutex_lock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) mutex_unlock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static void imx577_get_module_inf(struct imx577 *imx577,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) strscpy(inf->base.sensor, IMX577_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) strscpy(inf->base.module, imx577->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) strscpy(inf->base.lens, imx577->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static void imx577_set_awb_cfg(struct imx577 *imx577,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct rkmodule_awb_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) mutex_lock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) memcpy(&imx577->awb_cfg, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) mutex_unlock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static void imx577_set_lsc_cfg(struct imx577 *imx577,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct rkmodule_lsc_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) mutex_lock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) memcpy(&imx577->lsc_cfg, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) mutex_unlock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static int imx577_set_hdrae(struct imx577 *imx577,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct i2c_client *client = imx577->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) u32 l_a_gain, m_a_gain, s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) u32 l_d_gain, s_d_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) u32 fll, dol_cit1, dol_cit2, dol_off2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (!imx577->has_init_exp && !imx577->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) imx577->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) imx577->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) dev_dbg(&imx577->client->dev, "imx577 is not streaming, save hdr ae!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) l_a_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) m_a_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) s_a_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) l_exp_time, m_exp_time, s_exp_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) l_a_gain, m_a_gain, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (imx577->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) l_a_gain = m_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ret = imx577_write_reg(client, IMX577_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) IMX577_REG_VALUE_08BIT, IMX577_GROUP_HOLD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* gain effect n+1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (l_a_gain > 0x1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) l_a_gain = 0x1600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (l_a_gain < 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) l_a_gain = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (s_a_gain > 0x1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) s_a_gain = 0x1600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (s_a_gain < 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) s_a_gain = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) l_d_gain = l_a_gain > 0x160 ? (l_a_gain * 256 / 22 / 16) : 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) l_a_gain = l_a_gain > 0x160 ? 0x160 : l_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) l_a_gain = 1024 - 1024 * 16 / l_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) s_d_gain = s_a_gain > 0x160 ? (s_a_gain * 256 / 22 / 16) : 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) s_a_gain = s_a_gain > 0x160 ? 0x160 : s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) s_a_gain = 1024 - 1024 * 16 / s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ret |= imx577_write_reg(client, IMX577_LF_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) IMX577_REG_VALUE_08BIT, IMX577_FETCH_GAIN_H(l_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) ret |= imx577_write_reg(client, IMX577_LF_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) IMX577_REG_VALUE_08BIT, IMX577_FETCH_GAIN_L(l_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) ret |= imx577_write_reg(client, IMX577_SEF1_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) IMX577_REG_VALUE_08BIT, IMX577_FETCH_GAIN_H(s_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret |= imx577_write_reg(client, IMX577_SEF1_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) IMX577_REG_VALUE_08BIT, IMX577_FETCH_GAIN_L(s_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (IMX577_DGAIN_MODE && l_d_gain > 0 && s_d_gain > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ret |= imx577_write_reg(client, IMX577_LF_DGAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) IMX577_REG_VALUE_08BIT, IMX577_FETCH_DGAIN_H(l_d_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ret |= imx577_write_reg(client, IMX577_LF_DGAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) IMX577_REG_VALUE_08BIT, IMX577_FETCH_DGAIN_L(l_d_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) ret |= imx577_write_reg(client, IMX577_SEF1_DGAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) IMX577_REG_VALUE_08BIT, IMX577_FETCH_DGAIN_H(s_d_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ret |= imx577_write_reg(client, IMX577_SEF1_DGAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) IMX577_REG_VALUE_08BIT, IMX577_FETCH_DGAIN_L(s_d_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) fll = imx577->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) dol_cit1 = l_exp_time >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) dol_cit2 = s_exp_time >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) /*dol_cit1 dol_cit2 dol_off2 should be even*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (dol_cit1 < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) dol_cit1 = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) else if (dol_cit1 > fll - 2 * CIT_MARGIN - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) dol_cit1 = fll - 2 * CIT_MARGIN - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) dol_cit1 &= (~0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (dol_cit2 < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) dol_cit2 = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) else if (dol_cit2 > fll - BRL_FULL - CIT_MARGIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) dol_cit2 = fll - BRL_FULL - CIT_MARGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) dol_cit2 &= (~0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) dol_off2 = (dol_cit2 + CIT_MARGIN) & (~0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (dol_off2 < dol_cit2 + CIT_MARGIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) dol_off2 = (dol_cit2 + CIT_MARGIN) & (~0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) else if (dol_off2 > fll - BRL_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) dol_off2 = (fll - BRL_FULL) & (~0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) "l_exp_time=%d,s_exp_time=%d,fll=%d,rhs1=%d,l_a_gain=%d,s_a_gain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) l_exp_time, s_exp_time, fll, dol_off2, l_a_gain, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ret |= imx577_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) IMX577_RHS1_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) IMX577_FETCH_RHS1_L(dol_off2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ret |= imx577_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) IMX577_RHS1_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) IMX577_FETCH_RHS1_H(dol_off2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) ret |= imx577_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) IMX577_SEF1_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) IMX577_FETCH_EXP_L(dol_cit2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) ret |= imx577_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) IMX577_SEF1_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) IMX577_FETCH_EXP_H(dol_cit2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) ret |= imx577_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) IMX577_LF_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) IMX577_FETCH_EXP_L(dol_cit1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) ret |= imx577_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) IMX577_LF_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) IMX577_FETCH_EXP_H(dol_cit1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) ret |= imx577_write_reg(client, IMX577_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) IMX577_REG_VALUE_08BIT, IMX577_GROUP_HOLD_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static int imx577_get_channel_info(struct imx577 *imx577, struct rkmodule_channel_info *ch_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) ch_info->vc = imx577->cur_mode->vc[ch_info->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ch_info->width = imx577->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) ch_info->height = imx577->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ch_info->bus_fmt = imx577->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static long imx577_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) struct imx577 *imx577 = to_imx577(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) s64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) const struct imx577_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) u32 lane_num = imx577->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (imx577->cur_mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) ret = imx577_set_hdrae(imx577, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) imx577_get_module_inf(imx577, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) hdr->hdr_mode = imx577->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) w = imx577->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) h = imx577->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) imx577->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) dev_err(&imx577->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) mode = imx577->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) imx577->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) w = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) h = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) mutex_lock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) __v4l2_ctrl_modify_range(imx577->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) __v4l2_ctrl_modify_range(imx577->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) IMX577_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) __v4l2_ctrl_s_ctrl(imx577->link_freq, mode->link_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) dst_pixel_rate = (u32)link_freq_items[mode->link_freq_idx] /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) mode->bpp * 2 * lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) __v4l2_ctrl_s_ctrl_int64(imx577->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) mutex_unlock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) imx577_set_awb_cfg(imx577, (struct rkmodule_awb_cfg *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) case RKMODULE_LSC_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) imx577_set_lsc_cfg(imx577, (struct rkmodule_lsc_cfg *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) ret = imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) IMX577_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) IMX577_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) ret = imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) IMX577_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) IMX577_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) ch_info = (struct rkmodule_channel_info *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) ret = imx577_get_channel_info(imx577, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) static long imx577_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) struct rkmodule_lsc_cfg *lsc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ret = imx577_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) ret = imx577_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) ret = imx577_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (copy_to_user(up, hdr, sizeof(*hdr))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (copy_from_user(hdr, up, sizeof(*hdr))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) ret = imx577_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (copy_from_user(hdrae, up, sizeof(*hdrae))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) ret = imx577_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) case RKMODULE_LSC_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) lsc_cfg = kzalloc(sizeof(*lsc_cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (!lsc_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) ret = copy_from_user(lsc_cfg, up, sizeof(*lsc_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) ret = imx577_ioctl(sd, cmd, lsc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) kfree(lsc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) ret = imx577_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (!ch_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) ret = imx577_ioctl(sd, cmd, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) ret = copy_to_user(up, ch_info, sizeof(*ch_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) kfree(ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) static int __imx577_start_stream(struct imx577 *imx577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) ret = imx577_write_array(imx577->client, imx577->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) ret = __v4l2_ctrl_handler_setup(&imx577->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) if (imx577->has_init_exp && imx577->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) ret = imx577_ioctl(&imx577->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) &imx577->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) dev_err(&imx577->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) IMX577_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) IMX577_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static int __imx577_stop_stream(struct imx577 *imx577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) imx577->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) return imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) IMX577_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) IMX577_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static int imx577_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) struct imx577 *imx577 = to_imx577(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) struct i2c_client *client = imx577->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) dev_info(&client->dev, "%s: on: %d, %dx%d@%d, hdr: %d, bpp: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) __func__, on, imx577->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) imx577->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) DIV_ROUND_CLOSEST(imx577->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) imx577->cur_mode->max_fps.numerator),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) imx577->cur_mode->hdr_mode, imx577->cur_mode->bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) mutex_lock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (on == imx577->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) ret = __imx577_start_stream(imx577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) __imx577_stop_stream(imx577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) imx577->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) mutex_unlock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) static int imx577_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) struct imx577 *imx577 = to_imx577(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) struct i2c_client *client = imx577->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) mutex_lock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (imx577->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) ret = imx577_write_array(imx577->client, imx577_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) imx577->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) imx577->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) mutex_unlock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) static inline u32 imx577_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) return DIV_ROUND_UP(cycles, IMX577_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static int __imx577_power_on(struct imx577 *imx577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) struct device *dev = &imx577->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (!IS_ERR(imx577->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) gpiod_set_value_cansleep(imx577->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (!IS_ERR_OR_NULL(imx577->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) ret = pinctrl_select_state(imx577->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) imx577->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) ret = clk_set_rate(imx577->xvclk, IMX577_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (clk_get_rate(imx577->xvclk) != IMX577_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) ret = clk_prepare_enable(imx577->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (!IS_ERR(imx577->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) gpiod_set_value_cansleep(imx577->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) ret = regulator_bulk_enable(IMX577_NUM_SUPPLIES, imx577->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) if (!IS_ERR(imx577->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) gpiod_set_value_cansleep(imx577->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if (!IS_ERR(imx577->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) gpiod_set_value_cansleep(imx577->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) delay_us = imx577_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) clk_disable_unprepare(imx577->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) static void __imx577_power_off(struct imx577 *imx577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) struct device *dev = &imx577->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (!IS_ERR(imx577->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) gpiod_set_value_cansleep(imx577->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) clk_disable_unprepare(imx577->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (!IS_ERR(imx577->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) gpiod_set_value_cansleep(imx577->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if (!IS_ERR_OR_NULL(imx577->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ret = pinctrl_select_state(imx577->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) imx577->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (!IS_ERR(imx577->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) gpiod_set_value_cansleep(imx577->power_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) regulator_bulk_disable(IMX577_NUM_SUPPLIES, imx577->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static int imx577_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) struct imx577 *imx577 = to_imx577(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) return __imx577_power_on(imx577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) static int imx577_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) struct imx577 *imx577 = to_imx577(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) __imx577_power_off(imx577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static int imx577_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) struct imx577 *imx577 = to_imx577(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) const struct imx577_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) mutex_lock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) mutex_unlock(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static int imx577_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static int imx577_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) struct imx577 *imx577 = to_imx577(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) const struct imx577_mode *mode = imx577->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) u32 lane_num = imx577->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) val = 1 << (lane_num - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) #define DST_WIDTH_4048 4048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) static int imx577_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) struct imx577 *imx577 = to_imx577(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) if (imx577->cur_mode->width == 4056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) sel->r.left = CROP_START(imx577->cur_mode->width, DST_WIDTH_4048);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) sel->r.width = DST_WIDTH_4048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) sel->r.top = CROP_START(imx577->cur_mode->height, imx577->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) sel->r.height = imx577->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) sel->r.left = CROP_START(imx577->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) imx577->cur_mode->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) sel->r.width = imx577->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) sel->r.top = CROP_START(imx577->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) imx577->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) sel->r.height = imx577->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static const struct dev_pm_ops imx577_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) SET_RUNTIME_PM_OPS(imx577_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) imx577_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) static const struct v4l2_subdev_internal_ops imx577_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .open = imx577_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) static const struct v4l2_subdev_core_ops imx577_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .s_power = imx577_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .ioctl = imx577_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .compat_ioctl32 = imx577_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) static const struct v4l2_subdev_video_ops imx577_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .s_stream = imx577_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .g_frame_interval = imx577_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) static const struct v4l2_subdev_pad_ops imx577_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .enum_mbus_code = imx577_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .enum_frame_size = imx577_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .enum_frame_interval = imx577_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .get_fmt = imx577_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .set_fmt = imx577_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .get_selection = imx577_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .get_mbus_config = imx577_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static const struct v4l2_subdev_ops imx577_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .core = &imx577_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .video = &imx577_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .pad = &imx577_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) static int imx577_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) struct imx577 *imx577 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) struct imx577, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) struct i2c_client *client = imx577->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) u32 again = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) u32 dgain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (imx577->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) max = imx577->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) __v4l2_ctrl_modify_range(imx577->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) imx577->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) imx577->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) imx577->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) if (imx577->cur_mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) ret = imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) IMX577_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) IMX577_FETCH_EXP_H(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) ret |= imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) IMX577_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) IMX577_FETCH_EXP_L(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) dev_dbg(&client->dev, "set exposure 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /* gain_reg = 1024 - 1024 / gain_ana
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) * manual multiple 16 to add accuracy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) * then formula change to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) * gain_reg = 1024 - 1024 * 16 / (gain_ana * 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) if (imx577->cur_mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) if (ctrl->val > 0x1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) ctrl->val = 0x1600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (ctrl->val < 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) ctrl->val = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) dgain = ctrl->val > 0x160 ? (ctrl->val * 256 / 22 / 16) : 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) again = ctrl->val > 0x160 ? 0x160 : ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) again = 1024 - 1024 * 16 / again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) ret = imx577_write_reg(imx577->client, IMX577_REG_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) IMX577_FETCH_AGAIN_H(again));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) ret |= imx577_write_reg(imx577->client, IMX577_REG_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) IMX577_FETCH_AGAIN_L(again));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) ret |= imx577_write_reg(imx577->client, IMX577_REG_DGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) IMX577_DGAIN_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) if (IMX577_DGAIN_MODE && dgain > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) ret |= imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) IMX577_REG_DGAINGR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) IMX577_FETCH_DGAIN_H(dgain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) ret |= imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) IMX577_REG_DGAINGR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) IMX577_FETCH_DGAIN_L(dgain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) } else if (dgain > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) ret |= imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) IMX577_REG_DGAINR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) IMX577_FETCH_DGAIN_H(dgain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) ret |= imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) IMX577_REG_DGAINR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) IMX577_FETCH_DGAIN_L(dgain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) ret |= imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) IMX577_REG_DGAINB_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) IMX577_FETCH_DGAIN_H(dgain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) ret |= imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) IMX577_REG_DGAINB_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) IMX577_FETCH_DGAIN_L(dgain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) ret |= imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) IMX577_REG_DGAINGB_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) IMX577_FETCH_DGAIN_H(dgain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) ret |= imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) IMX577_REG_DGAINGB_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) IMX577_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) IMX577_FETCH_DGAIN_L(dgain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) dev_dbg(&client->dev, "set analog gain 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) ret = imx577_write_reg(imx577->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) IMX577_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) IMX577_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) ctrl->val + imx577->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) ret = imx577_enable_test_pattern(imx577, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) static const struct v4l2_ctrl_ops imx577_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .s_ctrl = imx577_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) static int imx577_initialize_controls(struct imx577 *imx577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) const struct imx577_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) handler = &imx577->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) mode = imx577->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) handler->lock = &imx577->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) imx577->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) ARRAY_SIZE(link_freq_items) - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) link_freq_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) if (imx577->cur_mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) imx577->cur_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) imx577->cur_pixel_rate = IMX577_PIXEL_RATE_1050M_10BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) } else if (imx577->cur_mode->bus_fmt == MEDIA_BUS_FMT_SRGGB12_1X12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) imx577->cur_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) imx577->cur_pixel_rate = IMX577_PIXEL_RATE_1050M_12BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) imx577->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) 0, IMX577_PIXEL_RATE_1050M_10BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) 1, imx577->cur_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) __v4l2_ctrl_s_ctrl(imx577->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) mode->link_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) imx577->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) if (imx577->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) imx577->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) imx577->vblank = v4l2_ctrl_new_std(handler, &imx577_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) IMX577_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) imx577->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) imx577->exposure = v4l2_ctrl_new_std(handler, &imx577_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) V4L2_CID_EXPOSURE, IMX577_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) exposure_max, IMX577_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) imx577->anal_gain = v4l2_ctrl_new_std(handler, &imx577_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) V4L2_CID_ANALOGUE_GAIN, IMX577_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) IMX577_GAIN_MAX, IMX577_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) IMX577_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) imx577->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) &imx577_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) ARRAY_SIZE(imx577_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) 0, 0, imx577_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) dev_err(&imx577->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) imx577->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) imx577->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) static int imx577_check_sensor_id(struct imx577 *imx577,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) struct device *dev = &imx577->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) ret = imx577_read_reg(client, IMX577_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) IMX577_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) dev_info(dev, "Detected Sony imx%04x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) static int imx577_configure_regulators(struct imx577 *imx577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) for (i = 0; i < IMX577_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) imx577->supplies[i].supply = imx577_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) return devm_regulator_bulk_get(&imx577->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) IMX577_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) imx577->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) static int imx577_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) struct imx577 *imx577;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) imx577 = devm_kzalloc(dev, sizeof(*imx577), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) if (!imx577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) &imx577->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) &imx577->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) &imx577->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) &imx577->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) hdr_mode = NO_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) dev_warn(dev, " Get hdr mode failed! no hdr default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) imx577->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) imx577->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) &imx577->bus_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) dev_err(dev, "Failed to get bus cfg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) imx577->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) if (IS_ERR(imx577->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) imx577->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) if (IS_ERR(imx577->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) imx577->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) if (IS_ERR(imx577->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) imx577->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) if (IS_ERR(imx577->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) ret = imx577_configure_regulators(imx577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) imx577->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) if (!IS_ERR(imx577->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) imx577->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) pinctrl_lookup_state(imx577->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) if (IS_ERR(imx577->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) imx577->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) pinctrl_lookup_state(imx577->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) if (IS_ERR(imx577->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) mutex_init(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) sd = &imx577->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) v4l2_i2c_subdev_init(sd, client, &imx577_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) ret = imx577_initialize_controls(imx577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) ret = __imx577_power_on(imx577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) ret = imx577_check_sensor_id(imx577, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) sd->internal_ops = &imx577_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) imx577->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) ret = media_entity_pads_init(&sd->entity, 1, &imx577->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) if (strcmp(imx577->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) imx577->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) IMX577_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) __imx577_power_off(imx577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) v4l2_ctrl_handler_free(&imx577->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) mutex_destroy(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) static int imx577_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) struct imx577 *imx577 = to_imx577(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) v4l2_ctrl_handler_free(&imx577->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) mutex_destroy(&imx577->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) __imx577_power_off(imx577);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) static const struct of_device_id imx577_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) { .compatible = "sony,imx577" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) MODULE_DEVICE_TABLE(of, imx577_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) static const struct i2c_device_id imx577_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) { "sony,imx577", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) static struct i2c_driver imx577_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .name = IMX577_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .pm = &imx577_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .of_match_table = of_match_ptr(imx577_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .probe = &imx577_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .remove = &imx577_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .id_table = imx577_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) return i2c_add_driver(&imx577_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) i2c_del_driver(&imx577_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) MODULE_DESCRIPTION("Sony imx577 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags