^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IMX464 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 add conversion gain control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X02 add debug interface for conversion gain control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X03 support enum sensor fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MIPI_FREQ_360M 360000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MIPI_FREQ_445M 445600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MIPI_FREQ_594M 594000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX464_10BIT_HDR2_PIXEL_RATE (MIPI_FREQ_594M * 2 / 10 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX464_XVCLK_FREQ_37M 37125000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX464_XVCLK_FREQ_24M 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CHIP_ID 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX464_REG_CHIP_ID 0x3057
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX464_REG_CTRL_MODE 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX464_MODE_SW_STANDBY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX464_MODE_STREAMING 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX464_REG_MARSTER_MODE 0x3002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX464_MODE_STOP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX464_MODE_START 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX464_GAIN_SWITCH_REG 0x3019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX464_LF_GAIN_REG_H 0x30E9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX464_LF_GAIN_REG_L 0x30E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX464_SF1_GAIN_REG_H 0x30EB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX464_SF1_GAIN_REG_L 0x30EA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX464_SF2_GAIN_REG_H 0x30ED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX464_SF2_GAIN_REG_L 0x30EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX464_LF_EXPO_REG_H 0x305A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX464_LF_EXPO_REG_M 0x3059
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX464_LF_EXPO_REG_L 0x3058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX464_SF1_EXPO_REG_H 0x305E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX464_SF1_EXPO_REG_M 0x305D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX464_SF1_EXPO_REG_L 0x305C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX464_SF2_EXPO_REG_H 0x3062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX464_SF2_EXPO_REG_M 0x3061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX464_SF2_EXPO_REG_L 0x3060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX464_RHS1_DEFAULT 0x06d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX464_RHS1_X3_DEFAULT 0x0a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX464_RHS1_REG_H 0x306a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX464_RHS1_REG_M 0x3069
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX464_RHS1_REG_L 0x3068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX464_RHS2_REG_H 0x306E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX464_RHS2_REG_M 0x306D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IMX464_RHS2_REG_L 0x306C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX464_RHS2_X3_DEFAULT 0x0ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX464_EXPOSURE_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX464_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX464_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX464_GAIN_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX464_GAIN_MAX 0xee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX464_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX464_GAIN_DEFAULT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX464_FETCH_GAIN_H(VAL) (((VAL) >> 8) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX464_FETCH_GAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX464_FETCH_EXP_H(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX464_FETCH_EXP_M(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX464_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX464_FETCH_RHS1_H(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX464_FETCH_RHS1_M(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX464_FETCH_RHS1_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX464_FETCH_VTS_H(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX464_FETCH_VTS_M(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX464_FETCH_VTS_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX464_GROUP_HOLD_REG 0x3001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX464_GROUP_HOLD_START 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX464_GROUP_HOLD_END 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX464_VTS_REG_L 0x3030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX464_VTS_REG_M 0x3031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX464_VTS_REG_H 0x3032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX464_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IMX464_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IMX464_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX464_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX464_VREVERSE_REG 0x304f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX464_HREVERSE_REG 0x304e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define BRL 1558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RHS1_MAX ((BRL * 2 - 1) / 4 * 4 + 1) // <3*BRL=2*1558 && 6n+1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SHR1_MIN 9u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Readout timing setting of SEF1(DOL3): RHS1 < 3 * BRL and should be 6n + 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RHS1_MAX_X3 ((BRL * 3 - 1) / 6 * 6 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SHR1_MIN_X3 13u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IMX464_NAME "imx464"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const char * const IMX464_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX464_NUM_SUPPLIES ARRAY_SIZE(IMX464_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct IMX464_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct IMX464 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct regulator_bulk_data supplies[IMX464_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct v4l2_ctrl *anal_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct v4l2_fwnode_endpoint bus_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) const struct IMX464_mode *support_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) const struct IMX464_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 cur_mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) enum rkmodule_sync_mode sync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) bool isHCG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define to_IMX464(sd) container_of(sd, struct IMX464, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct regval IMX464_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static __maybe_unused const struct regval IMX464_linear_10bit_2688x1520_2lane_37m_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x300C, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x300D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3034, 0xDC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3035, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3058, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3059, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x30BE, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x30E8, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3110, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x314C, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x315A, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x319D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x319E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3288, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x328C, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x328E, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3415, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3418, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3428, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x349E, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x34A2, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x34A4, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x34A6, 0x8E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x34AA, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x35BC, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x35BE, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x35CC, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x35CD, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x35CE, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x35CF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x35DC, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x35DE, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x35DF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x35E4, 0x2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x35E5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x35E6, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x35E7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x367C, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x367E, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3680, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3682, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x3718, 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x371D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x375D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x375E, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x375F, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x3760, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x376A, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x376B, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x376C, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x376D, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x376E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x376F, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3770, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3776, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3778, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x377A, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x377B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x377C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x377D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x377E, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x377F, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3780, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3781, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3782, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3784, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3788, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x378A, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x378B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x378C, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x378D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x378E, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x378F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x3790, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x3791, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x3792, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x3793, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x3794, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x3795, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x3796, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x3798, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x3A01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3A18, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x3A1A, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x3A1C, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3A1E, 0xF7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3A1F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x3A20, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x3A22, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x3A24, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3A26, 0x5F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x3A28, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static __maybe_unused const struct regval IMX464_hdr_2x_10bit_2688x1520_2lane_37m_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x300C, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x300D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3034, 0xDC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3035, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x3048, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x3049, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x304A, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x304B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x304C, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x304D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x3050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x3058, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x3059, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x3068, 0x3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x30BE, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x30E8, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x3110, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x314C, 0x80},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x315A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x319D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x319E, 0x01},//1188M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x31D7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3200, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x3288, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x328C, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x328E, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x3415, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3418, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3428, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x349E, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x34A2, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x34A4, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x34A6, 0x8E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x34AA, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x35BC, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x35BE, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x35CC, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x35CD, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x35CE, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x35CF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x35DC, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x35DE, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x35DF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x35E4, 0x2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x35E5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x35E6, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x35E7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x367C, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x367E, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x3680, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x3682, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x3718, 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x371D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x375D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x375E, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x375F, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x3760, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x376A, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x376B, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x376C, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x376D, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x376E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x376F, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3770, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x3776, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x3778, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x377A, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x377B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x377C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x377D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x377E, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x377F, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3780, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3781, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3782, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x3784, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x3788, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x378A, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x378B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x378C, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x378D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x378E, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x378F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3790, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3791, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x3792, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x3793, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x3794, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x3795, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x3796, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x3798, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x3A01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x3A18, 0x8F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x3A1A, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x3A1C, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x3A1E, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x3A1F, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x3A20, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x3A22, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x3A24, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x3A26, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x3A28, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static const struct regval IMX464_linear_10bit_2688x1520_2lane_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x300C, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x300D, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x3034, 0xDC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x3035, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x3048, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x3049, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x304A, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x304B, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x304C, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x304D, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x3050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x3058, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x3059, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3068, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x30BE, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x30E8, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x3110, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x314C, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x314D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x315A, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x3168, 0xA0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x319D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x319E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x31D7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x3200, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x3288, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x328C, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x328E, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x3415, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3418, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x3428, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x349E, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x34A2, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x34A4, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x34A6, 0x8E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x34AA, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x35BC, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x35BE, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x35CC, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x35CD, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x35CE, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x35CF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x35DC, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x35DE, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x35DF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x35E4, 0x2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x35E5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x35E6, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x35E7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x367C, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x367E, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x3680, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x3682, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x3718, 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x371D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x375D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x375E, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x375F, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x3760, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x376A, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x376B, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x376C, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x376D, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x376E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x376F, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x3770, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x3776, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x3778, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x377A, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x377B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x377C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x377D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x377E, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x377F, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x3780, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x3781, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x3782, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x3784, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x3788, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x378A, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x378B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x378C, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x378D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x378E, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x378F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x3790, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x3791, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x3792, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x3793, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x3794, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x3795, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x3796, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x3798, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x3A01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x3A18, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x3A1A, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x3A1C, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x3A1E, 0xF7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x3A1F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x3A20, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x3A22, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x3A24, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x3A26, 0x5F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x3A28, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static const struct regval IMX464_hdr_2x_10bit_2688x1520_2lane_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x300C, 0x3B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x300D, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x3034, 0xDC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x3035, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x3048, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x3049, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x304A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x304B, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x304C, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x304D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x3050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x3058, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x3059, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x3068, 0x3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x30BE, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x30E8, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x3110, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x314C, 0x29},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x314D, 0x01},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x315A, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x3168, 0xA0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x319D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x319E, 0x02},//1188M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x31D7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x3200, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x3288, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x328C, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x328E, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x3415, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x3418, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x3428, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {0x349E, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0x34A2, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x34A4, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x34A6, 0x8E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x34AA, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x35BC, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x35BE, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x35CC, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x35CD, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x35CE, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x35CF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x35DC, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x35DE, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x35DF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x35E4, 0x2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x35E5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x35E6, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x35E7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x367C, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x367E, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x3680, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x3682, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x3718, 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {0x371D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {0x375D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {0x375E, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {0x375F, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {0x3760, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {0x376A, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {0x376B, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0x376C, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {0x376D, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {0x376E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {0x376F, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {0x3770, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {0x3776, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {0x3778, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {0x377A, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {0x377B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {0x377C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x377D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x377E, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x377F, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x3780, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x3781, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {0x3782, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {0x3784, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {0x3788, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {0x378A, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {0x378B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {0x378C, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {0x378D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {0x378E, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {0x378F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {0x3790, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {0x3791, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {0x3792, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {0x3793, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {0x3794, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {0x3795, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {0x3796, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {0x3798, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {0x3A01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {0x3A18, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {0x3A1A, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {0x3A1C, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {0x3A1E, 0xF7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {0x3A1F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {0x3A20, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {0x3A22, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {0x3A24, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {0x3A26, 0x5F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {0x3A28, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static const struct regval IMX464_linear_10bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {0x300C, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {0x300D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {0x3030, 0xE4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {0x3031, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {0x3034, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {0x3035, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {0x3048, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {0x3049, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {0x304A, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {0x304B, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {0x304C, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {0x3050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {0x3058, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {0x3059, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {0x305C, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {0x3060, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {0x3061, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {0x3068, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {0x306C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {0x306D, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {0x30BE, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {0x30E8, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {0x3110, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {0x314C, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {0x315A, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {0x319D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {0x319E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {0x31D7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {0x3200, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {0x3288, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {0x328C, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {0x328E, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {0x3415, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {0x3418, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0x3428, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0x349E, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0x34A2, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0x34A4, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {0x34A6, 0x8E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {0x34AA, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {0x35BC, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {0x35BE, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {0x35CC, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {0x35CD, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {0x35CE, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {0x35CF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {0x35DC, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {0x35DE, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {0x35DF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {0x35E4, 0x2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0x35E5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {0x35E6, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {0x35E7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {0x367C, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {0x367E, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {0x3680, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {0x3682, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {0x3718, 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {0x371D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {0x375D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {0x375E, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {0x375F, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {0x3760, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {0x376A, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {0x376B, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {0x376C, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {0x376D, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {0x376E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {0x376F, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {0x3770, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {0x3776, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {0x3778, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {0x377A, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {0x377B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {0x377C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {0x377D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {0x377E, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {0x377F, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {0x3780, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {0x3781, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {0x3782, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {0x3784, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {0x3788, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {0x378A, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {0x378B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {0x378C, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {0x378D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {0x378E, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {0x378F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {0x3790, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {0x3791, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {0x3792, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {0x3793, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {0x3794, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {0x3795, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {0x3796, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {0x3798, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {0x3A18, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {0x3A1A, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {0x3A1C, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {0x3A1E, 0xF7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {0x3A1F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {0x3A20, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {0x3A22, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {0x3A24, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {0x3A26, 0x5F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {0x3A28, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static const struct regval IMX464_hdr_2x_10bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {0x300C, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {0x300D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {0x3030, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {0x3031, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {0x3034, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {0x3035, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {0x3048, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {0x3049, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {0x304A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {0x304B, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {0x304C, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {0x3050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {0x3058, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {0x3059, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {0x305C, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {0x3060, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {0x3061, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {0x3068, 0x6D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {0x306C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {0x306D, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {0x30BE, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {0x30E8, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {0x3110, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {0x314C, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {0x315A, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {0x319D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {0x319E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {0x31D7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {0x3200, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {0x3288, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {0x328C, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {0x328E, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {0x3415, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {0x3418, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {0x3428, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {0x349E, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {0x34A2, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {0x34A4, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {0x34A6, 0x8E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {0x34AA, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {0x35BC, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {0x35BE, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {0x35CC, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {0x35CD, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {0x35CE, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {0x35CF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {0x35DC, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {0x35DE, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {0x35DF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {0x35E4, 0x2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {0x35E5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {0x35E6, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {0x35E7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {0x367C, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {0x367E, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {0x3680, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {0x3682, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {0x3718, 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {0x371D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {0x375D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {0x375E, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {0x375F, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {0x3760, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {0x376A, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {0x376B, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {0x376C, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {0x376D, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {0x376E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {0x376F, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {0x3770, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {0x3776, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {0x3778, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {0x377A, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {0x377B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {0x377C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {0x377D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {0x377E, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {0x377F, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {0x3780, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {0x3781, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {0x3782, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {0x3784, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {0x3788, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {0x378A, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {0x378B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {0x378C, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {0x378D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {0x378E, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {0x378F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {0x3790, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {0x3791, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {0x3792, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {0x3793, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {0x3794, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {0x3795, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {0x3796, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {0x3798, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {0x3A18, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {0x3A1A, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {0x3A1C, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {0x3A1E, 0xF7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {0x3A1F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {0x3A20, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {0x3A22, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {0x3A24, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {0x3A26, 0x5F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {0x3A28, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static const struct regval IMX464_hdr_3x_10bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {0x300C, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {0x300D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #ifdef FRAME_15_FPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {0x3030, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {0x3031, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {0x3030, 0xD1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {0x3031, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) //add for default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {0x3034, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {0x3035, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {0x3048, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {0x3049, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {0x304A, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {0x304B, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {0x304C, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {0x3050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {0x3058, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {0x3059, 0x0D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {0x305C, 0x0D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {0x3060, 0xB0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {0x3061, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {0x3068, 0xA3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {0x306C, 0xCE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {0x306D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {0x30BE, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {0x30E8, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {0x3110, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {0x314C, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {0x315A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {0x319D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {0x319E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {0x31D7, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {0x3200, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {0x3288, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {0x328C, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {0x328E, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {0x3415, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {0x3418, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {0x3428, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {0x349E, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {0x34A2, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {0x34A4, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {0x34A6, 0x8E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {0x34AA, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {0x35BC, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {0x35BE, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {0x35CC, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {0x35CD, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {0x35CE, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {0x35CF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {0x35DC, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {0x35DE, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {0x35DF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {0x35E4, 0x2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {0x35E5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {0x35E6, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {0x35E7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {0x367C, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {0x367E, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {0x3680, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {0x3682, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {0x3718, 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {0x371D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {0x375D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {0x375E, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {0x375F, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {0x3760, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {0x376A, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {0x376B, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {0x376C, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {0x376D, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {0x376E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {0x376F, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {0x3770, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {0x3776, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {0x3778, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {0x377A, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {0x377B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {0x377C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {0x377D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {0x377E, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {0x377F, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {0x3780, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {0x3781, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {0x3782, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {0x3784, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {0x3788, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {0x378A, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {0x378B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {0x378C, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {0x378D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {0x378E, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {0x378F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {0x3790, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {0x3791, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {0x3792, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {0x3793, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {0x3794, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {0x3795, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {0x3796, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {0x3798, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {0x3A18, 0x8F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {0x3A1A, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {0x3A1C, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {0x3A1E, 0xF7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {0x3A1F, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {0x3A20, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {0x3A22, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {0x3A24, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {0x3A26, 0x5F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {0x3A28, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static __maybe_unused const struct regval IMX464_linear_12bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {0x300C, 0x3B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {0x300D, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {0x3018, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {0x302C, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {0x302E, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {0x302F, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {0x3030, 0x6B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {0x3031, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {0x3032, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {0x3034, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {0x3035, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {0x3048, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {0x3049, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {0x304A, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {0x304B, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {0x304C, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {0x3050, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {0x3056, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {0x3057, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {0x3058, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {0x3059, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {0x3068, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {0x3069, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {0x30BE, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) {0x30C6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {0x30CE, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {0x30D8, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {0x30D9, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {0x3110, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {0x314C, 0xF0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {0x315A, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {0x3168, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {0x319D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {0x319E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {0x31D7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {0x3202, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {0x3288, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {0x328C, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {0x328E, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {0x3415, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {0x3418, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {0x3428, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {0x349E, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {0x34A2, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {0x34A4, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {0x34A6, 0x8E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {0x34AA, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {0x367C, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {0x367E, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) {0x3680, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {0x3682, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {0x371D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {0x375D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {0x375E, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {0x375F, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {0x3760, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {0x376A, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {0x376B, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {0x376C, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) {0x376D, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {0x376E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {0x376F, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {0x3770, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {0x3776, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {0x3778, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {0x377A, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {0x377B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) {0x377C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {0x377D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {0x377E, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {0x377F, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {0x3780, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {0x3781, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {0x3782, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) {0x3784, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {0x3788, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {0x378A, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {0x378B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {0x378C, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {0x378D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {0x378E, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) {0x378F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {0x3790, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {0x3791, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {0x3792, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) {0x3793, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {0x3794, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {0x3795, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {0x3796, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {0x3200, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) {0x3798, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {0x3A01, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {0x3A18, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) {0x3A1A, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {0x3A1C, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {0x3A1E, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {0x3A1F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {0x3A20, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {0x3A22, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {0x3A24, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {0x3A26, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) {0x3A28, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static __maybe_unused const struct regval IMX464_hdr_2x_12bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {0x300C, 0x3B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {0x300D, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {0x3018, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {0x302C, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {0x302E, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) {0x302F, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {0x3030, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {0x3031, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) {0x3032, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {0x3034, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {0x3035, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {0x3048, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {0x3049, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) {0x304A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {0x304B, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {0x304C, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {0x3050, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {0x3056, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {0x3057, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) {0x3058, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {0x3059, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {0x3068, 0xD9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {0x3069, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) {0x30BE, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {0x30C6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {0x30CE, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {0x30D8, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {0x30D9, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) {0x3110, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {0x314C, 0xF0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {0x315A, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {0x3168, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) {0x319D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {0x319E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {0x31D7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {0x3202, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {0x3288, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {0x328C, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {0x328E, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {0x3415, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {0x3418, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) {0x3428, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) {0x349E, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) {0x34A2, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) {0x34A4, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {0x34A6, 0x8E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {0x34AA, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {0x367C, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) {0x367E, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) {0x3680, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {0x3682, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {0x371D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) {0x375D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) {0x375E, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {0x375F, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {0x3760, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {0x376A, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) {0x376B, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {0x376C, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {0x376D, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {0x376E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {0x376F, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {0x3770, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) {0x3776, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {0x3778, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {0x377A, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {0x377B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {0x377C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {0x377D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) {0x377E, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {0x377F, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {0x3780, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {0x3781, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {0x3782, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {0x3784, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {0x3788, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {0x378A, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {0x378B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {0x378C, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {0x378D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {0x378E, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {0x378F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {0x3790, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {0x3791, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) {0x3792, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {0x3793, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {0x3794, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {0x3795, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {0x3796, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) {0x3200, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {0x3798, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) {0x3A01, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {0x3A18, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {0x3A1A, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {0x3A1C, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {0x3A1E, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {0x3A1F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {0x3A20, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {0x3A22, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) {0x3A24, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {0x3A26, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {0x3A28, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static __maybe_unused const struct regval IMX464_interal_sync_master_start_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {0x3010, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {0x31a1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static __maybe_unused const struct regval IMX464_interal_sync_master_stop_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {0x31a1, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) static __maybe_unused const struct regval IMX464_external_sync_master_start_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) {0x3010, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {0x31a1, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) {0x31d9, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static __maybe_unused const struct regval IMX464_external_sync_master_stop_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {0x31a1, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static __maybe_unused const struct regval IMX464_slave_start_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {0x3010, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) {0x31a1, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * The width and height must be configured to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * the same as the current output resolution of the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * The input width of the isp needs to be 16 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * The input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * If the width or height does not meet the alignment rules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * you can configure the cropping parameters with the following function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * crop out the appropriate resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * struct v4l2_subdev_pad_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * .get_selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static const struct IMX464_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .width = 2712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .height = 1536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .exp_def = 0x0906,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .hts_def = 0x05dc * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .vts_def = 0x0ce4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .mclk = 37125000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .reg_list = IMX464_linear_10bit_2688x1520_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .width = 2712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .height = 1536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .exp_def = 0x03de,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .hts_def = 0x02ee * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .vts_def = 0x0672 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .mclk = 37125000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .reg_list = IMX464_hdr_2x_10bit_2688x1520_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .width = 2712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .height = 1536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #ifdef FRAME_15_FPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .denominator = 150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .exp_def = 0x05cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .hts_def = 0x01F4 * 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #ifdef FRAME_15_FPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .vts_def = 0x09A2 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .vts_def = 0x04D1 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .mclk = 37125000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .reg_list = IMX464_hdr_3x_10bit_2688x1520_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .hdr_mode = HDR_X3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static const struct IMX464_mode supported_modes_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .width = 2712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .height = 1538,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .exp_def = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .hts_def = 0x05dc * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .vts_def = 0x672,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .mclk = 24000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .reg_list = IMX464_linear_10bit_2688x1520_2lane_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .width = 2712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .height = 1538,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .denominator = 150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .exp_def = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .hts_def = 0x05dc * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .vts_def = 0x0672 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .mclk = 24000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .reg_list = IMX464_hdr_2x_10bit_2688x1520_2lane_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) MIPI_FREQ_445M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) MIPI_FREQ_594M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static int imx464_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static int IMX464_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) ret = imx464_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) IMX464_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static int IMX464_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) static int IMX464_get_reso_dist(const struct IMX464_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static const struct IMX464_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) IMX464_find_best_fit(struct IMX464 *IMX464, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) for (i = 0; i < IMX464->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dist = IMX464_get_reso_dist(&IMX464->support_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) IMX464->support_modes[i].bus_fmt == framefmt->code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return &IMX464->support_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static int IMX464_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) const struct IMX464_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) mutex_lock(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) mode = IMX464_find_best_fit(IMX464, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) mutex_unlock(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) IMX464->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) __v4l2_ctrl_modify_range(IMX464->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) __v4l2_ctrl_modify_range(IMX464->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) IMX464_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) IMX464->cur_vts = IMX464->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) pixel_rate = (u32)link_freq_menu_items[mode->mipi_freq_idx] / mode->bpp * 2 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) IMX464->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) __v4l2_ctrl_s_ctrl_int64(IMX464->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) __v4l2_ctrl_s_ctrl(IMX464->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) mutex_unlock(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static int IMX464_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) const struct IMX464_mode *mode = IMX464->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) mutex_lock(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) mutex_unlock(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) mutex_unlock(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static int IMX464_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) code->code = IMX464->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static int IMX464_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (fse->index >= IMX464->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (fse->code != IMX464->support_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) fse->min_width = IMX464->support_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) fse->max_width = IMX464->support_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) fse->max_height = IMX464->support_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) fse->min_height = IMX464->support_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static int IMX464_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) const struct IMX464_mode *mode = IMX464->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) mutex_lock(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) mutex_unlock(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static int IMX464_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) const struct IMX464_mode *mode = IMX464->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) u32 lane_num = IMX464->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) val = 1 << (lane_num - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) val = 1 << (lane_num - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) val = 1 << (lane_num - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) V4L2_MBUS_CSI2_CHANNEL_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static void IMX464_get_module_inf(struct IMX464 *IMX464,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) strscpy(inf->base.sensor, IMX464_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) strscpy(inf->base.module, IMX464->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) strscpy(inf->base.lens, IMX464->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) static int IMX464_set_hdrae(struct IMX464 *IMX464,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) struct i2c_client *client = IMX464->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) u32 l_a_gain, m_a_gain, s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) u32 gain_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) u32 shr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) u32 shr0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) u32 rhs1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) u32 rhs1_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static int rhs1_old = IMX464_RHS1_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) int rhs1_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) u32 fsc = IMX464->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) u8 cg_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (!IMX464->has_init_exp && !IMX464->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) IMX464->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) IMX464->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) dev_dbg(&IMX464->client->dev, "IMX464 don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) l_a_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) m_a_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) s_a_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) l_exp_time, m_exp_time, s_exp_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) l_a_gain, m_a_gain, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) if (IMX464->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) //2 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) l_a_gain = m_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) cg_mode = ae->middle_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (!IMX464->isHCG && cg_mode == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) gain_switch = 0x01 | 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) IMX464->isHCG = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) } else if (IMX464->isHCG && cg_mode == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) gain_switch = 0x00 | 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) IMX464->isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) ret = imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) IMX464_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) IMX464_GROUP_HOLD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) //gain effect n+1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) IMX464_LF_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) IMX464_FETCH_GAIN_H(l_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) IMX464_LF_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) IMX464_FETCH_GAIN_L(l_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) IMX464_SF1_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) IMX464_FETCH_GAIN_H(s_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) IMX464_SF1_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) IMX464_FETCH_GAIN_L(s_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) if (gain_switch & 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) IMX464_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) gain_switch & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) /* Restrictions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) * FSC = 2 * VMAX = 4n (4n, align with 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) * SHR1 + 9 <= SHR0 <= (FSC - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) * exp_l = FSC - SHR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) * SHR0 = FSC - exp_l (2n, align with 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) * exp_s = RHS1 - SHR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) * SHR1 + 2 <= RHS1 < BRL * 2 (4n + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) * SHR1 + 2 <= RHS1 <= SHR0 - 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * 9 <= SHR1 <= RHS1 - 2 (2n + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * RHS1(n+1) >= (RHS1(n) + BRL * 2) - FSC + 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * RHS1 and SHR1 shall be even value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) * T(l_exp) = FSC - SHR0, unit: H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) * T(s_exp) = RHS1 - SHR1, unit: H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) * Exposure ratio: T(l_exp) / T(s_exp) >= 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /* The HDR mode vts is already double by default to workaround T-line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) //long exposure and short exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) shr0 = fsc - l_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) rhs1_max = (RHS1_MAX > (shr0 - 9)) ? (shr0 - 9) : RHS1_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) rhs1 = SHR1_MIN + s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) dev_err(&client->dev, "line(%d) rhs1 %d\n", __LINE__, rhs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if (rhs1 < 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) rhs1 = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) else if (rhs1 > rhs1_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) rhs1 = rhs1_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) dev_dbg(&client->dev, "line(%d) rhs1 %d\n", __LINE__, rhs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) //Dynamic adjustment rhs1 must meet the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) rhs1_change_limit = rhs1_old + 2 * BRL - fsc + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) rhs1_change_limit = (rhs1_change_limit < 11) ? 11 : rhs1_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (rhs1_max < rhs1_change_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) "The total exposure limit makes rhs1 max is %d,but old rhs1 limit makes rhs1 min is %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) rhs1_max, rhs1_change_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (rhs1 < rhs1_change_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) rhs1 = rhs1_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) "line(%d) rhs1 %d,short time %d rhs1_old %d test %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) __LINE__, rhs1, s_exp_time, rhs1_old,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) (rhs1_old + 2 * BRL - fsc + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) rhs1 = (rhs1 >> 2) * 4 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) rhs1_old = rhs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) if (rhs1 - s_exp_time <= SHR1_MIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) shr1 = SHR1_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) s_exp_time = rhs1 - shr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) shr1 = rhs1 - s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) if (shr1 < 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) shr1 = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) else if (shr1 > (rhs1 - 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) shr1 = rhs1 - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) if (shr0 < (rhs1 + 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) shr0 = rhs1 + 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) else if (shr0 > (fsc - 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) shr0 = fsc - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) "fsc=%d,RHS1_MAX=%d,SHR1_MIN=%d,rhs1_max=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) fsc, RHS1_MAX, SHR1_MIN, rhs1_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) "l_exp_time=%d,s_exp_time=%d,shr0=%d,shr1=%d,rhs1=%d,l_a_gain=%d,s_a_gain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) l_exp_time, s_exp_time, shr0, shr1, rhs1, l_a_gain, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) //time effect n+2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) IMX464_RHS1_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) IMX464_FETCH_RHS1_L(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) IMX464_RHS1_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) IMX464_FETCH_RHS1_M(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) IMX464_RHS1_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) IMX464_FETCH_RHS1_H(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) IMX464_SF1_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) IMX464_FETCH_EXP_L(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) IMX464_SF1_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) IMX464_FETCH_EXP_M(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) IMX464_SF1_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) IMX464_FETCH_EXP_H(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) IMX464_LF_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) IMX464_FETCH_EXP_L(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) IMX464_LF_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) IMX464_FETCH_EXP_M(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) IMX464_LF_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) IMX464_FETCH_EXP_H(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) IMX464_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) IMX464_GROUP_HOLD_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static int IMX464_set_hdrae_3frame(struct IMX464 *IMX464,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) struct i2c_client *client = IMX464->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) u32 l_a_gain, m_a_gain, s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) int shr2, shr1, shr0, rhs2, rhs1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) int rhs1_change_limit, rhs2_change_limit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static int rhs1_old = IMX464_RHS1_X3_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) static int rhs2_old = IMX464_RHS2_X3_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) u32 gain_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) u8 cg_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) u32 fsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) int rhs1_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) int shr2_min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) if (!IMX464->has_init_exp && !IMX464->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) IMX464->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) IMX464->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) dev_dbg(&IMX464->client->dev, "IMX464 is not streaming, save hdr ae!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) l_a_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) m_a_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) s_a_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (IMX464->cur_mode->hdr_mode == HDR_X3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) //3 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) cg_mode = ae->long_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) if (!IMX464->isHCG && cg_mode == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) gain_switch = 0x01 | 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) IMX464->isHCG = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) } else if (IMX464->isHCG && cg_mode == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) gain_switch = 0x00 | 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) IMX464->isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) l_exp_time, l_a_gain, m_exp_time, m_a_gain, s_exp_time, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) ret = imx464_write_reg(client, IMX464_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) IMX464_REG_VALUE_08BIT, IMX464_GROUP_HOLD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) /* gain effect n+1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) ret |= imx464_write_reg(client, IMX464_LF_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) IMX464_REG_VALUE_08BIT, IMX464_FETCH_GAIN_H(l_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ret |= imx464_write_reg(client, IMX464_LF_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) IMX464_REG_VALUE_08BIT, IMX464_FETCH_GAIN_L(l_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) ret |= imx464_write_reg(client, IMX464_SF1_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) IMX464_REG_VALUE_08BIT, IMX464_FETCH_GAIN_H(m_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) ret |= imx464_write_reg(client, IMX464_SF1_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) IMX464_REG_VALUE_08BIT, IMX464_FETCH_GAIN_L(m_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) ret |= imx464_write_reg(client, IMX464_SF2_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) IMX464_REG_VALUE_08BIT, IMX464_FETCH_GAIN_H(s_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) ret |= imx464_write_reg(client, IMX464_SF2_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) IMX464_REG_VALUE_08BIT, IMX464_FETCH_GAIN_L(s_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if (gain_switch & 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) IMX464_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) gain_switch & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) /* Restrictions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) * FSC = 4 * VMAX and FSC should be 6n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) * exp_l = FSC - SHR0 + Toffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) * SHR0 = FSC - exp_l + Toffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) * SHR0 <= (FSC -3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) * SHR0 >= RHS2 + 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) * SHR0 should be 3n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) * exp_m = RHS1 - SHR1 + Toffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) * RHS1 < BRL * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) * RHS1 <= SHR2 - 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) * RHS1 >= SHR1 + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) * SHR1 >= 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) * SHR1 <= RHS1 - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) * RHS1(n+1) >= RHS1(n) + BRL * 3 -FSC + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) * SHR1 should be 3n+1 and RHS1 should be 6n+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) * exp_s = RHS2 - SHR2 + Toffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) * RHS2 < BRL * 3 + RHS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) * RHS2 <= SHR0 - 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) * RHS2 >= SHR2 + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) * SHR2 >= RHS1 + 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) * SHR2 <= RHS2 - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) * RHS1(n+1) >= RHS1(n) + BRL * 3 -FSC + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) * SHR2 should be 3n+2 and RHS2 should be 6n+2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) /* The HDR mode vts is double by default to workaround T-line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) fsc = IMX464->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) shr0 = fsc - l_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) "line(%d) shr0 %d, l_exp_time %d, fsc %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) __LINE__, shr0, l_exp_time, fsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) rhs1 = (SHR1_MIN_X3 + m_exp_time + 5) / 6 * 6 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) rhs1_max = RHS1_MAX_X3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if (rhs1 < SHR1_MIN_X3 + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) rhs1 = SHR1_MIN_X3 + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) else if (rhs1 > rhs1_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) rhs1 = rhs1_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) "line(%d) rhs1 %d, m_exp_time %d rhs1_old %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) __LINE__, rhs1, m_exp_time, rhs1_old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) //Dynamic adjustment rhs2 must meet the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) rhs1_change_limit = rhs1_old + 3 * BRL - fsc + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) rhs1_change_limit = (rhs1_change_limit < 16) ? 16 : rhs1_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) rhs1_change_limit = (rhs1_change_limit + 5) / 6 * 6 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) if (rhs1_max < rhs1_change_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) "The total exposure limit makes rhs1 max is %d,but old rhs1 limit makes rhs1 min is %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) rhs1_max, rhs1_change_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) if (rhs1 < rhs1_change_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) rhs1 = rhs1_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) "line(%d) m_exp_time %d rhs1_old %d, rhs1_new %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) __LINE__, m_exp_time, rhs1_old, rhs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) rhs1_old = rhs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) /* shr1 = rhs1 - s_exp_time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) if (rhs1 - m_exp_time <= SHR1_MIN_X3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) shr1 = SHR1_MIN_X3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) m_exp_time = rhs1 - shr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) shr1 = rhs1 - m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) shr2_min = rhs1 + 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) rhs2 = (shr2_min + s_exp_time + 5) / 6 * 6 + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) if (rhs2 > (shr0 - 13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) rhs2 = shr0 - 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) else if (rhs2 < 32)//16+13 +3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) rhs2 = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) "line(%d) rhs2 %d, s_exp_time %d, rhs2_old %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) __LINE__, rhs2, s_exp_time, rhs2_old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) //Dynamic adjustment rhs2 must meet the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) //RHS2(N+1) > (RHS2(N) + BRL 3) C VMAX 4) + 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) rhs2_change_limit = rhs2_old + 3 * BRL - fsc + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) rhs2_change_limit = (rhs2_change_limit < 32) ? 32 : rhs2_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) rhs2_change_limit = (rhs2_change_limit + 5) / 6 * 6 + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) if ((shr0 - 13) < rhs2_change_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) "The total exposure limit makes rhs2 max is %d,but old rhs1 limit makes rhs2 min is %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) shr0 - 13, rhs2_change_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (rhs2 < rhs2_change_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) rhs2 = rhs2_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) rhs2_old = rhs2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) /* shr2 = rhs2 - s_exp_time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) if (rhs2 - s_exp_time <= shr2_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) shr2 = shr2_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) s_exp_time = rhs2 - shr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) shr2 = rhs2 - s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) "line(%d) rhs2_new %d, s_exp_time %d shr2 %d, rhs2_change_limit %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) __LINE__, rhs2, s_exp_time, shr2, rhs2_change_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) if (shr0 < rhs2 + 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) shr0 = rhs2 + 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) else if (shr0 > fsc - 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) shr0 = fsc - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) "long exposure: l_exp_time=%d, fsc=%d, shr0=%d, l_a_gain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) l_exp_time, fsc, shr0, l_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) "middle exposure(SEF1): m_exp_time=%d, rhs1=%d, shr1=%d, m_a_gain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) m_exp_time, rhs1, shr1, m_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) "short exposure(SEF2): s_exp_time=%d, rhs2=%d, shr2=%d, s_a_gain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) s_exp_time, rhs2, shr2, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) /* time effect n+1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) /* write SEF2 exposure RHS2 regs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) IMX464_RHS2_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) IMX464_FETCH_RHS1_L(rhs2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) IMX464_RHS2_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) IMX464_FETCH_RHS1_M(rhs2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) IMX464_RHS2_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) IMX464_FETCH_RHS1_H(rhs2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) /* write SEF2 exposure SHR2 regs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) IMX464_SF2_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) IMX464_FETCH_EXP_L(shr2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) IMX464_SF2_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) IMX464_FETCH_EXP_M(shr2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) IMX464_SF2_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) IMX464_FETCH_EXP_H(shr2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) /* write SEF1 exposure RHS1 regs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) IMX464_RHS1_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) IMX464_FETCH_RHS1_L(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) IMX464_RHS1_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) IMX464_FETCH_RHS1_M(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) IMX464_RHS1_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) IMX464_FETCH_RHS1_H(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) /* write SEF1 exposure SHR1 regs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) IMX464_SF1_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) IMX464_FETCH_EXP_L(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) IMX464_SF1_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) IMX464_FETCH_EXP_M(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) IMX464_SF1_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) IMX464_FETCH_EXP_H(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) /* write LF exposure SHR0 regs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) IMX464_LF_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) IMX464_FETCH_EXP_L(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) IMX464_LF_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) IMX464_FETCH_EXP_M(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) IMX464_LF_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) IMX464_FETCH_EXP_H(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) ret |= imx464_write_reg(client, IMX464_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) IMX464_REG_VALUE_08BIT, IMX464_GROUP_HOLD_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) static int IMX464_set_conversion_gain(struct IMX464 *IMX464, u32 *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) struct i2c_client *client = IMX464->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) int cur_cg = *cg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) u32 gain_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) if (IMX464->isHCG && cur_cg == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) gain_switch = 0x00 | 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) IMX464->isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) } else if (!IMX464->isHCG && cur_cg == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) gain_switch = 0x01 | 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) IMX464->isHCG = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) ret = imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) IMX464_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) IMX464_GROUP_HOLD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) if (gain_switch & 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) IMX464_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) gain_switch & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) IMX464_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) IMX464_GROUP_HOLD_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) //ag: echo 0 > /sys/devices/platform/ff510000.i2c/i2c-1/1-0037/cam_s_cg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) static ssize_t set_conversion_gain_status(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) ret = kstrtoint(buf, 0, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) if (!ret && status >= 0 && status < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) IMX464_set_conversion_gain(IMX464, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) dev_err(dev, "input 0 for LCG, 1 for HCG, cur %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) static struct device_attribute attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) __ATTR(cam_s_cg, S_IWUSR, NULL, set_conversion_gain_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) static int add_sysfs_interfaces(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) for (i = 0; i < ARRAY_SIZE(attributes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) if (device_create_file(dev, attributes + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) goto undo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) undo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) for (i--; i >= 0 ; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) device_remove_file(dev, attributes + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) dev_err(dev, "%s: failed to create sysfs interface\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) static int remove_sysfs_interfaces(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) for (i = 0; i < ARRAY_SIZE(attributes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) device_remove_file(dev, attributes + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) static int IMX464_get_channel_info(struct IMX464 *IMX464, struct rkmodule_channel_info *ch_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) ch_info->vc = IMX464->cur_mode->vc[ch_info->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) ch_info->width = IMX464->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) ch_info->height = IMX464->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) ch_info->bus_fmt = IMX464->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) static long IMX464_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) u32 i, h, w, stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) u32 *sync_mode = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) if (IMX464->cur_mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) ret = IMX464_set_hdrae(IMX464, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) else if (IMX464->cur_mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) ret = IMX464_set_hdrae_3frame(IMX464, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) IMX464_get_module_inf(IMX464, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) hdr->hdr_mode = IMX464->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) w = IMX464->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) h = IMX464->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) for (i = 0; i < IMX464->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) if (w == IMX464->support_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) h == IMX464->support_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) IMX464->support_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) IMX464->cur_mode = &IMX464->support_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) if (i == IMX464->cfg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) dev_err(&IMX464->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) w = IMX464->cur_mode->hts_def - IMX464->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) h = IMX464->cur_mode->vts_def - IMX464->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) __v4l2_ctrl_modify_range(IMX464->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) __v4l2_ctrl_modify_range(IMX464->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) IMX464_VTS_MAX - IMX464->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) IMX464->cur_vts = IMX464->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) pixel_rate = (u32)link_freq_menu_items[IMX464->cur_mode->mipi_freq_idx] / IMX464->cur_mode->bpp * 2 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) IMX464->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) __v4l2_ctrl_s_ctrl_int64(IMX464->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) __v4l2_ctrl_s_ctrl(IMX464->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) IMX464->cur_mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) ret = IMX464_set_conversion_gain(IMX464, (u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) ret = imx464_write_reg(IMX464->client, IMX464_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) IMX464_REG_VALUE_08BIT, IMX464_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) ret = imx464_write_reg(IMX464->client, IMX464_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) IMX464_REG_VALUE_08BIT, IMX464_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) ch_info = (struct rkmodule_channel_info *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) ret = IMX464_get_channel_info(IMX464, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) case RKMODULE_GET_SYNC_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) sync_mode = (u32 *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) *sync_mode = IMX464->sync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) case RKMODULE_SET_SYNC_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) sync_mode = (u32 *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) IMX464->sync_mode = *sync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) static long IMX464_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) u32 cg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) u32 stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) u32 sync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) ret = IMX464_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) ret = IMX464_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) ret = IMX464_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) ret = IMX464_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) ret = IMX464_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) ret = copy_from_user(&cg, up, sizeof(cg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) ret = IMX464_ioctl(sd, cmd, &cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) ret = IMX464_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) if (!ch_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) ret = IMX464_ioctl(sd, cmd, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) ret = copy_to_user(up, ch_info, sizeof(*ch_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) kfree(ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) case RKMODULE_GET_SYNC_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) ret = IMX464_ioctl(sd, cmd, &sync_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) ret = copy_to_user(up, &sync_mode, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) case RKMODULE_SET_SYNC_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) ret = copy_from_user(&sync_mode, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) ret = IMX464_ioctl(sd, cmd, &sync_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) static int IMX464_init_conversion_gain(struct IMX464 *IMX464, bool isHCG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) struct i2c_client *client = IMX464->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) if (isHCG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) val = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) ret = imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) IMX464_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) static int __IMX464_start_stream(struct IMX464 *IMX464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) ret = IMX464_write_array(IMX464->client, IMX464->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) ret = IMX464_init_conversion_gain(IMX464, IMX464->isHCG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) ret = __v4l2_ctrl_handler_setup(&IMX464->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) if (IMX464->has_init_exp && IMX464->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) ret = IMX464_ioctl(&IMX464->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) &IMX464->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) dev_err(&IMX464->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) if (IMX464->sync_mode == EXTERNAL_MASTER_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) ret |= IMX464_write_array(IMX464->client, IMX464_external_sync_master_start_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) v4l2_err(&IMX464->subdev, "cur externam master mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) } else if (IMX464->sync_mode == INTERNAL_MASTER_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) ret |= IMX464_write_array(IMX464->client, IMX464_interal_sync_master_start_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) v4l2_err(&IMX464->subdev, "cur intertal master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) } else if (IMX464->sync_mode == SLAVE_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) ret |= IMX464_write_array(IMX464->client, IMX464_slave_start_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) v4l2_err(&IMX464->subdev, "cur slave mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) if (IMX464->sync_mode == NO_SYNC_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) ret = imx464_write_reg(IMX464->client, IMX464_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) IMX464_REG_VALUE_08BIT, IMX464_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) usleep_range(30000, 40000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) ret |= imx464_write_reg(IMX464->client, IMX464_REG_MARSTER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) IMX464_REG_VALUE_08BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) ret |= imx464_write_reg(IMX464->client, IMX464_REG_MARSTER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) IMX464_REG_VALUE_08BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static int __IMX464_stop_stream(struct IMX464 *IMX464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) IMX464->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) ret = imx464_write_reg(IMX464->client, IMX464_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) IMX464_REG_VALUE_08BIT, IMX464_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) if (IMX464->sync_mode == EXTERNAL_MASTER_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) ret |= IMX464_write_array(IMX464->client, IMX464_external_sync_master_stop_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) else if (IMX464->sync_mode == INTERNAL_MASTER_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) ret |= IMX464_write_array(IMX464->client, IMX464_interal_sync_master_stop_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) static int IMX464_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) struct i2c_client *client = IMX464->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) mutex_lock(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) if (on == IMX464->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) ret = __IMX464_start_stream(IMX464);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) __IMX464_stop_stream(IMX464);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) IMX464->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) mutex_unlock(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static int IMX464_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) struct i2c_client *client = IMX464->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) mutex_lock(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) if (IMX464->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) ret = IMX464_write_array(IMX464->client, IMX464_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) IMX464->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) IMX464->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) mutex_unlock(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static inline u32 IMX464_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) return DIV_ROUND_UP(cycles, IMX464_XVCLK_FREQ_37M / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) static int __IMX464_power_on(struct IMX464 *IMX464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) struct device *dev = &IMX464->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) if (!IS_ERR_OR_NULL(IMX464->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) ret = pinctrl_select_state(IMX464->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) IMX464->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) ret = clk_set_rate(IMX464->xvclk, IMX464->cur_mode->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) dev_warn(dev, "Failed to set xvclk rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) if (clk_get_rate(IMX464->xvclk) != IMX464->cur_mode->mclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) dev_warn(dev, "xvclk mismatched, %lu\n", clk_get_rate(IMX464->xvclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) IMX464->cur_mclk = IMX464->cur_mode->mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) ret = clk_prepare_enable(IMX464->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) if (!IS_ERR(IMX464->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) gpiod_set_value_cansleep(IMX464->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) ret = regulator_bulk_enable(IMX464_NUM_SUPPLIES, IMX464->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) usleep_range(15000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) if (!IS_ERR(IMX464->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) gpiod_set_value_cansleep(IMX464->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) if (!IS_ERR(IMX464->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) gpiod_set_value_cansleep(IMX464->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) delay_us = IMX464_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) clk_disable_unprepare(IMX464->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) static void __IMX464_power_off(struct IMX464 *IMX464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) struct device *dev = &IMX464->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) if (!IS_ERR(IMX464->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) gpiod_set_value_cansleep(IMX464->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) clk_disable_unprepare(IMX464->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) if (!IS_ERR(IMX464->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) gpiod_set_value_cansleep(IMX464->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) if (!IS_ERR_OR_NULL(IMX464->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) ret = pinctrl_select_state(IMX464->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) IMX464->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) regulator_bulk_disable(IMX464_NUM_SUPPLIES, IMX464->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) usleep_range(15000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) static int IMX464_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) return __IMX464_power_on(IMX464);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) static int IMX464_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) __IMX464_power_off(IMX464);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) static int IMX464_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) const struct IMX464_mode *def_mode = &IMX464->support_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) mutex_lock(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) mutex_unlock(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) static int IMX464_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) if (fie->index >= IMX464->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) fie->code = IMX464->support_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) fie->width = IMX464->support_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) fie->height = IMX464->support_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) fie->interval = IMX464->support_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) fie->reserved[0] = IMX464->support_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) #define DST_WIDTH 2560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) #define DST_HEIGHT 1520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) * The resolution of the driver configuration needs to be exactly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) * the same as the current output resolution of the sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) * the input width of the isp needs to be 16 aligned,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) * the input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) * Can be cropped to standard resolution by this function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) * otherwise it will crop out strange resolution according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) * to the alignment rules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) static int IMX464_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) sel->r.left = CROP_START(IMX464->cur_mode->width, DST_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) sel->r.width = DST_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) sel->r.top = CROP_START(IMX464->cur_mode->height, DST_HEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) sel->r.height = DST_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) static const struct dev_pm_ops IMX464_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) SET_RUNTIME_PM_OPS(IMX464_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) IMX464_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) static const struct v4l2_subdev_internal_ops IMX464_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .open = IMX464_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) static const struct v4l2_subdev_core_ops IMX464_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .s_power = IMX464_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) .ioctl = IMX464_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) .compat_ioctl32 = IMX464_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) static const struct v4l2_subdev_video_ops IMX464_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) .s_stream = IMX464_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) .g_frame_interval = IMX464_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) static const struct v4l2_subdev_pad_ops IMX464_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .enum_mbus_code = IMX464_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .enum_frame_size = IMX464_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .enum_frame_interval = IMX464_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .get_fmt = IMX464_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .set_fmt = IMX464_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) .get_selection = IMX464_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) .get_mbus_config = IMX464_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) static const struct v4l2_subdev_ops IMX464_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) .core = &IMX464_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) .video = &IMX464_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) .pad = &IMX464_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) static int IMX464_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) struct IMX464 *IMX464 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) struct IMX464, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) struct i2c_client *client = IMX464->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) const struct IMX464_mode *mode = IMX464->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) u32 vts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) u32 shr0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) u32 flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) if (mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) max = IMX464->cur_mode->height + ctrl->val - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) __v4l2_ctrl_modify_range(IMX464->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) IMX464->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) IMX464->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) IMX464->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) if (mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) shr0 = IMX464->cur_vts - ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) ret = imx464_write_reg(IMX464->client, IMX464_LF_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) IMX464_FETCH_EXP_L(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) ret |= imx464_write_reg(IMX464->client, IMX464_LF_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) IMX464_FETCH_EXP_M(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) ret |= imx464_write_reg(IMX464->client, IMX464_LF_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) IMX464_FETCH_EXP_H(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) dev_err(&client->dev, "set exposure 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) if (mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) ret = imx464_write_reg(IMX464->client, IMX464_LF_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) IMX464_FETCH_GAIN_H(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) ret |= imx464_write_reg(IMX464->client, IMX464_LF_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) IMX464_FETCH_GAIN_L(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) dev_err(&client->dev, "set analog gain 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) vts = ctrl->val + IMX464->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) if (mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) vts = (vts + 3) / 4 * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) IMX464->cur_vts = vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) vts /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) } else if (mode->hdr_mode == HDR_X3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) vts = (vts + 5) / 6 * 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) IMX464->cur_vts = vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) vts /= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) IMX464->cur_vts = vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) ret = imx464_write_reg(IMX464->client, IMX464_VTS_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) IMX464_FETCH_VTS_L(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) ret |= imx464_write_reg(IMX464->client, IMX464_VTS_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) IMX464_FETCH_VTS_M(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) ret |= imx464_write_reg(IMX464->client, IMX464_VTS_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) IMX464_FETCH_VTS_H(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) dev_err(&client->dev, "set vts 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) vts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) ret = imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) IMX464_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) IMX464_GROUP_HOLD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) ret |= imx464_write_reg(IMX464->client, IMX464_HREVERSE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) IMX464_REG_VALUE_08BIT, !!ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) IMX464_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) IMX464_GROUP_HOLD_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) flip = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) ret = imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) IMX464_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) IMX464_GROUP_HOLD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) ret |= imx464_write_reg(IMX464->client, IMX464_VREVERSE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) IMX464_REG_VALUE_08BIT, !!flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) if (flip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) ret |= imx464_write_reg(IMX464->client, 0x3074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) IMX464_REG_VALUE_08BIT, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) ret |= imx464_write_reg(IMX464->client, 0x3075,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) IMX464_REG_VALUE_08BIT, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) ret |= imx464_write_reg(IMX464->client, 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) IMX464_REG_VALUE_08BIT, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) ret |= imx464_write_reg(IMX464->client, 0x30ad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) IMX464_REG_VALUE_08BIT, 0x7e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) ret |= imx464_write_reg(IMX464->client, 0x30b6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) IMX464_REG_VALUE_08BIT, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) ret |= imx464_write_reg(IMX464->client, 0x30b7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) IMX464_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) ret |= imx464_write_reg(IMX464->client, 0x30d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) IMX464_REG_VALUE_08BIT, 0x45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) ret |= imx464_write_reg(IMX464->client, 0x3114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) IMX464_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) ret |= imx464_write_reg(IMX464->client, 0x3074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) IMX464_REG_VALUE_08BIT, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) ret |= imx464_write_reg(IMX464->client, 0x3075,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) IMX464_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) ret |= imx464_write_reg(IMX464->client, 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) IMX464_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) ret |= imx464_write_reg(IMX464->client, 0x30ad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) IMX464_REG_VALUE_08BIT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) ret |= imx464_write_reg(IMX464->client, 0x30b6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) IMX464_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) ret |= imx464_write_reg(IMX464->client, 0x30b7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) IMX464_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) ret |= imx464_write_reg(IMX464->client, 0x30d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) IMX464_REG_VALUE_08BIT, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) ret |= imx464_write_reg(IMX464->client, 0x3114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) IMX464_REG_VALUE_08BIT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) ret |= imx464_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) IMX464_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) IMX464_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) IMX464_GROUP_HOLD_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) static const struct v4l2_ctrl_ops IMX464_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) .s_ctrl = IMX464_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) static int IMX464_initialize_controls(struct IMX464 *IMX464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) const struct IMX464_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) handler = &IMX464->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) mode = IMX464->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) handler->lock = &IMX464->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) IMX464->link_freq = v4l2_ctrl_new_int_menu(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) 1, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) __v4l2_ctrl_s_ctrl(IMX464->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) IMX464->cur_mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) pixel_rate = (u32)link_freq_menu_items[mode->mipi_freq_idx] / mode->bpp * 2 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) IMX464->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) IMX464->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) V4L2_CID_PIXEL_RATE, 0, IMX464_10BIT_HDR2_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) 1, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) IMX464->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) if (IMX464->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) IMX464->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) IMX464->vblank = v4l2_ctrl_new_std(handler, &IMX464_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) IMX464_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) IMX464->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) exposure_max = mode->vts_def - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) IMX464->exposure = v4l2_ctrl_new_std(handler, &IMX464_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) V4L2_CID_EXPOSURE, IMX464_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) exposure_max, IMX464_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) IMX464->anal_a_gain = v4l2_ctrl_new_std(handler, &IMX464_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) V4L2_CID_ANALOGUE_GAIN, IMX464_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) IMX464_GAIN_MAX, IMX464_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) IMX464_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) v4l2_ctrl_new_std(handler, &IMX464_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) v4l2_ctrl_new_std(handler, &IMX464_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) dev_err(&IMX464->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) IMX464->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) IMX464->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) IMX464->isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) static int IMX464_check_sensor_id(struct IMX464 *IMX464,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) struct device *dev = &IMX464->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) ret = IMX464_read_reg(client, IMX464_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) IMX464_REG_VALUE_08BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) dev_info(dev, "Detected IMX464 id %06x\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) static int IMX464_configure_regulators(struct IMX464 *IMX464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) for (i = 0; i < IMX464_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) IMX464->supplies[i].supply = IMX464_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) return devm_regulator_bulk_get(&IMX464->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) IMX464_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) IMX464->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) static int IMX464_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) struct IMX464 *IMX464;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) const char *sync_mode_name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) IMX464 = devm_kzalloc(dev, sizeof(*IMX464), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) if (!IMX464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) &IMX464->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) &IMX464->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) &IMX464->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) &IMX464->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) ret = of_property_read_string(node, RKMODULE_CAMERA_SYNC_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) &sync_mode_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) IMX464->sync_mode = NO_SYNC_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) dev_err(dev, "could not get sync mode!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) if (strcmp(sync_mode_name, RKMODULE_EXTERNAL_MASTER_MODE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) IMX464->sync_mode = EXTERNAL_MASTER_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) else if (strcmp(sync_mode_name, RKMODULE_INTERNAL_MASTER_MODE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) IMX464->sync_mode = INTERNAL_MASTER_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) else if (strcmp(sync_mode_name, RKMODULE_SLAVE_MODE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) IMX464->sync_mode = SLAVE_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) hdr_mode = NO_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) dev_warn(dev, " Get hdr mode failed! no hdr default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) IMX464->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) &IMX464->bus_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) dev_err(dev, "Failed to get bus cfg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) if (IMX464->bus_cfg.bus.mipi_csi2.num_data_lanes == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) IMX464->support_modes = supported_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) IMX464->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) IMX464->support_modes = supported_modes_2lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) IMX464->cfg_num = ARRAY_SIZE(supported_modes_2lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) for (i = 0; i < IMX464->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) if (hdr_mode == IMX464->support_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) IMX464->cur_mode = &IMX464->support_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) IMX464->cur_mode = &IMX464->support_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) IMX464->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) if (IS_ERR(IMX464->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) IMX464->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) if (IS_ERR(IMX464->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) IMX464->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) if (IS_ERR(IMX464->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) IMX464->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) if (!IS_ERR(IMX464->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) IMX464->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) pinctrl_lookup_state(IMX464->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) if (IS_ERR(IMX464->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) IMX464->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) pinctrl_lookup_state(IMX464->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) if (IS_ERR(IMX464->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) ret = IMX464_configure_regulators(IMX464);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) mutex_init(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) sd = &IMX464->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) v4l2_i2c_subdev_init(sd, client, &IMX464_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) ret = IMX464_initialize_controls(IMX464);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) ret = __IMX464_power_on(IMX464);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) ret = IMX464_check_sensor_id(IMX464, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) sd->internal_ops = &IMX464_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) IMX464->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) ret = media_entity_pads_init(&sd->entity, 1, &IMX464->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) if (strcmp(IMX464->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) IMX464->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) IMX464_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) add_sysfs_interfaces(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) __IMX464_power_off(IMX464);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) v4l2_ctrl_handler_free(&IMX464->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) mutex_destroy(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) static int IMX464_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) struct IMX464 *IMX464 = to_IMX464(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) v4l2_ctrl_handler_free(&IMX464->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) mutex_destroy(&IMX464->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) __IMX464_power_off(IMX464);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) remove_sysfs_interfaces(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) static const struct of_device_id IMX464_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) { .compatible = "sony,imx464" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) MODULE_DEVICE_TABLE(of, IMX464_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) static const struct i2c_device_id IMX464_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) { "sony,imx464", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) static struct i2c_driver IMX464_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) .name = IMX464_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) .pm = &IMX464_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) .of_match_table = of_match_ptr(IMX464_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) .probe = &IMX464_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) .remove = &IMX464_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) .id_table = IMX464_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) return i2c_add_driver(&IMX464_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) i2c_del_driver(&IMX464_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) MODULE_DESCRIPTION("Sony IMX464 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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