^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * imx347 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 add conversion gain control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X02 add debug interface for conversion gain control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X03 support enum sensor fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X04 fix setting flow error according to datasheet and fix hdr gain error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MIPI_FREQ_360M 360000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MIPI_FREQ_594M 594000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX347_10BIT_LINEAR_PIXEL_RATE (MIPI_FREQ_594M * 2 / 10 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX347_10BIT_HDR2_PIXEL_RATE (MIPI_FREQ_594M * 2 / 10 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX347_12BIT_PIXEL_RATE (MIPI_FREQ_360M * 2 / 12 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX347_XVCLK_FREQ_37M 37125000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX347_XVCLK_FREQ_24M 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CHIP_ID 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX347_REG_CHIP_ID 0x3057
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX347_REG_CTRL_MODE 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX347_MODE_SW_STANDBY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX347_MODE_STREAMING 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX347_REG_MASTER_MODE 0x3002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX347_MASTER_MODE_STOP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX347_MASTER_MODE_START 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX347_REG_RESTART_MODE 0x3004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX347_RESTART_MODE_START 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX347_RESTART_MODE_STOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX347_GAIN_SWITCH_REG 0x3019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX347_LF_GAIN_REG_H 0x30E9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX347_LF_GAIN_REG_L 0x30E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX347_SF1_GAIN_REG_H 0x30EB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX347_SF1_GAIN_REG_L 0x30EA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX347_LF_EXPO_REG_H 0x305A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX347_LF_EXPO_REG_M 0x3059
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX347_LF_EXPO_REG_L 0x3058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX347_SF1_EXPO_REG_H 0x305E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX347_SF1_EXPO_REG_M 0x305D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX347_SF1_EXPO_REG_L 0x305C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX347_RHS1_REG_H 0x306a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX347_RHS1_REG_M 0x3069
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX347_RHS1_REG_L 0x3068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX347_EXPOSURE_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX347_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX347_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX347_GAIN_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IMX347_GAIN_MAX 0xee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX347_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX347_GAIN_DEFAULT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX347_FETCH_GAIN_H(VAL) (((VAL) >> 8) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX347_FETCH_GAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX347_FETCH_EXP_H(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX347_FETCH_EXP_M(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX347_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX347_FETCH_RHS1_H(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX347_FETCH_RHS1_M(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX347_FETCH_RHS1_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX347_FETCH_VTS_H(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX347_FETCH_VTS_M(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX347_FETCH_VTS_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX347_GROUP_HOLD_REG 0x3001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX347_GROUP_HOLD_START 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX347_GROUP_HOLD_END 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX347_VTS_REG_L 0x3030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX347_VTS_REG_M 0x3031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX347_VTS_REG_H 0x3032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX347_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX347_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX347_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX347_2LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX347_4LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX347_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX347_VREVERSE_REG 0x304f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX347_HREVERSE_REG 0x304e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RHS1_MAX 3113 // <2*BRL=2*1556 && 4n+1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SHR1_MIN 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BRL 1556
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static bool g_isHCG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMX347_NAME "imx347"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const char * const imx347_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX347_NUM_SUPPLIES ARRAY_SIZE(imx347_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct imx347_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u8 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct imx347 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct regulator_bulk_data supplies[IMX347_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct v4l2_ctrl *anal_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const struct imx347_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 cur_pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 cur_link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define to_imx347(sd) container_of(sd, struct imx347, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const struct regval imx347_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct regval imx347_linear_10bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x300C, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x300D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3018, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x302C, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x302E, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x302F, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3030, 0xBC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3031, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3032, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3034, 0xDC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3035, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3048, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3049, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x304A, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x304B, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x304C, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3056, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3057, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3058, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3059, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3068, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3069, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x30BE, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x30C6, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x30CE, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x30D8, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x30D9, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3110, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x314C, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x315A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3168, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x319D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x319E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x31D7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3200, 0x11},/* Each frame gain adjustment disabed in linear mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3202, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3288, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x328C, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x328E, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3415, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3418, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3428, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x349E, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x34A2, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x34A4, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x34A6, 0x8E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x34AA, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x367C, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x367E, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3680, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3682, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x371D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x375D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x375E, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x375F, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3760, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x376A, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x376B, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x376C, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x376D, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x376E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x376F, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x3770, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x3776, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x3778, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x377A, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x377B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x377C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x377D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x377E, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x377F, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3780, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3781, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3782, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3784, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x3788, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x378A, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x378B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x378C, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x378D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x378E, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x378F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3790, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3791, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3792, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3793, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3794, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3795, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3796, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x3798, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x3A01, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x3A18, 0x8F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3A1A, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3A1C, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x3A1E, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x3A1F, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x3A20, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x3A22, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x3A24, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x3A26, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x3A28, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const struct regval imx347_hdr_2x_10bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x300C, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x300D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3018, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x302C, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x302E, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x302F, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3030, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x3031, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x3032, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x3034, 0xEE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x3035, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x3048, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x3049, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x304A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x304B, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x304C, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3056, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x3057, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x3058, 0x4A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x3059, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x3068, 0xD1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x3069, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x30BE, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x30C6, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x30CE, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x30D8, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x30D9, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x3110, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x314C, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x315A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3168, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x319D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x319E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x31D7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x3200, 0x10},/* Each frame gain adjustment EN in hdr mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3202, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x3288, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x328C, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x328E, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x3415, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3418, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3428, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x349E, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x34A2, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x34A4, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x34A6, 0x8E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x34AA, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x367C, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x367E, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3680, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3682, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x371D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x375D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x375E, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x375F, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x3760, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x376A, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x376B, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x376C, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x376D, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x376E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x376F, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x3770, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x3776, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x3778, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x377A, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x377B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x377C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x377D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x377E, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x377F, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x3780, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x3781, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x3782, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x3784, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x3788, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x378A, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x378B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x378C, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x378D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x378E, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x378F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3790, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3791, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3792, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3793, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3794, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x3795, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x3796, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x3798, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x3A01, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x3A18, 0x8F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x3A1A, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x3A1C, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x3A1E, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x3A1F, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3A20, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3A22, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x3A24, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x3A26, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x3A28, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const struct regval imx347_linear_12bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x300C, 0x3B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x300D, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x3018, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x302C, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x302E, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x302F, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x3030, 0x6B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x3031, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x3032, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x3034, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x3035, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x3048, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x3049, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x304A, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x304B, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x304C, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x3050, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x3056, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x3057, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x3058, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x3059, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x3068, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x3069, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x30BE, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x30C6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x30CE, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x30D8, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x30D9, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x3110, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x314C, 0xF0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x315A, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x3168, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x319D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x319E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x31D7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x3200, 0x11},/* Each frame gain adjustment disabed in linear mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x3202, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x3288, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x328C, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x328E, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x3415, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x3418, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x3428, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x349E, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x34A2, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x34A4, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x34A6, 0x8E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x34AA, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x367C, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x367E, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x3680, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x3682, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x371D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x375D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x375E, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x375F, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x3760, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x376A, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x376B, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x376C, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x376D, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x376E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x376F, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x3770, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x3776, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x3778, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x377A, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x377B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x377C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x377D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x377E, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x377F, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x3780, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x3781, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x3782, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x3784, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x3788, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x378A, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x378B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x378C, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x378D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x378E, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x378F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x3790, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x3791, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x3792, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x3793, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x3794, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x3795, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x3796, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x3798, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x3A01, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x3A18, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x3A1A, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x3A1C, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x3A1E, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x3A1F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x3A20, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x3A22, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x3A24, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x3A26, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x3A28, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const struct regval imx347_hdr_2x_12bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x300C, 0x3B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x300D, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x3018, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x302C, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x302E, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x302F, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x3030, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x3031, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x3032, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x3034, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x3035, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x3048, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x3049, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x304A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x304B, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x304C, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x3050, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x3056, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x3057, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x3058, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x3059, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x3068, 0xD9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x3069, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x30BE, 0x5E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x30C6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x30CE, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x30D8, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x30D9, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x3110, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x314C, 0xF0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x315A, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x3168, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x319D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x319E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x31D7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x3200, 0x10},/* Each frame gain adjustment EN in hdr mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x3202, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x3288, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x328C, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x328E, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x3415, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x3418, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x3428, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x349E, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x34A2, 0x9A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x34A4, 0x8A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x34A6, 0x8E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x34AA, 0xD8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x367C, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {0x367E, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0x3680, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x3682, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x371D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x375D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x375E, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x375F, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x3760, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x376A, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x376B, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x376C, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x376D, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x376E, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x376F, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x3770, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x3776, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x3778, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x377A, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x377B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x377C, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x377D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {0x377E, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {0x377F, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {0x3780, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {0x3781, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {0x3782, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {0x3784, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {0x3788, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {0x378A, 0xCA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0x378B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {0x378C, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {0x378D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {0x378E, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {0x378F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {0x3790, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {0x3791, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {0x3792, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {0x3793, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {0x3794, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {0x3795, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {0x3796, 0x7F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x3798, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x3A01, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x3A18, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x3A1A, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x3A1C, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {0x3A1E, 0xBF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {0x3A1F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {0x3A20, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {0x3A22, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {0x3A24, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {0x3A26, 0x4F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {0x3A28, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * The width and height must be configured to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * the same as the current output resolution of the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * The input width of the isp needs to be 16 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * The input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * If the width or height does not meet the alignment rules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * you can configure the cropping parameters with the following function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * crop out the appropriate resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * struct v4l2_subdev_pad_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * .get_selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static const struct imx347_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .width = 2712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .height = 1536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .exp_def = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .hts_def = 0x05dc * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .vts_def = 0x07bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .reg_list = imx347_linear_10bit_2688x1520_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .width = 2712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .height = 1536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .exp_def = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .hts_def = 0x02ee * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .vts_def = 0x07bc * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .reg_list = imx347_hdr_2x_10bit_2688x1520_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .height = 1538,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .denominator = 299960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .exp_def = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .hts_def = 0x02EE * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .vts_def = 0x0A6B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .reg_list = imx347_linear_12bit_2688x1520_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .bpp = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .height = 1538,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .exp_def = 0x0240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .hts_def = 0x02ee * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .vts_def = 0x0640 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .reg_list = imx347_hdr_2x_12bit_2688x1520_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .bpp = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) MIPI_FREQ_360M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) MIPI_FREQ_594M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int imx347_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static int imx347_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = imx347_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) IMX347_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static int imx347_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static int imx347_get_reso_dist(const struct imx347_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static const struct imx347_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) imx347_find_best_fit(struct imx347 *imx347, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) for (i = 0; i < imx347->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) dist = imx347_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) supported_modes[i].bus_fmt == framefmt->code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static int imx347_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) const struct imx347_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct device *dev = &imx347->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mutex_lock(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) mode = imx347_find_best_fit(imx347, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) mutex_unlock(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) imx347->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) __v4l2_ctrl_modify_range(imx347->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) __v4l2_ctrl_modify_range(imx347->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) IMX347_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) imx347->cur_vts = imx347->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) imx347->cur_pixel_rate = IMX347_10BIT_LINEAR_PIXEL_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) else if (mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) imx347->cur_pixel_rate = IMX347_10BIT_HDR2_PIXEL_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) imx347->cur_link_freq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) clk_disable_unprepare(imx347->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ret = clk_set_rate(imx347->xvclk, IMX347_XVCLK_FREQ_37M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_err(dev, "Failed to set xvclk rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (clk_get_rate(imx347->xvclk) != IMX347_XVCLK_FREQ_37M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dev_err(dev, "xvclk mismatched\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ret = clk_prepare_enable(imx347->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) imx347->cur_pixel_rate = IMX347_12BIT_PIXEL_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) imx347->cur_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) clk_disable_unprepare(imx347->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ret = clk_set_rate(imx347->xvclk, IMX347_XVCLK_FREQ_24M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dev_err(dev, "Failed to set xvclk rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (clk_get_rate(imx347->xvclk) != IMX347_XVCLK_FREQ_24M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) dev_err(dev, "xvclk mismatched\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret = clk_prepare_enable(imx347->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) __v4l2_ctrl_s_ctrl_int64(imx347->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) imx347->cur_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) __v4l2_ctrl_s_ctrl(imx347->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) imx347->cur_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) mutex_unlock(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static int imx347_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) const struct imx347_mode *mode = imx347->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) mutex_lock(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) mutex_unlock(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) mutex_unlock(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static int imx347_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) code->code = imx347->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static int imx347_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (fse->index >= imx347->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static int imx347_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) const struct imx347_mode *mode = imx347->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) mutex_lock(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) mutex_unlock(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int imx347_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) const struct imx347_mode *mode = imx347->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) val = 1 << (IMX347_2LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) val = 1 << (IMX347_4LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) val = 1 << (IMX347_4LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static void imx347_get_module_inf(struct imx347 *imx347,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) strscpy(inf->base.sensor, IMX347_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) strscpy(inf->base.module, imx347->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) strscpy(inf->base.lens, imx347->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static int imx347_set_hdrae(struct imx347 *imx347,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct i2c_client *client = imx347->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) u32 l_a_gain, m_a_gain, s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) u32 gain_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) u32 shr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u32 shr0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) u32 rhs1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) u32 rhs1_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static int rhs1_old = 209;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) int rhs1_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) u32 fsc = imx347->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) u8 cg_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (!imx347->has_init_exp && !imx347->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) imx347->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) imx347->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dev_dbg(&imx347->client->dev, "imx347 don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) l_a_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) m_a_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) s_a_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) l_exp_time, m_exp_time, s_exp_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) l_a_gain, m_a_gain, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (imx347->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) //2 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) l_a_gain = m_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) cg_mode = ae->middle_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (!g_isHCG && cg_mode == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) gain_switch = 0x01 | 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) g_isHCG = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) } else if (g_isHCG && cg_mode == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) gain_switch = 0x00 | 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) g_isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) IMX347_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) IMX347_GROUP_HOLD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) //gain effect n+1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) IMX347_LF_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) IMX347_FETCH_GAIN_H(l_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) IMX347_LF_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) IMX347_FETCH_GAIN_L(l_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) IMX347_SF1_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) IMX347_FETCH_GAIN_H(s_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) IMX347_SF1_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) IMX347_FETCH_GAIN_L(s_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (gain_switch & 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) IMX347_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) gain_switch & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) //long exposure and short exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) shr0 = fsc - l_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) rhs1_max = (RHS1_MAX > (shr0 - 9)) ? (shr0 - 9) : RHS1_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) rhs1 = SHR1_MIN + s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) dev_dbg(&client->dev, "line(%d) rhs1 %d\n", __LINE__, rhs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (rhs1 < 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) rhs1 = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) else if (rhs1 > rhs1_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) rhs1 = rhs1_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) dev_dbg(&client->dev, "line(%d) rhs1 %d\n", __LINE__, rhs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) //Dynamic adjustment rhs1 must meet the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) rhs1_change_limit = rhs1_old + 2 * BRL - fsc + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) rhs1_change_limit = (rhs1_change_limit < 13) ? 13 : rhs1_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (rhs1 < rhs1_change_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) rhs1 = rhs1_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) "line(%d) rhs1 %d,short time %d rhs1_old %d test %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) __LINE__, rhs1, s_exp_time, rhs1_old,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) (rhs1_old + 2 * BRL - fsc + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) rhs1 = (rhs1 >> 2) * 4 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) rhs1_old = rhs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (rhs1 < s_exp_time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) shr1 = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) s_exp_time = rhs1 - shr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) shr1 = rhs1 - s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (shr1 < 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) shr1 = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) else if (shr1 > (rhs1 - 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) shr1 = rhs1 - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (shr0 < (rhs1 + 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) shr0 = rhs1 + 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) else if (shr0 > (fsc - 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) shr0 = fsc - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) "fsc=%d,RHS1_MAX=%d,SHR1_MIN=%d,rhs1_max=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) fsc, RHS1_MAX, SHR1_MIN, rhs1_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) "l_exp_time=%d,s_exp_time=%d,shr0=%d,shr1=%d,rhs1=%d,l_a_gain=%d,s_a_gain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) l_exp_time, s_exp_time, shr0, shr1, rhs1, l_a_gain, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) //time effect n+2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) IMX347_RHS1_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) IMX347_FETCH_RHS1_L(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) IMX347_RHS1_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) IMX347_FETCH_RHS1_M(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) IMX347_RHS1_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) IMX347_FETCH_RHS1_H(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) IMX347_SF1_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) IMX347_FETCH_EXP_L(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) IMX347_SF1_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) IMX347_FETCH_EXP_M(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) IMX347_SF1_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) IMX347_FETCH_EXP_H(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) IMX347_LF_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) IMX347_FETCH_EXP_L(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) IMX347_LF_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) IMX347_FETCH_EXP_M(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) IMX347_LF_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) IMX347_FETCH_EXP_H(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) IMX347_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) IMX347_GROUP_HOLD_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static int imx347_set_conversion_gain(struct imx347 *imx347, u32 *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct i2c_client *client = imx347->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) int cur_cg = *cg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) u32 gain_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (g_isHCG && cur_cg == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) gain_switch = 0x00 | 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) g_isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) } else if (!g_isHCG && cur_cg == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) gain_switch = 0x01 | 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) g_isHCG = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ret = imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) IMX347_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) IMX347_GROUP_HOLD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (gain_switch & 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) IMX347_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) gain_switch & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) ret |= imx347_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) IMX347_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) IMX347_GROUP_HOLD_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) //ag: echo 0 > /sys/devices/platform/ff510000.i2c/i2c-1/1-0037/cam_s_cg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static ssize_t set_conversion_gain_status(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ret = kstrtoint(buf, 0, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (!ret && status >= 0 && status < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) imx347_set_conversion_gain(imx347, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) dev_err(dev, "input 0 for LCG, 1 for HCG, cur %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static struct device_attribute attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) __ATTR(cam_s_cg, S_IWUSR, NULL, set_conversion_gain_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static int add_sysfs_interfaces(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) for (i = 0; i < ARRAY_SIZE(attributes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (device_create_file(dev, attributes + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) goto undo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) undo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) for (i--; i >= 0 ; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) device_remove_file(dev, attributes + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) dev_err(dev, "%s: failed to create sysfs interface\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static long imx347_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) u32 i, h, w, stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) ret = imx347_set_hdrae(imx347, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) imx347_get_module_inf(imx347, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) hdr->hdr_mode = imx347->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) w = imx347->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) h = imx347->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) for (i = 0; i < imx347->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) imx347->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (i == imx347->cfg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dev_err(&imx347->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) w = imx347->cur_mode->hts_def - imx347->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) h = imx347->cur_mode->vts_def - imx347->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) __v4l2_ctrl_modify_range(imx347->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) __v4l2_ctrl_modify_range(imx347->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) IMX347_VTS_MAX - imx347->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) imx347->cur_vts = imx347->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (imx347->cur_mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (imx347->cur_mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) imx347->cur_pixel_rate = IMX347_10BIT_LINEAR_PIXEL_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) else if (imx347->cur_mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) imx347->cur_pixel_rate = IMX347_10BIT_HDR2_PIXEL_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) __v4l2_ctrl_s_ctrl_int64(imx347->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) imx347->cur_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) ret = imx347_set_conversion_gain(imx347, (u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) ret = imx347_write_reg(imx347->client, IMX347_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) IMX347_REG_VALUE_08BIT, IMX347_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ret = imx347_write_reg(imx347->client, IMX347_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) IMX347_REG_VALUE_08BIT, IMX347_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static long imx347_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) u32 cg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) u32 stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) ret = imx347_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) ret = imx347_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (copy_from_user(hdr, up, sizeof(*hdr))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) ret = imx347_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (copy_from_user(hdrae, up, sizeof(*hdrae))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) ret = imx347_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (copy_from_user(&cg, up, sizeof(cg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) ret = imx347_ioctl(sd, cmd, &cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (copy_from_user(&stream, up, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) ret = imx347_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static int imx347_init_conversion_gain(struct imx347 *imx347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) struct i2c_client *client = imx347->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ret = imx347_write_reg(client, IMX347_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) IMX347_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) g_isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static int __imx347_start_stream(struct imx347 *imx347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) ret = imx347_write_array(imx347->client, imx347->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) ret = imx347_init_conversion_gain(imx347);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) ret = __v4l2_ctrl_handler_setup(&imx347->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (imx347->has_init_exp && imx347->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) ret = imx347_ioctl(&imx347->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) &imx347->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) dev_err(&imx347->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) ret = imx347_write_reg(imx347->client, IMX347_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) IMX347_REG_VALUE_08BIT, IMX347_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) ret |= imx347_write_reg(imx347->client, IMX347_REG_MASTER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) IMX347_REG_VALUE_08BIT, IMX347_MASTER_MODE_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static int __imx347_stop_stream(struct imx347 *imx347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) u32 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) imx347->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) ret = imx347_write_reg(imx347->client, IMX347_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) IMX347_REG_VALUE_08BIT, IMX347_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) ret |= imx347_write_reg(imx347->client, IMX347_REG_MASTER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) IMX347_REG_VALUE_08BIT, IMX347_MASTER_MODE_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) ret |= imx347_read_reg(imx347->client, IMX347_REG_RESTART_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) IMX347_REG_VALUE_08BIT, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) dev_dbg(&imx347->client->dev, "reg 0x3004 = 0x%x\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (value == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) ret |= imx347_write_reg(imx347->client, IMX347_REG_RESTART_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) IMX347_REG_VALUE_08BIT, IMX347_RESTART_MODE_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) ret |= imx347_write_reg(imx347->client, IMX347_REG_RESTART_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) IMX347_REG_VALUE_08BIT, IMX347_RESTART_MODE_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static int imx347_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) struct i2c_client *client = imx347->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) dev_dbg(&imx347->client->dev, "s_stream: %d. %dx%d, hdr: %d, bpp: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) on, imx347->cur_mode->width, imx347->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) imx347->cur_mode->hdr_mode, imx347->cur_mode->bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) mutex_lock(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) if (on == imx347->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ret = __imx347_start_stream(imx347);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) __imx347_stop_stream(imx347);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) imx347->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) mutex_unlock(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static int imx347_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) struct i2c_client *client = imx347->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) mutex_lock(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (imx347->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) ret = imx347_write_array(imx347->client, imx347_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) imx347->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) imx347->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) mutex_unlock(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) static inline u32 imx347_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) return DIV_ROUND_UP(cycles, IMX347_XVCLK_FREQ_37M / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static int __imx347_power_on(struct imx347 *imx347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) struct device *dev = &imx347->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) unsigned long mclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (!IS_ERR_OR_NULL(imx347->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) ret = pinctrl_select_state(imx347->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) imx347->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (imx347->cur_mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) mclk = IMX347_XVCLK_FREQ_37M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) mclk = IMX347_XVCLK_FREQ_24M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ret = clk_set_rate(imx347->xvclk, mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) dev_warn(dev, "Failed to set xvclk rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (clk_get_rate(imx347->xvclk) != mclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) dev_warn(dev, "xvclk mismatched\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) ret = clk_prepare_enable(imx347->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (!IS_ERR(imx347->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) gpiod_set_value_cansleep(imx347->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) ret = regulator_bulk_enable(IMX347_NUM_SUPPLIES, imx347->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (!IS_ERR(imx347->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) gpiod_set_value_cansleep(imx347->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if (!IS_ERR(imx347->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) gpiod_set_value_cansleep(imx347->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) delay_us = imx347_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) clk_disable_unprepare(imx347->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) static void __imx347_power_off(struct imx347 *imx347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) struct device *dev = &imx347->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (!IS_ERR(imx347->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) gpiod_set_value_cansleep(imx347->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) clk_disable_unprepare(imx347->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (!IS_ERR(imx347->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) gpiod_set_value_cansleep(imx347->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (!IS_ERR_OR_NULL(imx347->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) ret = pinctrl_select_state(imx347->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) imx347->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) regulator_bulk_disable(IMX347_NUM_SUPPLIES, imx347->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static int imx347_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) return __imx347_power_on(imx347);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) static int imx347_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) __imx347_power_off(imx347);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) static int imx347_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) const struct imx347_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) mutex_lock(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) mutex_unlock(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static int imx347_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (fie->index >= imx347->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) #define DST_WIDTH 2688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #define DST_HEIGHT 1520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) * The resolution of the driver configuration needs to be exactly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) * the same as the current output resolution of the sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) * the input width of the isp needs to be 16 aligned,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) * the input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) * Can be cropped to standard resolution by this function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) * otherwise it will crop out strange resolution according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * to the alignment rules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) static int imx347_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) sel->r.left = CROP_START(imx347->cur_mode->width, DST_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) sel->r.width = DST_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) sel->r.top = CROP_START(imx347->cur_mode->height, DST_HEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) sel->r.height = DST_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) static const struct dev_pm_ops imx347_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) SET_RUNTIME_PM_OPS(imx347_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) imx347_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) static const struct v4l2_subdev_internal_ops imx347_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .open = imx347_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static const struct v4l2_subdev_core_ops imx347_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .s_power = imx347_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .ioctl = imx347_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .compat_ioctl32 = imx347_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) static const struct v4l2_subdev_video_ops imx347_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .s_stream = imx347_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .g_frame_interval = imx347_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) static const struct v4l2_subdev_pad_ops imx347_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .enum_mbus_code = imx347_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .enum_frame_size = imx347_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .enum_frame_interval = imx347_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .get_fmt = imx347_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .set_fmt = imx347_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .get_selection = imx347_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .get_mbus_config = imx347_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) static const struct v4l2_subdev_ops imx347_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .core = &imx347_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .video = &imx347_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .pad = &imx347_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) static int imx347_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct imx347 *imx347 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct imx347, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) struct i2c_client *client = imx347->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) const struct imx347_mode *mode = imx347->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) u32 vts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) u32 shr0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) u32 flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) if (mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) max = imx347->cur_mode->height + ctrl->val - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) __v4l2_ctrl_modify_range(imx347->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) imx347->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) imx347->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) imx347->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) shr0 = imx347->cur_vts - ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) ret = imx347_write_reg(imx347->client, IMX347_LF_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) IMX347_FETCH_EXP_L(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ret |= imx347_write_reg(imx347->client, IMX347_LF_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) IMX347_FETCH_EXP_M(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) ret |= imx347_write_reg(imx347->client, IMX347_LF_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) IMX347_FETCH_EXP_H(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) dev_dbg(&client->dev, "set exposure 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) ret = imx347_write_reg(imx347->client, IMX347_LF_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) IMX347_FETCH_GAIN_H(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) ret |= imx347_write_reg(imx347->client, IMX347_LF_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) IMX347_FETCH_GAIN_L(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) dev_dbg(&client->dev, "set analog gain 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) vts = ctrl->val + imx347->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) imx347->cur_vts = vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (imx347->cur_mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) vts /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) ret = imx347_write_reg(imx347->client, IMX347_VTS_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) IMX347_FETCH_VTS_L(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ret |= imx347_write_reg(imx347->client, IMX347_VTS_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) IMX347_FETCH_VTS_M(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) ret |= imx347_write_reg(imx347->client, IMX347_VTS_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) IMX347_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) IMX347_FETCH_VTS_H(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) dev_dbg(&client->dev, "set vblank 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) ret = imx347_write_reg(imx347->client, IMX347_HREVERSE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) IMX347_REG_VALUE_08BIT, !!ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) flip = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) ret = imx347_write_reg(imx347->client, IMX347_VREVERSE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) IMX347_REG_VALUE_08BIT, !!flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if (flip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) ret |= imx347_write_reg(imx347->client, 0x3074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) IMX347_REG_VALUE_08BIT, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) ret |= imx347_write_reg(imx347->client, 0x3075,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) IMX347_REG_VALUE_08BIT, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ret |= imx347_write_reg(imx347->client, 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) IMX347_REG_VALUE_08BIT, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) ret |= imx347_write_reg(imx347->client, 0x30ad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) IMX347_REG_VALUE_08BIT, 0x7e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) ret |= imx347_write_reg(imx347->client, 0x30b6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) IMX347_REG_VALUE_08BIT, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) ret |= imx347_write_reg(imx347->client, 0x30b7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) IMX347_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) ret |= imx347_write_reg(imx347->client, 0x30d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) IMX347_REG_VALUE_08BIT, 0x45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ret |= imx347_write_reg(imx347->client, 0x3114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) IMX347_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) ret |= imx347_write_reg(imx347->client, 0x3074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) IMX347_REG_VALUE_08BIT, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) ret |= imx347_write_reg(imx347->client, 0x3075,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) IMX347_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) ret |= imx347_write_reg(imx347->client, 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) IMX347_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) ret |= imx347_write_reg(imx347->client, 0x30ad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) IMX347_REG_VALUE_08BIT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) ret |= imx347_write_reg(imx347->client, 0x30b6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) IMX347_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) ret |= imx347_write_reg(imx347->client, 0x30b7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) IMX347_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) ret |= imx347_write_reg(imx347->client, 0x30d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) IMX347_REG_VALUE_08BIT, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) ret |= imx347_write_reg(imx347->client, 0x3114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) IMX347_REG_VALUE_08BIT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) static const struct v4l2_ctrl_ops imx347_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .s_ctrl = imx347_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) static int imx347_initialize_controls(struct imx347 *imx347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) const struct imx347_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) handler = &imx347->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) mode = imx347->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) handler->lock = &imx347->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) imx347->link_freq = v4l2_ctrl_new_int_menu(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) 1, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if (imx347->cur_mode->bus_fmt == MEDIA_BUS_FMT_SRGGB10_1X10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) imx347->cur_link_freq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (imx347->cur_mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) imx347->cur_pixel_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) IMX347_10BIT_LINEAR_PIXEL_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) else if (imx347->cur_mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) imx347->cur_pixel_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) IMX347_10BIT_HDR2_PIXEL_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) imx347->cur_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) imx347->cur_pixel_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) IMX347_12BIT_PIXEL_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) __v4l2_ctrl_s_ctrl(imx347->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) imx347->cur_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) imx347->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) V4L2_CID_PIXEL_RATE, 0, IMX347_10BIT_HDR2_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) 1, imx347->cur_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) imx347->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) if (imx347->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) imx347->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) imx347->vblank = v4l2_ctrl_new_std(handler, &imx347_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) IMX347_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) imx347->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) exposure_max = mode->vts_def - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) imx347->exposure = v4l2_ctrl_new_std(handler, &imx347_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) V4L2_CID_EXPOSURE, IMX347_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) exposure_max, IMX347_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) imx347->anal_a_gain = v4l2_ctrl_new_std(handler, &imx347_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) V4L2_CID_ANALOGUE_GAIN, IMX347_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) IMX347_GAIN_MAX, IMX347_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) IMX347_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) v4l2_ctrl_new_std(handler, &imx347_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) v4l2_ctrl_new_std(handler, &imx347_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) dev_err(&imx347->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) imx347->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) imx347->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static int imx347_check_sensor_id(struct imx347 *imx347,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) struct device *dev = &imx347->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) ret = imx347_read_reg(client, IMX347_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) IMX347_REG_VALUE_08BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) dev_info(dev, "Detected imx347 id %06x\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) static int imx347_configure_regulators(struct imx347 *imx347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) for (i = 0; i < IMX347_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) imx347->supplies[i].supply = imx347_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) return devm_regulator_bulk_get(&imx347->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) IMX347_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) imx347->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) static int imx347_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) struct imx347 *imx347;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) imx347 = devm_kzalloc(dev, sizeof(*imx347), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) if (!imx347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) &imx347->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) &imx347->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) &imx347->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) &imx347->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) hdr_mode = NO_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) dev_warn(dev, " Get hdr mode failed! no hdr default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) imx347->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) imx347->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) for (i = 0; i < imx347->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) imx347->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) imx347->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) if (IS_ERR(imx347->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) imx347->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) if (IS_ERR(imx347->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) imx347->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) if (IS_ERR(imx347->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) imx347->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) if (!IS_ERR(imx347->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) imx347->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) pinctrl_lookup_state(imx347->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (IS_ERR(imx347->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) imx347->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) pinctrl_lookup_state(imx347->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) if (IS_ERR(imx347->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) ret = imx347_configure_regulators(imx347);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) mutex_init(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) sd = &imx347->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) v4l2_i2c_subdev_init(sd, client, &imx347_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) ret = imx347_initialize_controls(imx347);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) ret = __imx347_power_on(imx347);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) ret = imx347_check_sensor_id(imx347, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) sd->internal_ops = &imx347_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) imx347->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) ret = media_entity_pads_init(&sd->entity, 1, &imx347->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (strcmp(imx347->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) imx347->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) IMX347_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) g_isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) add_sysfs_interfaces(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) __imx347_power_off(imx347);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) v4l2_ctrl_handler_free(&imx347->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) mutex_destroy(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) static int imx347_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) struct imx347 *imx347 = to_imx347(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) v4l2_ctrl_handler_free(&imx347->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) mutex_destroy(&imx347->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) __imx347_power_off(imx347);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) static const struct of_device_id imx347_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) { .compatible = "sony,imx347" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) MODULE_DEVICE_TABLE(of, imx347_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) static const struct i2c_device_id imx347_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) { "sony,imx347", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) static struct i2c_driver imx347_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .name = IMX347_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .pm = &imx347_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .of_match_table = of_match_ptr(imx347_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .probe = &imx347_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .remove = &imx347_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .id_table = imx347_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) return i2c_add_driver(&imx347_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) i2c_del_driver(&imx347_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) MODULE_DESCRIPTION("Sony imx347 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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