^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * imx335 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 support 10bit DOL3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X02 fix set sensor vertical invert failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X03 add hdr_mode in enum frame interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X04 fix hdr ae error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * V0.0X01.0X05 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * V0.0X01.0X06 Increase hdr exposure restrictions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MIPI_FREQ_594M 594000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX335_4LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX335_XVCLK_FREQ_37M 37125000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* TODO: Get the real chip id from reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CHIP_ID 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX335_REG_CHIP_ID 0x3A01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX335_REG_CTRL_MODE 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX335_MODE_SW_STANDBY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX335_MODE_STREAMING 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX335_LF_GAIN_REG_H 0x30E9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX335_LF_GAIN_REG_L 0x30E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX335_SF1_GAIN_REG_H 0x30EB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX335_SF1_GAIN_REG_L 0x30EA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX335_SF2_GAIN_REG_H 0x30ED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX335_SF2_GAIN_REG_L 0x30EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX335_LF_EXPO_REG_H 0x305A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX335_LF_EXPO_REG_M 0x3059
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX335_LF_EXPO_REG_L 0x3058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX335_SF1_EXPO_REG_H 0x305E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX335_SF1_EXPO_REG_M 0x305D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX335_SF1_EXPO_REG_L 0x305C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX335_RHS1_REG_H 0x306A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX335_RHS1_REG_M 0x3069
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX335_RHS1_REG_L 0x3068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX335_RHS1_DEFAULT 0x0122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX335_RHS1_X3_DEFAULT 0x012E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX335_SF2_EXPO_REG_H 0x3062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX335_SF2_EXPO_REG_M 0x3061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX335_SF2_EXPO_REG_L 0x3060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX335_RHS2_REG_H 0x306E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX335_RHS2_REG_M 0x306D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX335_RHS2_REG_L 0x306C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX335_RHS2_X3_DEFAULT 0x016C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * The linear shr0 shall be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * 9 <= shr0 <= VMAX - 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * 1 <= expo = VMAX - shr0 <= VMAX - 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * == VMAX - SHR0_MIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMX335_EXPOSURE_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX335_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SHR0_MIN 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX335_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX335_GAIN_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX335_GAIN_MAX 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX335_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX335_GAIN_DEFAULT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX335_FETCH_GAIN_H(VAL) (((VAL) >> 8) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX335_FETCH_GAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX335_FETCH_EXP_H(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX335_FETCH_EXP_M(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX335_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX335_FETCH_RHS1_H(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX335_FETCH_RHS1_M(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX335_FETCH_RHS1_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX335_FETCH_VTS_H(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX335_FETCH_VTS_M(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX335_FETCH_VTS_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX335_VTS_REG_L 0x3030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX335_VTS_REG_M 0x3031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX335_VTS_REG_H 0x3032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX335_HREVERSE_REG 0x304E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX335_VREVERSE_REG 0x304F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX335_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX335_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IMX335_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX335_GROUP_HOLD_REG 0x3001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX335_GROUP_HOLD_START 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IMX335_GROUP_HOLD_END 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Basic Readout Lines. Number of necessary readout lines in sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define BRL (1984u * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RHS1_MAX (BRL * 2 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SHR1_MIN 18u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Readout timing setting of SEF1(DOL3): RHS1 < 3 * BRL and should be 12n + 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RHS1_MAX_X3 ((BRL * 3 - 1) / 12 * 12 + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SHR1_MIN_X3 26u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX335_NAME "imx335"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const char * const imx335_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IMX335_NUM_SUPPLIES ARRAY_SIZE(imx335_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct imx335_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct imx335 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct regulator_bulk_data supplies[IMX335_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct v4l2_ctrl *anal_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) const struct imx335_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define to_imx335(sd) container_of(sd, struct imx335, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct regval imx335_linear_10bit_2592x1944_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x300C, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x300D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3034, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3035, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3048, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3049, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x304A, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x304B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x304C, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3058, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3059, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x305C, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3060, 0xE8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3061, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3068, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3069, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x306C, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x306D, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x30E8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x315A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x319D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x31D7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3200, 0x01}, /* Each frame gain adjustment disabed in linear mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3288, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3414, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3416, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x341C, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x341D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x364A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x364C, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x367C, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x367E, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3706, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3708, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3714, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3715, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3716, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3717, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x371C, 0x3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x371D, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x372C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x372D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x372E, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x372F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3730, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3731, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3732, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3733, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3734, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x3735, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3740, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x375D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x375E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x375F, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3760, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x376A, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x376B, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x376C, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x376D, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x376E, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x3776, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3778, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x377A, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x377B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x377C, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x377D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x377E, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x377F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3780, 0xD9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3781, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3782, 0xF5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x3784, 0xA5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x3788, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x378A, 0xD9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x378B, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x378C, 0xEB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x378D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x378E, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x378F, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3790, 0xF5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3792, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3794, 0x7A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3796, 0xA1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct regval imx335_hdr2_10bit_2592x1944_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x300C, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x300D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x3034, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x3035, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x3048, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x3049, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x304A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x304B, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x304C, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x3050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3058, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x3059, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x305C, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3060, 0xE8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3061, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x3068, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x3069, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x306C, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x306D, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x30E8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x315A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x319D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x31D7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3200, 0x00}, /* Each frame gain adjustment EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x3288, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3414, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3416, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x341C, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x341D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x364A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x364C, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x367C, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x367E, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x3706, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x3708, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x3714, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x3715, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x3716, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3717, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x371C, 0x3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x371D, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x372C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x372D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x372E, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x372F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3730, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x3731, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x3732, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x3733, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x3734, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x3735, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3740, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x375D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x375E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x375F, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x3760, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x376A, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x376B, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x376C, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x376D, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x376E, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3776, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3778, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x377A, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x377B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x377C, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x377D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x377E, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x377F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x3780, 0xD9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x3781, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x3782, 0xF5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x3784, 0xA5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x3788, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x378A, 0xD9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x378B, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x378C, 0xEB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x378D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x378E, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x378F, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x3790, 0xF5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x3792, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x3794, 0x7A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x3796, 0xA1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static const struct regval imx335_hdr3_10bit_2592x1944_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x300C, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x300D, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x3034, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3035, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x3048, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x3049, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x304A, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x304B, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x304C, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3050, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3058, 0xC4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x3059, 0x3B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x305C, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x3060, 0x4E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x3061, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x3068, 0x2E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x3069, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x306C, 0x6C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x306D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x30E8, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x315A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x316A, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x319D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x31A1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x31D7, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x3200, 0x00}, /* Each frame gain adjustment EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x3288, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x328A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x3414, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x3416, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x341C, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x341D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x3648, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x364A, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x364C, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x3678, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x367C, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x367E, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x3706, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x3708, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x3714, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x3715, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x3716, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x3717, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x371C, 0x3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x371D, 0x3F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x372C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x372D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x372E, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x372F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x3730, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x3731, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x3732, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x3733, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x3734, 0xFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x3735, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x3740, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x375D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x375E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x375F, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x3760, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x3768, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x3769, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x376A, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x376B, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x376C, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x376D, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x376E, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x3776, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x3777, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x3778, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x3779, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x377A, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x377B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x377C, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x377D, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x377E, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x377F, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x3780, 0xD9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x3781, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x3782, 0xF5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x3783, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x3784, 0xA5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x3788, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x378A, 0xD9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x378B, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x378C, 0xEB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x378D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x378E, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x378F, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x3790, 0xF5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x3792, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x3794, 0x7A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x3796, 0xA1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * The width and height must be configured to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * the same as the current output resolution of the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * The input width of the isp needs to be 16 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * The input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * If the width or height does not meet the alignment rules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * you can configure the cropping parameters with the following function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * crop out the appropriate resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * struct v4l2_subdev_pad_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * .get_selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const struct imx335_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* 1H period = 7.4us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .width = 2616,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .height = 1964,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .exp_def = 0x1194 - 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .hts_def = 0x0226 * IMX335_4LANES * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .vts_def = 0x1194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .reg_list = imx335_linear_10bit_2592x1944_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* 1H period = 3.70us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .width = 2616,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .height = 1964,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .exp_def = 0x1194 * 2 - 0x1248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .hts_def = 0x0113 * IMX335_4LANES * 2 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * IMX335 HDR mode T-line is a half of Linear mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * make vts double(that is FSC) to workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .vts_def = 0x1194 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .reg_list = imx335_hdr2_10bit_2592x1944_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* 1H period = 3.70us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .width = 2616,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .height = 1964,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .denominator = 150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .exp_def = 0x1194 * 2 - 0x1248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .hts_def = 0x0113 * IMX335_4LANES * 2 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * IMX335 HDR mode T-line is a half of Linear mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * make vts double(that is FSC) to workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .vts_def = 0x1194 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .reg_list = imx335_hdr3_10bit_2592x1944_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .hdr_mode = HDR_X3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const s64 link_freq_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MIPI_FREQ_594M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int imx335_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int imx335_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = imx335_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) IMX335_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static int imx335_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int imx335_get_reso_dist(const struct imx335_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const struct imx335_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) imx335_find_best_fit(struct imx335 *imx335, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) for (i = 0; i < imx335->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dist = imx335_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) supported_modes[i].bus_fmt == framefmt->code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static void imx335_change_mode(struct imx335 *imx335, const struct imx335_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) imx335->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) imx335->cur_vts = imx335->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dev_dbg(&imx335->client->dev, "set fmt: cur_mode: %dx%d, hdr: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mode->width, mode->height, mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int imx335_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct imx335 *imx335 = to_imx335(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) const struct imx335_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) mutex_lock(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) mode = imx335_find_best_fit(imx335, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) imx335_change_mode(imx335, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) __v4l2_ctrl_modify_range(imx335->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) __v4l2_ctrl_modify_range(imx335->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) IMX335_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) mutex_unlock(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static int imx335_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct imx335 *imx335 = to_imx335(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) const struct imx335_mode *mode = imx335->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) mutex_lock(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) mutex_unlock(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static int imx335_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct imx335 *imx335 = to_imx335(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) code->code = imx335->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int imx335_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct imx335 *imx335 = to_imx335(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (fse->index >= imx335->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int imx335_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct imx335 *imx335 = to_imx335(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) const struct imx335_mode *mode = imx335->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mutex_lock(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mutex_unlock(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static int imx335_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct imx335 *imx335 = to_imx335(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) const struct imx335_mode *mode = imx335->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) val = 1 << (IMX335_4LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static void imx335_get_module_inf(struct imx335 *imx335,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) strlcpy(inf->base.sensor, IMX335_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) strlcpy(inf->base.module, imx335->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) strlcpy(inf->base.lens, imx335->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static int imx335_set_hdrae(struct imx335 *imx335,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct i2c_client *client = imx335->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u32 l_a_gain, m_a_gain, s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) int shr1, shr0, rhs1, rhs1_max, rhs1_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int rhs1_old = IMX335_RHS1_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u32 fsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (!imx335->has_init_exp && !imx335->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) imx335->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) imx335->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) dev_dbg(&imx335->client->dev, "imx335 is not streaming, save hdr ae!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) l_a_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) m_a_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) s_a_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) l_exp_time, l_a_gain, m_exp_time, m_a_gain, s_exp_time, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (imx335->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) l_a_gain = m_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ret = imx335_write_reg(client, IMX335_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) IMX335_REG_VALUE_08BIT, IMX335_GROUP_HOLD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* gain effect n+1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ret |= imx335_write_reg(client, IMX335_LF_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_H(l_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ret |= imx335_write_reg(client, IMX335_LF_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_L(l_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ret |= imx335_write_reg(client, IMX335_SF1_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_H(s_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ret |= imx335_write_reg(client, IMX335_SF1_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_L(s_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* Restrictions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) * FSC = 2 * VMAX = 4n (4n, align with 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * SHR1 + 18 <= SHR0 <= (FSC - 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * exp_l = FSC - SHR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * SHR0 = FSC - exp_l (4n, align with 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * exp_s = RHS1 - SHR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * SHR1 + 4 <= RHS1 < BRL * 2 (8n + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * SHR1 + 4 <= RHS1 <= SHR0 - 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * 18 <= SHR1 <= RHS1 - 4 (4n + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * RHS1(n+1) >= (RHS1(n) + BRL * 2) - FSC + 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * RHS1 and SHR1 shall be even value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * T(l_exp) = FSC - SHR0, unit: H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * T(s_exp) = RHS1 - SHR1, unit: H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * Exposure ratio: T(l_exp) / T(s_exp) >= 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* The HDR mode vts is already double by default to workaround T-line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) fsc = imx335->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) shr0 = fsc - l_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) rhs1_max = min(RHS1_MAX, shr0 - SHR1_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) rhs1_max = (rhs1_max & ~0x7) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) rhs1_min = max(SHR1_MIN + 4u, rhs1_old + 2 * BRL - fsc + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) rhs1_min = (rhs1_min + 7u) / 8 * 8 + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (rhs1_max < rhs1_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) "The total exposure limit makes rhs1 max is %d,but old rhs1 limit makes rhs1 min is %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) rhs1_max, rhs1_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) rhs1 = SHR1_MIN + s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) rhs1 = (rhs1 & ~0x7) + 2; /* shall be 8n + 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (rhs1 > rhs1_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) rhs1 = rhs1_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (rhs1 < rhs1_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) rhs1 = rhs1_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) "line(%d) rhs1 %d, short time %d rhs1_old %d, rhs1_new %d, rhs1_min %d rhs1_max %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) __LINE__, rhs1, s_exp_time, rhs1_old, rhs1, rhs1_min, rhs1_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) rhs1_old = rhs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* shr1 = rhs1 - s_exp_time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (rhs1 - s_exp_time <= SHR1_MIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) shr1 = SHR1_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) s_exp_time = rhs1 - shr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) shr1 = rhs1 - s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) shr1 = (shr1 & ~0x3) + 2; /* shall be 4n + 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (shr0 < rhs1 + 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) shr0 = rhs1 + 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) else if (shr0 > fsc - 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) shr0 = fsc - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) shr0 &= (~0x3); /* align with 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) "fsc=%d,RHS1_MAX=%d,SHR1_MIN=%d,rhs1_max=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) fsc, RHS1_MAX, SHR1_MIN, rhs1_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) "l_exp_time=%d,s_exp_time=%d,shr0=%d,shr1=%d,rhs1=%d,l_a_gain=%d,s_a_gain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) l_exp_time, s_exp_time, shr0, shr1, rhs1, l_a_gain, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* time effect n+2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) IMX335_RHS1_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) IMX335_FETCH_RHS1_L(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) IMX335_RHS1_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) IMX335_FETCH_RHS1_M(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) IMX335_RHS1_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) IMX335_FETCH_RHS1_H(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) IMX335_SF1_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) IMX335_FETCH_EXP_L(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) IMX335_SF1_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) IMX335_FETCH_EXP_M(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) IMX335_SF1_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) IMX335_FETCH_EXP_H(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) IMX335_LF_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) IMX335_FETCH_EXP_L(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) IMX335_LF_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) IMX335_FETCH_EXP_M(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) IMX335_LF_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) IMX335_FETCH_EXP_H(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ret |= imx335_write_reg(client, IMX335_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) IMX335_REG_VALUE_08BIT, IMX335_GROUP_HOLD_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static int imx335_set_hdrae_3frame(struct imx335 *imx335,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct i2c_client *client = imx335->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) u32 l_a_gain, m_a_gain, s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) int shr2, shr1, shr0, rhs2, rhs1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) int rhs1_change_limit, rhs2_change_limit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static int rhs1_old = IMX335_RHS1_X3_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static int rhs2_old = IMX335_RHS2_X3_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) u32 fsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) int rhs1_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) int shr2_min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (!imx335->has_init_exp && !imx335->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) imx335->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) imx335->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dev_dbg(&imx335->client->dev, "imx335 is not streaming, save hdr ae!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) l_a_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) m_a_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) s_a_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) l_exp_time, l_a_gain, m_exp_time, m_a_gain, s_exp_time, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret = imx335_write_reg(client, IMX335_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) IMX335_REG_VALUE_08BIT, IMX335_GROUP_HOLD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* gain effect n+1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ret |= imx335_write_reg(client, IMX335_LF_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_H(l_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ret |= imx335_write_reg(client, IMX335_LF_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_L(l_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ret |= imx335_write_reg(client, IMX335_SF1_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_H(m_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ret |= imx335_write_reg(client, IMX335_SF1_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_L(m_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ret |= imx335_write_reg(client, IMX335_SF2_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_H(s_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret |= imx335_write_reg(client, IMX335_SF2_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) IMX335_REG_VALUE_08BIT, IMX335_FETCH_GAIN_L(s_a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* Restrictions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * FSC = 4 * VMAX and FSC should be 6n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * exp_l = FSC - SHR0 + Toffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * SHR0 = FSC - exp_l + Toffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * SHR0 <= (FSC -6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * SHR0 >= RHS2 + 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * SHR0 should be 6n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * exp_m = RHS1 - SHR1 + Toffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * RHS1 < BRL * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * RHS1 <= SHR2 - 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * RHS1 >= SHR1 + 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * SHR1 >= 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * SHR1 <= RHS1 - 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * RHS1(n+1) >= RHS1(n) + BRL * 3 -FSC + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * SHR1 should be 6n+2 and RHS1 should be 12n+2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * exp_s = RHS2 - SHR2 + Toffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * RHS2 < BRL * 3 + RHS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * RHS2 <= SHR0 - 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * RHS2 >= SHR2 + 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * SHR2 >= RHS1 + 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * SHR2 <= RHS2 - 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * RHS1(n+1) >= RHS1(n) + BRL * 3 -FSC + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * SHR2 should be 6n+4 and RHS2 should be 12n+4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* The HDR mode vts is double by default to workaround T-line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) fsc = imx335->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) fsc = fsc / 6 * 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) shr0 = fsc - l_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) "line(%d) shr0 %d, l_exp_time %d, fsc %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) __LINE__, shr0, l_exp_time, fsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) rhs1 = (SHR1_MIN_X3 + m_exp_time + 11) / 12 * 12 + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) rhs1_max = RHS1_MAX_X3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (rhs1 < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) rhs1 = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) else if (rhs1 > rhs1_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) rhs1 = rhs1_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) "line(%d) rhs1 %d, m_exp_time %d rhs1_old %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) __LINE__, rhs1, m_exp_time, rhs1_old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) //Dynamic adjustment rhs2 must meet the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) rhs1_change_limit = rhs1_old + 3 * BRL - fsc + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) rhs1_change_limit = (rhs1_change_limit < 32) ? 32 : rhs1_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) rhs1_change_limit = (rhs1_change_limit + 11) / 12 * 12 + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (rhs1_max < rhs1_change_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) "The total exposure limit makes rhs1 max is %d,but old rhs1 limit makes rhs1 min is %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) rhs1_max, rhs1_change_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (rhs1 < rhs1_change_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) rhs1 = rhs1_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) "line(%d) m_exp_time %d rhs1_old %d, rhs1_new %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) __LINE__, m_exp_time, rhs1_old, rhs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) rhs1_old = rhs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* shr1 = rhs1 - s_exp_time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (rhs1 - m_exp_time <= SHR1_MIN_X3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) shr1 = SHR1_MIN_X3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) m_exp_time = rhs1 - shr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) shr1 = rhs1 - m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) shr2_min = rhs1 + 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) rhs2 = (shr2_min + s_exp_time + 11) / 12 * 12 + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (rhs2 > (shr0 - 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) rhs2 = shr0 - 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) else if (rhs2 < 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) rhs2 = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) "line(%d) rhs2 %d, s_exp_time %d, rhs2_old %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) __LINE__, rhs2, s_exp_time, rhs2_old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) //Dynamic adjustment rhs2 must meet the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) rhs2_change_limit = rhs2_old + 3 * BRL - fsc + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) rhs2_change_limit = (rhs2_change_limit < 64) ? 64 : rhs2_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) rhs2_change_limit = (rhs2_change_limit + 11) / 12 * 12 + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if ((shr0 - 26) < rhs2_change_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) "The total exposure limit makes rhs2 max is %d,but old rhs1 limit makes rhs2 min is %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) shr0 - 26, rhs2_change_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (rhs2 < rhs2_change_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) rhs2 = rhs2_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) rhs2_old = rhs2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* shr2 = rhs2 - s_exp_time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (rhs2 - s_exp_time <= shr2_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) shr2 = shr2_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) s_exp_time = rhs2 - shr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) shr2 = rhs2 - s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) "line(%d) rhs2_new %d, s_exp_time %d shr2 %d, rhs2_change_limit %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) __LINE__, rhs2, s_exp_time, shr2, rhs2_change_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (shr0 < rhs2 + 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) shr0 = rhs2 + 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) else if (shr0 > fsc - 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) shr0 = fsc - 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) "long exposure: l_exp_time=%d, fsc=%d, shr0=%d, l_a_gain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) l_exp_time, fsc, shr0, l_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) "middle exposure(SEF1): m_exp_time=%d, rhs1=%d, shr1=%d, m_a_gain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) m_exp_time, rhs1, shr1, m_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) "short exposure(SEF2): s_exp_time=%d, rhs2=%d, shr2=%d, s_a_gain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) s_exp_time, rhs2, shr2, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* time effect n+1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* write SEF2 exposure RHS2 regs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) IMX335_RHS2_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) IMX335_FETCH_RHS1_L(rhs2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) IMX335_RHS2_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) IMX335_FETCH_RHS1_M(rhs2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) IMX335_RHS2_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) IMX335_FETCH_RHS1_H(rhs2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /* write SEF2 exposure SHR2 regs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) IMX335_SF2_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) IMX335_FETCH_EXP_L(shr2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) IMX335_SF2_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) IMX335_FETCH_EXP_M(shr2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) IMX335_SF2_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) IMX335_FETCH_EXP_H(shr2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /* write SEF1 exposure RHS1 regs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) IMX335_RHS1_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) IMX335_FETCH_RHS1_L(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) IMX335_RHS1_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) IMX335_FETCH_RHS1_M(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) IMX335_RHS1_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) IMX335_FETCH_RHS1_H(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* write SEF1 exposure SHR1 regs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) IMX335_SF1_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) IMX335_FETCH_EXP_L(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) IMX335_SF1_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) IMX335_FETCH_EXP_M(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) IMX335_SF1_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) IMX335_FETCH_EXP_H(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* write LF exposure SHR0 regs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) IMX335_LF_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) IMX335_FETCH_EXP_L(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) IMX335_LF_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) IMX335_FETCH_EXP_M(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ret |= imx335_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) IMX335_LF_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) IMX335_FETCH_EXP_H(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ret |= imx335_write_reg(client, IMX335_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) IMX335_REG_VALUE_08BIT, IMX335_GROUP_HOLD_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static long imx335_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) struct imx335 *imx335 = to_imx335(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (imx335->cur_mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ret = imx335_set_hdrae(imx335, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) else if (imx335->cur_mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ret = imx335_set_hdrae_3frame(imx335, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) imx335_get_module_inf(imx335, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) hdr->hdr_mode = imx335->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) w = imx335->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) h = imx335->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) for (i = 0; i < imx335->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) imx335_change_mode(imx335, &supported_modes[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (i == imx335->cfg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) dev_err(&imx335->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) w = imx335->cur_mode->hts_def - imx335->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) h = imx335->cur_mode->vts_def - imx335->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) __v4l2_ctrl_modify_range(imx335->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) __v4l2_ctrl_modify_range(imx335->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) IMX335_VTS_MAX - imx335->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) imx335_write_reg(imx335->client, IMX335_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) IMX335_REG_VALUE_08BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) imx335_write_reg(imx335->client, IMX335_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) IMX335_REG_VALUE_08BIT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) static long imx335_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ret = imx335_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) ret = imx335_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ret = imx335_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ret = imx335_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ret = imx335_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ret = imx335_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static int __imx335_start_stream(struct imx335 *imx335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) ret = imx335_write_array(imx335->client, imx335->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) ret = __v4l2_ctrl_handler_setup(&imx335->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (imx335->has_init_exp && imx335->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ret = imx335_ioctl(&imx335->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) &imx335->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) dev_err(&imx335->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) return imx335_write_reg(imx335->client, IMX335_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) IMX335_REG_VALUE_08BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static int __imx335_stop_stream(struct imx335 *imx335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) imx335->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) return imx335_write_reg(imx335->client, IMX335_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) IMX335_REG_VALUE_08BIT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static int imx335_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) struct imx335 *imx335 = to_imx335(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) struct i2c_client *client = imx335->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) dev_dbg(&imx335->client->dev, "s_stream: %d. %dx%d, hdr: %d, bpp: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) on, imx335->cur_mode->width, imx335->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) imx335->cur_mode->hdr_mode, imx335->cur_mode->bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) mutex_lock(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (on == imx335->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) ret = __imx335_start_stream(imx335);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) __imx335_stop_stream(imx335);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) imx335->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) mutex_unlock(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static int imx335_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) struct imx335 *imx335 = to_imx335(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) struct i2c_client *client = imx335->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) mutex_lock(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (imx335->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) imx335->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) imx335->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) mutex_unlock(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static int __imx335_power_on(struct imx335 *imx335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) struct device *dev = &imx335->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (!IS_ERR_OR_NULL(imx335->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) ret = pinctrl_select_state(imx335->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) imx335->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) ret = regulator_bulk_enable(IMX335_NUM_SUPPLIES, imx335->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) goto err_pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (!IS_ERR(imx335->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) gpiod_set_value_cansleep(imx335->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /* At least 500ns between power raising and Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (!IS_ERR(imx335->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) gpiod_set_value_cansleep(imx335->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ret = clk_set_rate(imx335->xvclk, IMX335_XVCLK_FREQ_37M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) dev_warn(dev, "Failed to set xvclk rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (clk_get_rate(imx335->xvclk) != IMX335_XVCLK_FREQ_37M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) dev_warn(dev, "xvclk mismatched\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) ret = clk_prepare_enable(imx335->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* At least 20us between Reset and I2C communication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) usleep_range(20, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (!IS_ERR(imx335->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) gpiod_set_value_cansleep(imx335->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) regulator_bulk_disable(IMX335_NUM_SUPPLIES, imx335->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) err_pinctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (!IS_ERR_OR_NULL(imx335->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) pinctrl_select_state(imx335->pinctrl, imx335->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static void __imx335_power_off(struct imx335 *imx335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) struct device *dev = &imx335->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (!IS_ERR(imx335->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) gpiod_set_value_cansleep(imx335->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) clk_disable_unprepare(imx335->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) if (!IS_ERR_OR_NULL(imx335->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) ret = pinctrl_select_state(imx335->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) imx335->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) regulator_bulk_disable(IMX335_NUM_SUPPLIES, imx335->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) static int imx335_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) struct imx335 *imx335 = to_imx335(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return __imx335_power_on(imx335);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static int imx335_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct imx335 *imx335 = to_imx335(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) __imx335_power_off(imx335);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static int imx335_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) struct imx335 *imx335 = to_imx335(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) const struct imx335_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) mutex_lock(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) mutex_unlock(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static int imx335_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) struct imx335 *imx335 = to_imx335(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) if (fie->index >= imx335->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) #define DST_WIDTH 2592
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) #define DST_HEIGHT 1944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) * The resolution of the driver configuration needs to be exactly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) * the same as the current output resolution of the sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) * the input width of the isp needs to be 16 aligned,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) * the input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * Can be cropped to standard resolution by this function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * otherwise it will crop out strange resolution according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) * to the alignment rules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static int imx335_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) * From "Pixel Array Image Drawing in All scan mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) * there are 12 pixel offset on horizontal and vertical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) sel->r.left = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) sel->r.width = DST_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) sel->r.top = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) sel->r.height = DST_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) static const struct dev_pm_ops imx335_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) SET_RUNTIME_PM_OPS(imx335_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) imx335_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static const struct v4l2_subdev_internal_ops imx335_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .open = imx335_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static const struct v4l2_subdev_core_ops imx335_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .s_power = imx335_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .ioctl = imx335_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .compat_ioctl32 = imx335_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static const struct v4l2_subdev_video_ops imx335_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .s_stream = imx335_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .g_frame_interval = imx335_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static const struct v4l2_subdev_pad_ops imx335_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .enum_mbus_code = imx335_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .enum_frame_size = imx335_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .enum_frame_interval = imx335_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .get_fmt = imx335_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .set_fmt = imx335_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .get_selection = imx335_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .get_mbus_config = imx335_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) static const struct v4l2_subdev_ops imx335_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .core = &imx335_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .video = &imx335_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .pad = &imx335_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static int imx335_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) struct imx335 *imx335 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) struct imx335, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) struct i2c_client *client = imx335->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) u32 vts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) u32 shr0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (imx335->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) max = imx335->cur_mode->height + ctrl->val - SHR0_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) __v4l2_ctrl_modify_range(imx335->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) imx335->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) imx335->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) imx335->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (imx335->cur_mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) shr0 = imx335->cur_vts - ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) ret = imx335_write_reg(imx335->client, IMX335_LF_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) IMX335_FETCH_EXP_L(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) ret |= imx335_write_reg(imx335->client, IMX335_LF_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) IMX335_FETCH_EXP_M(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) ret |= imx335_write_reg(imx335->client, IMX335_LF_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) IMX335_FETCH_EXP_H(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) dev_dbg(&client->dev, "set exposure(shr0) %d = cur_vts(%d) - val(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) shr0, imx335->cur_vts, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (imx335->cur_mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) ret = imx335_write_reg(imx335->client, IMX335_LF_GAIN_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) IMX335_FETCH_GAIN_H(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) ret |= imx335_write_reg(imx335->client, IMX335_LF_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) IMX335_FETCH_GAIN_L(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) dev_dbg(&client->dev, "set analog gain 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) vts = ctrl->val + imx335->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) * vts of hdr mode is double to correct T-line calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * Restore before write to reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (imx335->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) vts = (vts + 3) / 4 * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) imx335->cur_vts = vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) vts /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) } else if (imx335->cur_mode->hdr_mode == HDR_X3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) vts = (vts + 11) / 12 * 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) imx335->cur_vts = vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) vts /= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) imx335->cur_vts = vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) ret = imx335_write_reg(imx335->client, IMX335_VTS_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) IMX335_FETCH_VTS_L(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) ret |= imx335_write_reg(imx335->client, IMX335_VTS_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) IMX335_FETCH_VTS_M(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) ret |= imx335_write_reg(imx335->client, IMX335_VTS_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) IMX335_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) IMX335_FETCH_VTS_H(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) ret = imx335_write_reg(imx335->client, IMX335_HREVERSE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) IMX335_REG_VALUE_08BIT, !!ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) if (ctrl->val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) ret = imx335_write_reg(imx335->client, IMX335_VREVERSE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) IMX335_REG_VALUE_08BIT, !!ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) ret |= imx335_write_reg(imx335->client, 0x3081,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) IMX335_REG_VALUE_08BIT, 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) ret |= imx335_write_reg(imx335->client, 0x3083,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) IMX335_REG_VALUE_08BIT, 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ret |= imx335_write_reg(imx335->client, 0x30b6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) IMX335_REG_VALUE_08BIT, 0xfa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) ret |= imx335_write_reg(imx335->client, 0x30b7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) IMX335_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) ret |= imx335_write_reg(imx335->client, 0x3116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) IMX335_REG_VALUE_08BIT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) ret |= imx335_write_reg(imx335->client, 0x3117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) IMX335_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) ret = imx335_write_reg(imx335->client, IMX335_VREVERSE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) IMX335_REG_VALUE_08BIT, !!ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ret |= imx335_write_reg(imx335->client, 0x3081,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) IMX335_REG_VALUE_08BIT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) ret |= imx335_write_reg(imx335->client, 0x3083,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) IMX335_REG_VALUE_08BIT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) ret |= imx335_write_reg(imx335->client, 0x30b6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) IMX335_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) ret |= imx335_write_reg(imx335->client, 0x30b7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) IMX335_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) ret |= imx335_write_reg(imx335->client, 0x3116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) IMX335_REG_VALUE_08BIT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) ret |= imx335_write_reg(imx335->client, 0x3117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) IMX335_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) static const struct v4l2_ctrl_ops imx335_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .s_ctrl = imx335_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) static int imx335_initialize_controls(struct imx335 *imx335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) const struct imx335_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) u64 pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) handler = &imx335->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) mode = imx335->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) handler->lock = &imx335->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) imx335->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ARRAY_SIZE(link_freq_items) - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) link_freq_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) pixel_rate = (u32)link_freq_items[0] / mode->bpp * 2 * IMX335_4LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) imx335->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) V4L2_CID_PIXEL_RATE, 0, pixel_rate, 1, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) imx335->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (imx335->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) imx335->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) imx335->vblank = v4l2_ctrl_new_std(handler, &imx335_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) IMX335_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) imx335->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) exposure_max = mode->vts_def - SHR0_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) imx335->exposure = v4l2_ctrl_new_std(handler, &imx335_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) V4L2_CID_EXPOSURE, IMX335_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) exposure_max, IMX335_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) imx335->anal_a_gain = v4l2_ctrl_new_std(handler, &imx335_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) V4L2_CID_ANALOGUE_GAIN, IMX335_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) IMX335_GAIN_MAX, IMX335_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) IMX335_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) v4l2_ctrl_new_std(handler, &imx335_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) v4l2_ctrl_new_std(handler, &imx335_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) dev_err(&imx335->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) imx335->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) imx335->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) static int imx335_check_sensor_id(struct imx335 *imx335,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) struct device *dev = &imx335->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) ret = imx335_read_reg(client, IMX335_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) IMX335_REG_VALUE_08BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) dev_info(dev, "Detected imx335 id %06x\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static int imx335_configure_regulators(struct imx335 *imx335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) for (i = 0; i < IMX335_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) imx335->supplies[i].supply = imx335_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return devm_regulator_bulk_get(&imx335->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) IMX335_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) imx335->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) static int imx335_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) struct imx335 *imx335;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) imx335 = devm_kzalloc(dev, sizeof(*imx335), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) if (!imx335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) &imx335->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) &imx335->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) &imx335->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) &imx335->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) hdr_mode = NO_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) dev_warn(dev, " Get hdr mode failed! no hdr default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) imx335->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) imx335->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) for (i = 0; i < imx335->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) imx335->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) imx335->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) if (IS_ERR(imx335->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) imx335->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) if (IS_ERR(imx335->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) imx335->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if (!IS_ERR(imx335->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) imx335->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) pinctrl_lookup_state(imx335->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) if (IS_ERR(imx335->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) dev_info(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) imx335->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) pinctrl_lookup_state(imx335->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) if (IS_ERR(imx335->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) dev_info(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) dev_info(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) ret = imx335_configure_regulators(imx335);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) mutex_init(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) sd = &imx335->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) v4l2_i2c_subdev_init(sd, client, &imx335_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) ret = imx335_initialize_controls(imx335);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) ret = __imx335_power_on(imx335);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) ret = imx335_check_sensor_id(imx335, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) sd->internal_ops = &imx335_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) imx335->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) ret = media_entity_pads_init(&sd->entity, 1, &imx335->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) if (strcmp(imx335->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) imx335->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) IMX335_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) __imx335_power_off(imx335);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) v4l2_ctrl_handler_free(&imx335->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) mutex_destroy(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) static int imx335_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) struct imx335 *imx335 = to_imx335(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) v4l2_ctrl_handler_free(&imx335->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) mutex_destroy(&imx335->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) __imx335_power_off(imx335);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) static const struct of_device_id imx335_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) { .compatible = "sony,imx335" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) MODULE_DEVICE_TABLE(of, imx335_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) static const struct i2c_device_id imx335_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) { "sony,imx335", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) static struct i2c_driver imx335_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .name = IMX335_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .pm = &imx335_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .of_match_table = of_match_ptr(imx335_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .probe = &imx335_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .remove = &imx335_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .id_table = imx335_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) return i2c_add_driver(&imx335_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) i2c_del_driver(&imx335_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) MODULE_DESCRIPTION("Sony imx335 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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