^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * imx334 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * 1.add parse mclk pinctrl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 2.add set flip ctrl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X05 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX334_LINK_FREQ_445 445500000// 891Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX334_LINK_FREQ_594 594000000// 1188Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX334_LINK_FREQ_891 891000000// 1782Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX334_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PIXEL_RATE_WITH_445M_10BIT (IMX334_LINK_FREQ_445 * 2 / 10 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PIXEL_RATE_WITH_594M_12BIT (IMX334_LINK_FREQ_594 * 2 / 12 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PIXEL_RATE_WITH_891M_10BIT (IMX334_LINK_FREQ_891 * 2 / 10 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PIXEL_RATE_WITH_891M_12BIT (IMX334_LINK_FREQ_891 * 2 / 12 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX334_XVCLK_FREQ_37 37125000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX334_XVCLK_FREQ_74 74250000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CHIP_ID 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX334_REG_CHIP_ID 0x302c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX334_REG_CTRL_MODE 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX334_MODE_SW_STANDBY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX334_MODE_STREAMING 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX334_LF_GAIN_REG_L 0x30E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX334_SF1_GAIN_REG_L 0x30EA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX334_LF_EXPO_REG_H 0x305A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX334_LF_EXPO_REG_M 0x3059
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX334_LF_EXPO_REG_L 0x3058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX334_SF1_EXPO_REG_H 0x305E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX334_SF1_EXPO_REG_M 0x305D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX334_SF1_EXPO_REG_L 0x305C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX334_RHS1_REG_H 0x306a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX334_RHS1_REG_M 0x3069
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX334_RHS1_REG_L 0x3068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX334_EXPOSURE_MIN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX334_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX334_VTS_MAX 0xfffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX334_REG_GAIN 0x30e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX334_GAIN_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX334_GAIN_MAX 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX334_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX334_GAIN_DEFAULT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX334_REG_TEST_PATTERN 0x5e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX334_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IMX334_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX334_REG_VTS_H 0x3032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMX334_REG_VTS_M 0x3031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX334_REG_VTS_L 0x3030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX334_FETCH_EXP_H(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX334_FETCH_EXP_M(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX334_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX334_FETCH_RHS1_H(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX334_FETCH_RHS1_M(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX334_FETCH_RHS1_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX334_FETCH_VTS_H(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX334_FETCH_VTS_M(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX334_FETCH_VTS_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX334_VREVERSE_REG 0x304f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX334_HREVERSE_REG 0x304e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX334_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX334_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX334_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX334_NAME "imx334"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BRL 2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RHS1_MAX 4397 // <2*BRL && 4n+1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SHR1_MIN 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const char * const imx334_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX334_NUM_SUPPLIES ARRAY_SIZE(imx334_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct imx334_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const struct regval *global_reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 vclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct imx334 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct regulator_bulk_data supplies[IMX334_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const struct imx334_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 cur_vclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 cur_mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define to_imx334(sd) container_of(sd, struct imx334, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct regval imx334_10_3840x2160_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x300C, 0x5B},// BCWAIT_TIME[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x300D, 0x40},// CPWAIT_TIME[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3050, 0x00},// ADBIT[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x316A, 0x7E},// INCKSEL4[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x319D, 0x00},// MDBIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x31A1, 0x00},// XVS_DRV[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3288, 0x21},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x328A, 0x02},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3414, 0x05},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3416, 0x18},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x341D, 0x01},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x35AC, 0x0E},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3648, 0x01},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x364A, 0x04},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x364C, 0x04},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3678, 0x01},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x367C, 0x31},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x367E, 0x31},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3708, 0x02},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3714, 0x01},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3715, 0x02},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3716, 0x02},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3717, 0x02},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x371C, 0x3D},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x371D, 0x3F},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x372C, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x372D, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x372E, 0x46},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x372F, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3730, 0x89},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3731, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3732, 0x08},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3733, 0x01},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3734, 0xFE},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3735, 0x05},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x375D, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x375E, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x375F, 0x61},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3760, 0x06},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3768, 0x1B},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3769, 0x1B},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x376A, 0x1A},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x376B, 0x19},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x376C, 0x18},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x376D, 0x14},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x376E, 0x0F},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3776, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3777, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3778, 0x46},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3779, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x377A, 0x08},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x377B, 0x01},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x377C, 0x45},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x377D, 0x01},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x377E, 0x23},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x377F, 0x02},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3780, 0xD9},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3781, 0x03},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3782, 0xF5},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3783, 0x06},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3784, 0xA5},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x3788, 0x0F},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x378A, 0xD9},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x378B, 0x03},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x378C, 0xEB},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x378D, 0x05},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x378E, 0x87},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x378F, 0x06},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3790, 0xF5},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3792, 0x43},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3794, 0x7A},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3796, 0xA1},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x3E04, 0x0E},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) *IMX334LQR All-pixel scan CSI-2_4lane 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *AD:10bit Output:10bit 891Mbps Master Mode 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *Tool ver : Ver4.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct regval imx334_linear_10_3840x2160_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x302E, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x302F, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3030, 0xCA},// VMAX[19:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x3031, 0x08},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x3034, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3035, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x3048, 0x00},// WDMODE[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x3049, 0x00},// WDSEL[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x304A, 0x00},// WD_SET1[2:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x304B, 0x01},// WD_SET2[3:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x304C, 0x14},// OPB_SIZE_V[5:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3058, 0x05},// SHR0[19:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3059, 0x00},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3068, 0x8B},// RHS1[19:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3069, 0x00},//{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3076, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x3077, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x315a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x319e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x31D7, 0x00},// XVSMSKCNT_INT[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x3200, 0x11},// FGAINEN[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x341C, 0x47},// ADBIT1[8:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3a18, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3a1a, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3a1c, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3a1e, 0xf7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3a1f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3a20, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3a22, 0x6f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3a24, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x3a26, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x3a28, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) *All-pixel scan CSI-2_4lane 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *AD:10bit Output:10bit 1782Mbps Master Mode DOL HDR 2frame VC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) *Tool ver : Ver3.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct regval imx334_hdr_10_3840x2160_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x302E, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x302F, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x3030, 0xC4},// VMAX[19:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3031, 0x09},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x3034, 0xEF},// HMAX[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x3035, 0x01},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3048, 0x01},// WDMODE[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3049, 0x01},// WDSEL[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x304A, 0x01},// WD_SET1[2:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x304B, 0x02},// WD_SET2[3:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x304C, 0x13},// OPB_SIZE_V[5:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3058, 0xD0},// SHR0[19:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x3059, 0x07},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x3068, 0x51},// RHS1[19:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x3069, 0x05},//{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x3076, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x3077, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x315A, 0x02},// INCKSEL2[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x319E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x31D7, 0x01},// XVSMSKCNT_INT[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x3200, 0x10},// FGAINEN[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x341C, 0xFF},// ADBIT1[8:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3a18, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x3a1a, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x3a1c, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x3a1e, 0xf7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x3a1f, 0xDF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x3a20, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x3a22, 0xCF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x3a24, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x3a26, 0xB7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x3a28, 0x5F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const struct regval imx334_12_3840x2160_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x31A1, 0x00},// XVS_DRV[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3288, 0x21},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x328A, 0x02},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x3414, 0x05},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x3416, 0x18},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x35AC, 0x0E},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x3648, 0x01},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x364A, 0x04},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x364C, 0x04},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x3678, 0x01},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x367C, 0x31},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x367E, 0x31},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3708, 0x02},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x3714, 0x01},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x3715, 0x02},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x3716, 0x02},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x3717, 0x02},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x371C, 0x3D},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x371D, 0x3F},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x372C, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x372D, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x372E, 0x46},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x372F, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3730, 0x89},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x3731, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3732, 0x08},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x3733, 0x01},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x3734, 0xFE},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x3735, 0x05},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x375D, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x375E, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x375F, 0x61},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x3760, 0x06},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x3768, 0x1B},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x3769, 0x1B},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x376A, 0x1A},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x376B, 0x19},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x376C, 0x18},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x376D, 0x14},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x376E, 0x0F},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x3776, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x3777, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x3778, 0x46},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x3779, 0x00},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x377A, 0x08},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x377B, 0x01},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x377C, 0x45},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x377D, 0x01},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x377E, 0x23},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x377F, 0x02},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x3780, 0xD9},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3781, 0x03},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x3782, 0xF5},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x3783, 0x06},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x3784, 0xA5},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x3788, 0x0F},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x378A, 0xD9},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x378B, 0x03},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x378C, 0xEB},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x378D, 0x05},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x378E, 0x87},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x378F, 0x06},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3790, 0xF5},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3792, 0x43},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3794, 0x7A},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x3796, 0xA1},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x3E04, 0x0E},// -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) *IMX334LQR All-pixel scan CSI-2_4lane 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) *AD:12bit Output:12bit 1188Mbps Master Mode 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) *Tool ver : Ver4.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static const struct regval imx334_linear_12_3840x2160_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x302E, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x302F, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x3030, 0xCA},// VMAX[19:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x3031, 0x08},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x300C, 0x5B},// BCWAIT_TIME[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x300D, 0x40},// CPWAIT_TIME[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x3034, 0x4C},// HMAX[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x3035, 0x04},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x3048, 0x00},// WDMODE[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x3049, 0x00},// WDSEL[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x304A, 0x00},// WD_SET1[2:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x304B, 0x01},// WD_SET2[3:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x304C, 0x14},// OPB_SIZE_V[5:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x3058, 0x17},// SHR0[19:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x3059, 0x00},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x3068, 0x8B},// RHS1[19:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x3069, 0x00},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x3076, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x3077, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x314C, 0x80},// INCKSEL 1[8:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x315A, 0x02},// INCKSEL2[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x316A, 0x7E},// INCKSEL4[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x319E, 0x01},// SYS_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x31D7, 0x00},// XVSMSKCNT_INT[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x3200, 0x11},// FGAINEN[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x3A18, 0x8F},// TCLKPOST[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x3A1A, 0x4F},// TCLKPREPARE[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x3A1C, 0x47},// TCLKTRAIL[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x3A1E, 0x37},// TCLKZERO[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x3A20, 0x4F},// THSPREPARE[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x3A22, 0x87},// THSZERO[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x3A24, 0x4F},// THSTRAIL[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x3A26, 0x7F},// THSEXIT[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x3A28, 0x3F},// TLPX[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) *All-pixel scan CSI-2_4lane 74.25Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) *AD:12bit Output:12bit 1782Mbps Master Mode DOL HDR 2frame VC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) *Tool ver : Ver3.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const struct regval imx334_hdr_12_74M_3840x2160_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x302E, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x302F, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x3030, 0xC8},// VMAX[19:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x3031, 0x08},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x300C, 0xB6},// BCWAIT_TIME[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x300D, 0x7F},// CPWAIT_TIME[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x3034, 0x26},// HMAX[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x3035, 0x02},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x3048, 0x01},// WDMODE[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x3049, 0x01},// WDSEL[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x304A, 0x01},// WD_SET1[2:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x304B, 0x02},// WD_SET2[3:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x304C, 0x13},// OPB_SIZE_V[5:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3058, 0xC2},// SHR0[19:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x3059, 0x01},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x3068, 0x19},// RHS1[19:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x3069, 0x01},//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x3076, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x3077, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x314C, 0xC0},// INCKSEL 1[8:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x315A, 0x03},// INCKSEL2[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x316A, 0x7F},// INCKSEL4[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x319E, 0x00},// SYS_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x31D7, 0x01},// XVSMSKCNT_INT[1:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x3200, 0x10},// FGAINEN[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x3A18, 0xB7},// TCLKPOST[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x3A1A, 0x67},// TCLKPREPARE[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x3A1C, 0x6F},// TCLKTRAIL[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x3A1E, 0xDF},// TCLKZERO[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x3A20, 0x6F},// THSPREPARE[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x3A22, 0xCF},// THSZERO[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x3A24, 0x6F},// THSTRAIL[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x3A26, 0xB7},// THSEXIT[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x3A28, 0x5F},// TLPX[15:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const struct imx334_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .width = 3864,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .height = 2180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .exp_def = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .hts_def = 0x044C * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .vts_def = 0x08CA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .global_reg_list = imx334_10_3840x2160_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .reg_list = imx334_linear_10_3840x2160_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .vclk_freq = IMX334_XVCLK_FREQ_37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .width = 3864,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .height = 2180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .exp_def = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .hts_def = 0x01EF * 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .vts_def = 0x09C4 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .global_reg_list = imx334_10_3840x2160_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .reg_list = imx334_hdr_10_3840x2160_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .vclk_freq = IMX334_XVCLK_FREQ_37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .mipi_freq_idx = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .width = 3864,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .height = 2180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .exp_def = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .hts_def = 0x044C * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .vts_def = 0x08CA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .global_reg_list = imx334_12_3840x2160_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .reg_list = imx334_linear_12_3840x2160_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .vclk_freq = IMX334_XVCLK_FREQ_37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .bpp = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .width = 3864,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .height = 2180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .exp_def = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .hts_def = 0x0226 * 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .vts_def = 0x08C8 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .global_reg_list = imx334_12_3840x2160_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .reg_list = imx334_hdr_12_74M_3840x2160_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .vclk_freq = IMX334_XVCLK_FREQ_74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .bpp = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .mipi_freq_idx = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) IMX334_LINK_FREQ_445,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) IMX334_LINK_FREQ_594,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) IMX334_LINK_FREQ_891,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const char * const imx334_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int imx334_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int imx334_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (unlikely(regs[i].addr == REG_DELAY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) usleep_range(regs[i].val, regs[i].val * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = imx334_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int imx334_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (ret == ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (ret != ARRAY_SIZE(msgs) && i == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int imx334_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct imx334 *imx334 = to_imx334(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) const struct imx334_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) s64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mutex_lock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) mode = v4l2_find_nearest_size(supported_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ARRAY_SIZE(supported_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) width, height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) fmt->format.width, fmt->format.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) mutex_unlock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) imx334->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) imx334->cur_vts = imx334->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) __v4l2_ctrl_modify_range(imx334->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) __v4l2_ctrl_modify_range(imx334->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) IMX334_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (imx334->cur_vclk_freq != mode->vclk_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) clk_disable_unprepare(imx334->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ret = clk_set_rate(imx334->xvclk, mode->vclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ret |= clk_prepare_enable(imx334->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dev_err(&imx334->client->dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) mutex_unlock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) imx334->cur_vclk_freq = mode->vclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (imx334->cur_mipi_freq_idx != mode->mipi_freq_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dst_pixel_rate = ((u32)link_freq_menu_items[mode->mipi_freq_idx]) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) mode->bpp * 2 * IMX334_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) __v4l2_ctrl_s_ctrl_int64(imx334->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) __v4l2_ctrl_s_ctrl(imx334->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) imx334->cur_mipi_freq_idx = mode->mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) mutex_unlock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static int imx334_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct imx334 *imx334 = to_imx334(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) const struct imx334_mode *mode = imx334->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) mutex_lock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mutex_unlock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mutex_unlock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int imx334_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct imx334 *imx334 = to_imx334(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) code->code = imx334->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static int imx334_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static int imx334_enable_test_pattern(struct imx334 *imx334, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) val = (pattern - 1) | IMX334_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) val = IMX334_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return imx334_write_reg(imx334->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) IMX334_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static int imx334_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct imx334 *imx334 = to_imx334(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) const struct imx334_mode *mode = imx334->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) mutex_lock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) mutex_unlock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static int imx334_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct imx334 *imx334 = to_imx334(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) const struct imx334_mode *mode = imx334->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) val = 1 << (IMX334_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) config->flags = (mode->hdr_mode == NO_HDR) ? val : (val | V4L2_MBUS_CSI2_CHANNEL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static void imx334_get_module_inf(struct imx334 *imx334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) strlcpy(inf->base.sensor, IMX334_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) strlcpy(inf->base.module, imx334->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) strlcpy(inf->base.lens, imx334->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static int imx334_set_hdrae(struct imx334 *imx334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct i2c_client *client = imx334->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) u32 l_a_gain, m_a_gain, s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u32 shr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u32 shr0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u32 rhs1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) u32 rhs1_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int rhs1_old = 225;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int rhs1_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u32 fsc = imx334->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (!imx334->has_init_exp && !imx334->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) imx334->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) imx334->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dev_dbg(&imx334->client->dev, "imx334 don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) l_a_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) m_a_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) s_a_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "rev exp: L_exp:0x%x,0x%x, M_exp:0x%x,0x%x S_exp:0x%x,0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) l_exp_time, l_a_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) m_exp_time, m_a_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) s_exp_time, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (imx334->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) //2 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) l_a_gain = m_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) //gain effect n+1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ret |= imx334_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) IMX334_LF_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) l_a_gain & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ret |= imx334_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) IMX334_SF1_GAIN_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) s_a_gain & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) //long exposure and short exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) shr0 = fsc - l_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) rhs1_max = (RHS1_MAX > (shr0 - 9)) ? (shr0 - 9) : RHS1_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) rhs1_max = (rhs1_max >> 2) * 4 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) rhs1 = ((SHR1_MIN + s_exp_time + 3) >> 2) * 4 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) dev_dbg(&client->dev, "line(%d) rhs1 %d\n", __LINE__, rhs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (rhs1 < 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) rhs1 = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) else if (rhs1 > rhs1_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) rhs1 = rhs1_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) dev_dbg(&client->dev, "line(%d) rhs1 %d\n", __LINE__, rhs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) //Dynamic adjustment rhs1 must meet the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) rhs1_change_limit = rhs1_old + 2 * BRL - fsc + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) rhs1_change_limit = (rhs1_change_limit < 13) ? 13 : rhs1_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) rhs1_change_limit = ((rhs1_change_limit + 3) >> 2) * 4 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (rhs1 < rhs1_change_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) rhs1 = rhs1_change_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) "line(%d) rhs1 %d,short time %d rhs1_old %d test %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) __LINE__, rhs1, s_exp_time, rhs1_old,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) (rhs1_old + 2 * BRL - fsc + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) rhs1_old = rhs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) shr1 = rhs1 - s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (shr1 < 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) shr1 = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) else if (shr1 > (rhs1 - 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) shr1 = rhs1 - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (shr0 < (rhs1 + 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) shr0 = rhs1 + 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) else if (shr0 > (fsc - 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) shr0 = fsc - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) "fsc=%d,RHS1_MAX=%d,SHR1_MIN=%d,rhs1_max=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) fsc, RHS1_MAX, SHR1_MIN, rhs1_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) "l_exp_time=%d,s_exp_time=%d,shr0=%d,shr1=%d,rhs1=%d,l_a_gain=%d,s_a_gain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) l_exp_time, s_exp_time, shr0, shr1, rhs1, l_a_gain, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) //time effect n+2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ret |= imx334_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) IMX334_RHS1_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) IMX334_FETCH_RHS1_L(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ret |= imx334_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) IMX334_RHS1_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) IMX334_FETCH_RHS1_M(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ret |= imx334_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) IMX334_RHS1_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) IMX334_FETCH_RHS1_H(rhs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ret |= imx334_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) IMX334_SF1_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) IMX334_FETCH_EXP_L(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ret |= imx334_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) IMX334_SF1_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) IMX334_FETCH_EXP_M(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret |= imx334_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) IMX334_SF1_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) IMX334_FETCH_EXP_H(shr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ret |= imx334_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) IMX334_LF_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) IMX334_FETCH_EXP_L(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ret |= imx334_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) IMX334_LF_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) IMX334_FETCH_EXP_M(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ret |= imx334_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) IMX334_LF_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) IMX334_FETCH_EXP_H(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static long imx334_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct imx334 *imx334 = to_imx334(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) s64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) const struct imx334_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return imx334_set_hdrae(imx334, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) imx334_get_module_inf(imx334, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) hdr->hdr_mode = imx334->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) w = imx334->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) h = imx334->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) imx334->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) dev_err(&imx334->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) mode = imx334->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) imx334->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) w = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) h = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) __v4l2_ctrl_modify_range(imx334->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) __v4l2_ctrl_modify_range(imx334->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) IMX334_VTS_MAX -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (imx334->cur_vclk_freq != mode->vclk_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) clk_disable_unprepare(imx334->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ret = clk_set_rate(imx334->xvclk, mode->vclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ret |= clk_prepare_enable(imx334->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dev_err(&imx334->client->dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) imx334->cur_vclk_freq = mode->vclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (imx334->cur_mipi_freq_idx != mode->mipi_freq_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) dst_pixel_rate = ((u32)link_freq_menu_items[mode->mipi_freq_idx]) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) mode->bpp * 2 * IMX334_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) __v4l2_ctrl_s_ctrl_int64(imx334->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) __v4l2_ctrl_s_ctrl(imx334->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) imx334->cur_mipi_freq_idx = mode->mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = imx334_write_reg(imx334->client, IMX334_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) IMX334_REG_VALUE_08BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ret = imx334_write_reg(imx334->client, IMX334_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) IMX334_REG_VALUE_08BIT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static long imx334_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ret = imx334_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ret = imx334_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ret = imx334_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ret = imx334_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ret = imx334_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ret = imx334_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static int __imx334_start_stream(struct imx334 *imx334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ret = imx334_write_array(imx334->client, imx334->cur_mode->global_reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ret = imx334_write_array(imx334->client, imx334->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (imx334->has_init_exp && imx334->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ret = imx334_ioctl(&imx334->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) &imx334->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) dev_err(&imx334->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) mutex_unlock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ret = v4l2_ctrl_handler_setup(&imx334->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) mutex_lock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return imx334_write_reg(imx334->client, IMX334_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) IMX334_REG_VALUE_08BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static int __imx334_stop_stream(struct imx334 *imx334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return imx334_write_reg(imx334->client, IMX334_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) IMX334_REG_VALUE_08BIT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static int imx334_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct imx334 *imx334 = to_imx334(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct i2c_client *client = imx334->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) mutex_lock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (on == imx334->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ret = __imx334_start_stream(imx334);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) __imx334_stop_stream(imx334);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) imx334->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) mutex_unlock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static int imx334_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct imx334 *imx334 = to_imx334(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) struct i2c_client *client = imx334->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) mutex_lock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (imx334->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) imx334->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) imx334->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) mutex_unlock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static inline u32 imx334_cal_delay(u32 cycles, struct imx334 *imx334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (imx334->cur_mode->vclk_freq == IMX334_XVCLK_FREQ_37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return DIV_ROUND_UP(cycles, IMX334_XVCLK_FREQ_37 / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return DIV_ROUND_UP(cycles, IMX334_XVCLK_FREQ_74 / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static int __imx334_power_on(struct imx334 *imx334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) s64 vclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct device *dev = &imx334->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (!IS_ERR_OR_NULL(imx334->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) ret = pinctrl_select_state(imx334->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) imx334->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (imx334->cur_mode->vclk_freq == IMX334_XVCLK_FREQ_37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) vclk_freq = IMX334_XVCLK_FREQ_37;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) vclk_freq = IMX334_XVCLK_FREQ_74;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ret = clk_set_rate(imx334->xvclk, vclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (clk_get_rate(imx334->xvclk) != vclk_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) dev_warn(dev, "xvclk mismatched, modes are based on 37.125MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ret = clk_prepare_enable(imx334->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (!IS_ERR(imx334->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) gpiod_set_value_cansleep(imx334->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) ret = regulator_bulk_enable(IMX334_NUM_SUPPLIES, imx334->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (!IS_ERR(imx334->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) gpiod_set_value_cansleep(imx334->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (!IS_ERR(imx334->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) gpiod_set_value_cansleep(imx334->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) delay_us = imx334_cal_delay(8192, imx334);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) clk_disable_unprepare(imx334->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static void __imx334_power_off(struct imx334 *imx334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (!IS_ERR(imx334->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) gpiod_set_value_cansleep(imx334->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) clk_disable_unprepare(imx334->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (!IS_ERR(imx334->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) gpiod_set_value_cansleep(imx334->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) regulator_bulk_disable(IMX334_NUM_SUPPLIES, imx334->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static int imx334_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) struct imx334 *imx334 = to_imx334(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return __imx334_power_on(imx334);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static int imx334_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) struct imx334 *imx334 = to_imx334(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) __imx334_power_off(imx334);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static int imx334_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) struct imx334 *imx334 = to_imx334(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) const struct imx334_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) mutex_lock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) mutex_unlock(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static int imx334_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define DST_WIDTH 3840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define DST_HEIGHT 2160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static int imx334_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) struct imx334 *imx334 = to_imx334(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) sel->r.left = CROP_START(imx334->cur_mode->width, DST_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) sel->r.width = DST_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) sel->r.top = CROP_START(imx334->cur_mode->height, DST_HEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) sel->r.height = DST_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static const struct dev_pm_ops imx334_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) SET_RUNTIME_PM_OPS(imx334_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) imx334_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static const struct v4l2_subdev_internal_ops imx334_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .open = imx334_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static const struct v4l2_subdev_core_ops imx334_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .s_power = imx334_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .ioctl = imx334_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .compat_ioctl32 = imx334_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static const struct v4l2_subdev_video_ops imx334_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .s_stream = imx334_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .g_frame_interval = imx334_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) static const struct v4l2_subdev_pad_ops imx334_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .enum_mbus_code = imx334_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .enum_frame_size = imx334_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .enum_frame_interval = imx334_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .get_fmt = imx334_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .set_fmt = imx334_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .get_selection = imx334_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .get_mbus_config = imx334_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) static const struct v4l2_subdev_ops imx334_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .core = &imx334_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .video = &imx334_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .pad = &imx334_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static int imx334_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) struct imx334 *imx334 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct imx334, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) struct i2c_client *client = imx334->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) u32 shr0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) u32 vts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) u32 flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) max = imx334->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) __v4l2_ctrl_modify_range(imx334->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) imx334->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) imx334->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) imx334->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) shr0 = imx334->cur_vts - ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) ret = imx334_write_reg(imx334->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) IMX334_LF_EXPO_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) IMX334_FETCH_EXP_H(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) ret |= imx334_write_reg(imx334->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) IMX334_LF_EXPO_REG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) IMX334_FETCH_EXP_M(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) ret |= imx334_write_reg(imx334->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) IMX334_LF_EXPO_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) IMX334_FETCH_EXP_L(shr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) ret = imx334_write_reg(imx334->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) IMX334_REG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) IMX334_REG_VALUE_08BIT, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) vts = ctrl->val + imx334->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * vts of hdr mode is double to correct T-line calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) * Restore before write to reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (imx334->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) vts = ((vts + 3) >> 2) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) imx334->cur_vts = vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) vts = vts >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) imx334->cur_vts = vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) ret = imx334_write_reg(imx334->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) IMX334_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) IMX334_FETCH_VTS_H(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) ret |= imx334_write_reg(imx334->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) IMX334_REG_VTS_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) IMX334_FETCH_VTS_M(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) ret |= imx334_write_reg(imx334->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) IMX334_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) IMX334_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) IMX334_FETCH_VTS_L(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) ret = imx334_enable_test_pattern(imx334, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) ret = imx334_write_reg(imx334->client, IMX334_HREVERSE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) IMX334_REG_VALUE_08BIT, !!ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) flip = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (flip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) ret = imx334_write_reg(imx334->client, IMX334_VREVERSE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) IMX334_REG_VALUE_08BIT, !!flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) ret |= imx334_write_reg(imx334->client, 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) IMX334_REG_VALUE_08BIT, 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) ret |= imx334_write_reg(imx334->client, 0x309b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) IMX334_REG_VALUE_08BIT, 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) ret = imx334_write_reg(imx334->client, IMX334_VREVERSE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) IMX334_REG_VALUE_08BIT, !!flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) ret |= imx334_write_reg(imx334->client, 0x3080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) IMX334_REG_VALUE_08BIT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) ret |= imx334_write_reg(imx334->client, 0x309b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) IMX334_REG_VALUE_08BIT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) static const struct v4l2_ctrl_ops imx334_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .s_ctrl = imx334_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) static int imx334_initialize_controls(struct imx334 *imx334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) const struct imx334_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) s64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) handler = &imx334->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) mode = imx334->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) handler->lock = &imx334->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) imx334->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) 2, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) dst_pixel_rate = ((u32)link_freq_menu_items[mode->mipi_freq_idx]) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) mode->bpp * 2 * IMX334_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) imx334->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) 0, PIXEL_RATE_WITH_891M_10BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) v4l2_ctrl_s_ctrl(imx334->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) imx334->cur_mipi_freq_idx = mode->mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) imx334->cur_vclk_freq = mode->vclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) imx334->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (imx334->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) imx334->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) imx334->vblank = v4l2_ctrl_new_std(handler, &imx334_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) IMX334_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) imx334->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) imx334->exposure = v4l2_ctrl_new_std(handler, &imx334_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) V4L2_CID_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) IMX334_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) exposure_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) IMX334_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) imx334->anal_gain = v4l2_ctrl_new_std(handler, &imx334_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) V4L2_CID_ANALOGUE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) IMX334_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) IMX334_GAIN_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) IMX334_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) IMX334_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) imx334->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) &imx334_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) ARRAY_SIZE(imx334_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) 0, 0, imx334_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) v4l2_ctrl_new_std(handler, &imx334_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) v4l2_ctrl_new_std(handler, &imx334_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) dev_err(&imx334->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) "Failed to init controls( %d )\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) imx334->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) imx334->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static int imx334_check_sensor_id(struct imx334 *imx334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) struct device *dev = &imx334->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) ret = imx334_read_reg(client, IMX334_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) IMX334_REG_VALUE_08BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (id == CHIP_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) usleep_range(2000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) dev_info(dev, "Detected imx334 id:%06x\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static int imx334_configure_regulators(struct imx334 *imx334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) for (i = 0; i < IMX334_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) imx334->supplies[i].supply = imx334_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) return devm_regulator_bulk_get(&imx334->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) IMX334_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) imx334->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static int imx334_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) struct imx334 *imx334;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) imx334 = devm_kzalloc(dev, sizeof(*imx334), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (!imx334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) &imx334->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) &imx334->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) &imx334->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) &imx334->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) imx334->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) imx334->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) if (i == ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) imx334->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) imx334->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (IS_ERR(imx334->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) imx334->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) if (IS_ERR(imx334->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) imx334->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (IS_ERR(imx334->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) imx334->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (!IS_ERR(imx334->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) imx334->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) pinctrl_lookup_state(imx334->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (IS_ERR(imx334->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) dev_info(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) imx334->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) pinctrl_lookup_state(imx334->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (IS_ERR(imx334->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) dev_info(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) dev_info(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) ret = imx334_configure_regulators(imx334);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) mutex_init(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) sd = &imx334->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) v4l2_i2c_subdev_init(sd, client, &imx334_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) ret = imx334_initialize_controls(imx334);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ret = __imx334_power_on(imx334);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) ret = imx334_check_sensor_id(imx334, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) sd->internal_ops = &imx334_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) imx334->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) ret = media_entity_pads_init(&sd->entity, 1, &imx334->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (strcmp(imx334->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) imx334->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) IMX334_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) __imx334_power_off(imx334);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) v4l2_ctrl_handler_free(&imx334->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) mutex_destroy(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) static int imx334_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) struct imx334 *imx334 = to_imx334(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) v4l2_ctrl_handler_free(&imx334->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) mutex_destroy(&imx334->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) __imx334_power_off(imx334);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) static const struct of_device_id imx334_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) { .compatible = "sony,imx334" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) MODULE_DEVICE_TABLE(of, imx334_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static const struct i2c_device_id imx334_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) { "sony,imx334", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static struct i2c_driver imx334_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .name = IMX334_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .pm = &imx334_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .of_match_table = of_match_ptr(imx334_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .probe = &imx334_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .remove = &imx334_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .id_table = imx334_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) return i2c_add_driver(&imx334_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) i2c_del_driver(&imx334_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) MODULE_DESCRIPTION("Sony imx334 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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