^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * imx327 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X04 support lvds interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X05 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X06 fixed linear mode exp calc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX327_LINK_FREQ_111M 111370000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX327_LINK_FREQ_222M 222750000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX327_2LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX327_4LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX327_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX327_PIXEL_RATE_NORMAL (IMX327_LINK_FREQ_111M * 2 / 10 * IMX327_4LANES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX327_PIXEL_RATE_HDR (IMX327_LINK_FREQ_222M * 2 / 10 * IMX327_4LANES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX327_XVCLK_FREQ 37125000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CHIP_ID 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX327_REG_CHIP_ID 0x301e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX327_REG_CTRL_MODE 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX327_MODE_SW_STANDBY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX327_MODE_STREAMING 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX327_REG_SHS1_H 0x3022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX327_REG_SHS1_M 0x3021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX327_REG_SHS1_L 0x3020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX327_REG_SHS2_H 0x3026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX327_REG_SHS2_M 0x3025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX327_REG_SHS2_L 0x3024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX327_REG_RHS1_H 0x3032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX327_REG_RHS1_M 0x3031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX327_REG_RHS1_L 0x3030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX327_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX327_FETCH_MID_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX327_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX327_EXPOSURE_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX327_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX327_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX327_GAIN_SWITCH_REG 0x3009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX327_REG_LF_GAIN 0x3014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX327_REG_SF_GAIN 0x30f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX327_GAIN_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX327_GAIN_MAX 0xee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX327_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX327_GAIN_DEFAULT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX327_GROUP_HOLD_REG 0x3001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX327_GROUP_HOLD_START 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX327_GROUP_HOLD_END 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define USED_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #ifdef USED_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX327_REG_TEST_PATTERN 0x308c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX327_TEST_PATTERN_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX327_REG_VTS_H 0x301a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMX327_REG_VTS_M 0x3019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX327_REG_VTS_L 0x3018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX327_FETCH_HIGH_BYTE_VTS(VAL) (((VAL) >> 16) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX327_FETCH_MID_BYTE_VTS(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX327_FETCH_LOW_BYTE_VTS(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX327_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX327_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX327_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static bool g_isHCG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX327_NAME "imx327"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX327_FLIP_REG 0x3007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MIRROR_BIT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define FLIP_BIT_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const char * const imx327_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX327_NUM_SUPPLIES ARRAY_SIZE(imx327_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct imx327_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct rkmodule_lvds_cfg lvds_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct imx327 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct regulator_bulk_data supplies[IMX327_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct v4l2_ctrl *h_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct v4l2_ctrl *v_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #ifdef USED_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const struct imx327_mode *support_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 support_modes_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) const struct imx327_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct v4l2_fwnode_endpoint bus_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define to_imx327(sd) container_of(sd, struct imx327, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct regval imx327_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * lvds_datarate per lane 222.75Mbps 4 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct regval imx327_linear_1920x1080_lvds_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3003, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3007, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3009, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x300a, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3010, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3011, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3018, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3019, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x301c, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x301d, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3046, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x304b, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x305c, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x305d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x305e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x305f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x309e, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x309f, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x311c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3128, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3129, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x313b, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x315e, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3164, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x317c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x31ec, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3480, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * lvds_datarate per lane 445.5Mbps 4 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const struct regval imx327_hdr2_1920x1080_lvds_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3003, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3007, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3009, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x300a, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x300c, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3011, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3018, 0xb8},/* VMAX L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3019, 0x05},/* VMAX M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x301c, 0xec},/* HMAX L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x301d, 0x07},/* HMAX H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3020, 0x02},//hdr+ shs1 l short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3021, 0x00},//hdr+ shs1 m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3024, 0xc9},//hdr+ shs2 l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x3025, 0x07},//hdr+ shs2 m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3030, 0xe1},//hdr+ IMX327_RHS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3031, 0x00},//hdr+IMX327_RHS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3045, 0x03},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3046, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x304b, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x305c, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x305d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x305e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x305f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x309e, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x309f, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x30d2, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x30d7, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3106, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3129, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x313b, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x315e, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3164, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x317c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x31ec, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x3414, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x3415, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3480, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x31a0, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x31a1, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x303c, 0x04},//Y offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x303d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x303e, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x303f, 0x04},//height
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x303A, 0x08},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3010, 0x61},//hdr+ gain 1frame FPGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3014, 0x00},//hdr+ gain 1frame long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x30F0, 0x64},//hdr+ gain 2frame FPGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x30f2, 0x00},//hdr+ gain 2frame short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * mipi_datarate per lane 222.75Mbps 4 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const struct regval imx327_linear_1920x1080_mipi_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3003, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x3007, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x3009, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x300A, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3010, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3011, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x3018, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x3019, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x301C, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x301D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x3046, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x304B, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x305C, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x305D, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x305E, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x305F, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x309E, 0x4A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x309F, 0x4A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x311c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3128, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x3129, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x313B, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x315E, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3164, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x317C, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x31EC, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x3405, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x3407, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x3414, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x3418, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3419, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x3441, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x3442, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3443, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3444, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x3445, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x3446, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x3447, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x3448, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x3449, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x344A, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x344B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x344C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x344D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x344E, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x344F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x3450, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x3451, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3452, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3453, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3454, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3455, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3472, 0x9c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x3473, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x3480, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * mipi_datarate per lane 445.5Mbps 4 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct regval imx327_hdr2_1920x1080_mipi_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x3003, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3007, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3009, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x300a, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x300c, 0x11}, //hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3011, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x3018, 0xb8},/* VMAX L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x3019, 0x05},/* VMAX M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x301a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x301c, 0xEc},/* HMAX L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x301d, 0x07},/* HMAX H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x3045, 0x05},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x3046, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x304b, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x305c, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x305d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x305e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x305f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x309e, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x309f, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x30d2, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x30d7, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x3106, 0x11},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x3129, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x313b, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x315e, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x3164, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x317c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x31ec, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x3405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x3407, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3414, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x3415, 0x00},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x3418, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x3419, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x3441, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x3442, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3443, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x3444, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x3445, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3446, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3447, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3448, 0x37},//37?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3449, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x344a, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x344b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x344c, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x344d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x344e, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x344f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x3450, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x3451, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x3452, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x3453, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3454, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3455, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x3472, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x3473, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x347b, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x3480, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x31a0, 0xb4},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x31a1, 0x02},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x3020, 0x02},//hdr+ shs1 l short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x3021, 0x00},//hdr+ shs1 m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x3022, 0x00},//hdr+ shs1 h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x3030, 0xe1},//hdr+ IMX327_RHS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x3031, 0x00},//hdr+IMX327_RHS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x3032, 0x00},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x31A0, 0xe8},//hdr+ HBLANK1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x31A1, 0x01},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x303c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x303d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x303e, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x303f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x303A, 0x08},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x3024, 0xc9},//hdr+ shs2 l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x3025, 0x06},//hdr+ shs2 m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x3026, 0x00},//hdr+ shs2 h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x3010, 0x61},//hdr+ gain 1frame FPGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x3014, 0x00},//hdr+ gain 1frame long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x30F0, 0x64},//hdr+ gain 2frame FPGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x30f2, 0x00},//hdr+ gain 2frame short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * The width and height must be configured to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * the same as the current output resolution of the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * The input width of the isp needs to be 16 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * The input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * If the width or height does not meet the alignment rules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * you can configure the cropping parameters with the following function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * crop out the appropriate resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * struct v4l2_subdev_pad_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * .get_selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct imx327_mode lvds_supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .width = 1948,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .height = 1110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .exp_def = 0x03fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .hts_def = 0x1130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .vts_def = 0x0546,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .reg_list = imx327_linear_1920x1080_lvds_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .lvds_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .mode = LS_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .frm_sync_code[LVDS_CODE_GRP_LINEAR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .odd_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .sav = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .eav = 0x274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .sav = 0x2ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .eav = 0x2d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .width = 1948,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .height = 1098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .exp_def = 0x0473,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .hts_def = 0x07ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .vts_def = 0x05b8 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .reg_list = imx327_hdr2_1920x1080_lvds_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .lvds_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .mode = SONY_DOL_HDR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .frm_sync_code[LVDS_CODE_GRP_LONG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .odd_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .sav = 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .eav = 0x075,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .sav = 0x0ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .eav = 0x0d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .even_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .sav = 0x101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .eav = 0x175,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .sav = 0x1ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .eav = 0x1d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .frm_sync_code[LVDS_CODE_GRP_SHORT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .odd_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .sav = 0x002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .eav = 0x076,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .sav = 0x0ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .eav = 0x0d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .even_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .sav = 0x102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .eav = 0x176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .sav = 0x1ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .eav = 0x1d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const struct imx327_mode mipi_supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .width = 1948,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .height = 1097,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .exp_def = 0x03fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .hts_def = 0x1130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .vts_def = 0x0546,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .reg_list = imx327_linear_1920x1080_mipi_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .width = 1952,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .height = 1089,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .exp_def = 0x0473,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .hts_def = 0x07ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .vts_def = 0x05b8 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .reg_list = imx327_hdr2_1920x1080_mipi_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) IMX327_LINK_FREQ_111M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) IMX327_LINK_FREQ_222M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #ifdef USED_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static const char * const imx327_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) "Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) "Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) "Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) "Bar Type 4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "Bar Type 5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "Bar Type 6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) "Bar Type 7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) "Bar Type 8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "Bar Type 9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) "Bar Type 10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "Bar Type 11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "Bar Type 12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "Bar Type 13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "Bar Type 14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "Bar Type 15"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int imx327_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int imx327_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (unlikely(regs[i].addr == REG_DELAY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) usleep_range(regs[i].val * 1000, regs[i].val * 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ret = imx327_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int imx327_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int imx327_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) const struct imx327_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) s32 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) s64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) mutex_lock(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) mode = v4l2_find_nearest_size(imx327->support_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) imx327->support_modes_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) width, height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) fmt->format.width, fmt->format.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) mutex_unlock(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) imx327->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) __v4l2_ctrl_modify_range(imx327->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) __v4l2_ctrl_modify_range(imx327->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) IMX327_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (imx327->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dst_pixel_rate = IMX327_LINK_FREQ_111M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dst_link_freq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dst_pixel_rate = IMX327_LINK_FREQ_222M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) __v4l2_ctrl_s_ctrl_int64(imx327->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) __v4l2_ctrl_s_ctrl(imx327->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) imx327->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) mutex_unlock(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static int imx327_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) const struct imx327_mode *mode = imx327->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) mutex_lock(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mutex_unlock(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mutex_unlock(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int imx327_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) const struct imx327_mode *mode = imx327->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) code->code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int imx327_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (fse->index >= imx327->support_modes_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (fse->code != imx327->support_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) fse->min_width = imx327->support_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) fse->max_width = imx327->support_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) fse->max_height = imx327->support_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) fse->min_height = imx327->support_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #ifdef USED_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int imx327_enable_test_pattern(struct imx327 *imx327, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) imx327_read_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) IMX327_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (pattern) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) val = ((pattern - 1) << 4) | IMX327_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) 0x300a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) 0x300e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) val &= ~IMX327_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) 0x300a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) 0x300e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) IMX327_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int imx327_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) const struct imx327_mode *mode = imx327->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) mutex_lock(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) mutex_unlock(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static int imx327_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) val = 1 << (IMX327_4LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) config->type = imx327->bus_cfg.bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int imx327_set_hdrae(struct imx327 *imx327,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) u32 l_gain, m_gain, s_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) u32 shs1, shs2, rhs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) u32 gain_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) u8 cg_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) u32 fsc = imx327->cur_vts;//The HDR mode vts is double by default to workaround T-line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (!imx327->has_init_exp && !imx327->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) imx327->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) imx327->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dev_dbg(&imx327->client->dev, "imx327 don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) l_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) m_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) s_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (imx327->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) //2 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) l_gain = m_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) cg_mode = ae->middle_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) dev_dbg(&imx327->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) "rev exp req: L_time=%d, gain=%d, S_time=%d, gain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) l_exp_time, l_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) s_exp_time, s_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret = imx327_read_reg(imx327->client, IMX327_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) IMX327_REG_VALUE_08BIT, &gain_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (!g_isHCG && cg_mode == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) gain_switch |= 0x0110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) g_isHCG = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) } else if (g_isHCG && cg_mode == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) gain_switch &= 0xef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) gain_switch |= 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) g_isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) //long exposure and short exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) rhs1 = 0xe1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) shs1 = rhs1 - s_exp_time - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) shs2 = fsc - l_exp_time - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (shs1 < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) shs1 = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (shs2 < (rhs1 + 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) shs2 = rhs1 + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) else if (shs2 > (fsc - 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) shs2 = fsc - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ret |= imx327_write_reg(imx327->client, IMX327_REG_SHS1_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) IMX327_FETCH_LOW_BYTE_EXP(shs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ret |= imx327_write_reg(imx327->client, IMX327_REG_SHS1_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) IMX327_FETCH_MID_BYTE_EXP(shs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ret |= imx327_write_reg(imx327->client, IMX327_REG_SHS1_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) IMX327_FETCH_HIGH_BYTE_EXP(shs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ret |= imx327_write_reg(imx327->client, IMX327_REG_SHS2_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) IMX327_FETCH_LOW_BYTE_EXP(shs2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ret |= imx327_write_reg(imx327->client, IMX327_REG_SHS2_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) IMX327_FETCH_MID_BYTE_EXP(shs2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ret |= imx327_write_reg(imx327->client, IMX327_REG_SHS2_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) IMX327_FETCH_HIGH_BYTE_EXP(shs2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ret |= imx327_write_reg(imx327->client, IMX327_REG_LF_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) l_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ret |= imx327_write_reg(imx327->client, IMX327_REG_SF_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) s_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (gain_switch & 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ret |= imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) IMX327_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) IMX327_GROUP_HOLD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ret |= imx327_write_reg(imx327->client, IMX327_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) IMX327_REG_VALUE_08BIT, gain_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ret |= imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) IMX327_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) IMX327_GROUP_HOLD_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) dev_dbg(&imx327->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) "set l_gain:0x%x s_gain:0x%x shs2:0x%x shs1:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) l_gain, s_gain, shs2, shs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static void imx327_get_module_inf(struct imx327 *imx327,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) strlcpy(inf->base.sensor, IMX327_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) strlcpy(inf->base.module, imx327->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) strlcpy(inf->base.lens, imx327->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static int imx327_set_conversion_gain(struct imx327 *imx327, u32 *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct i2c_client *client = imx327->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) int cur_cg = *cg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u32 gain_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ret = imx327_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) IMX327_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) &gain_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (g_isHCG && cur_cg == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) gain_switch &= 0xef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) gain_switch |= 0x0100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) g_isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) } else if (!g_isHCG && cur_cg == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) gain_switch |= 0x0110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) g_isHCG = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (gain_switch & 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret |= imx327_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) IMX327_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) IMX327_GROUP_HOLD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ret |= imx327_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) IMX327_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) gain_switch & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ret |= imx327_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) IMX327_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) IMX327_GROUP_HOLD_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) //ag: echo 0 > /sys/devices/platform/ff510000.i2c/i2c-1/1-0037/cam_s_cg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static ssize_t set_conversion_gain_status(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ret = kstrtoint(buf, 0, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (!ret && status >= 0 && status < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) imx327_set_conversion_gain(imx327, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) dev_err(dev, "input 0 for LCG, 1 for HCG, cur %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static struct device_attribute attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) __ATTR(cam_s_cg, S_IWUSR, NULL, set_conversion_gain_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static int add_sysfs_interfaces(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) for (i = 0; i < ARRAY_SIZE(attributes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (device_create_file(dev, attributes + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) goto undo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) undo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) for (i--; i >= 0 ; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) device_remove_file(dev, attributes + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dev_err(dev, "%s: failed to create sysfs interface\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static long imx327_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct rkmodule_lvds_cfg *lvds_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) s64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) s32 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) imx327_get_module_inf(imx327, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ret = imx327_set_hdrae(imx327, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (imx327->cur_mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) hdr->esp.mode = HDR_ID_CODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) hdr->hdr_mode = imx327->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) for (i = 0; i < imx327->support_modes_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (imx327->support_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) imx327->cur_mode = &imx327->support_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (i == imx327->support_modes_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) dev_err(&imx327->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) "not find hdr mode:%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) hdr->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) w = imx327->cur_mode->hts_def - imx327->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) h = imx327->cur_mode->vts_def - imx327->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) __v4l2_ctrl_modify_range(imx327->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) __v4l2_ctrl_modify_range(imx327->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) IMX327_VTS_MAX - imx327->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (imx327->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) dst_pixel_rate = IMX327_PIXEL_RATE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dst_link_freq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) dst_pixel_rate = IMX327_PIXEL_RATE_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) __v4l2_ctrl_s_ctrl_int64(imx327->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) __v4l2_ctrl_s_ctrl(imx327->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) imx327->cur_vts = imx327->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ret = imx327_set_conversion_gain(imx327, (u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) case RKMODULE_GET_LVDS_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) lvds_cfg = (struct rkmodule_lvds_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (imx327->bus_cfg.bus_type == V4L2_MBUS_CCP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) memcpy(lvds_cfg, &imx327->cur_mode->lvds_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) sizeof(struct rkmodule_lvds_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ret = imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) IMX327_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ret = imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) IMX327_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static long imx327_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) u32 cg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = imx327_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ret = imx327_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ret = imx327_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ret = imx327_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ret = imx327_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ret = copy_from_user(&cg, up, sizeof(cg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret = imx327_ioctl(sd, cmd, &cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ret = imx327_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static int imx327_init_conversion_gain(struct imx327 *imx327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct i2c_client *client = imx327->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) ret = imx327_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) IMX327_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) val &= 0xef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ret = imx327_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) IMX327_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) g_isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static int __imx327_start_stream(struct imx327 *imx327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ret = imx327_write_array(imx327->client, imx327->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ret = imx327_init_conversion_gain(imx327);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ret = __v4l2_ctrl_handler_setup(&imx327->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (imx327->has_init_exp && imx327->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) ret = imx327_ioctl(&imx327->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) &imx327->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) dev_err(&imx327->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) ret = imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) IMX327_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static int __imx327_stop_stream(struct imx327 *imx327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) return imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) IMX327_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) static int imx327_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct i2c_client *client = imx327->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) mutex_lock(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (on == imx327->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ret = __imx327_start_stream(imx327);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) __imx327_stop_stream(imx327);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) imx327->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) mutex_unlock(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static int imx327_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) struct i2c_client *client = imx327->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) mutex_lock(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (imx327->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ret = imx327_write_array(imx327->client, imx327_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) imx327->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) imx327->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) mutex_unlock(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static inline u32 imx327_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return DIV_ROUND_UP(cycles, IMX327_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static int __imx327_power_on(struct imx327 *imx327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct device *dev = &imx327->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (!IS_ERR_OR_NULL(imx327->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ret = pinctrl_select_state(imx327->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) imx327->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ret = clk_set_rate(imx327->xvclk, IMX327_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) dev_warn(dev, "Failed to set xvclk rate (37.125M Hz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (clk_get_rate(imx327->xvclk) != IMX327_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) dev_warn(dev, "xvclk mismatched,based on 24M Hz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) ret = clk_prepare_enable(imx327->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ret = regulator_bulk_enable(IMX327_NUM_SUPPLIES, imx327->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (!IS_ERR(imx327->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) gpiod_set_value_cansleep(imx327->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (!IS_ERR(imx327->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) gpiod_set_value_cansleep(imx327->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (!IS_ERR(imx327->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) gpiod_set_value_cansleep(imx327->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) delay_us = imx327_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) clk_disable_unprepare(imx327->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) static void __imx327_power_off(struct imx327 *imx327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) struct device *dev = &imx327->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (!IS_ERR(imx327->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) gpiod_set_value_cansleep(imx327->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) clk_disable_unprepare(imx327->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (!IS_ERR(imx327->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) gpiod_set_value_cansleep(imx327->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (!IS_ERR_OR_NULL(imx327->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) ret = pinctrl_select_state(imx327->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) imx327->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) regulator_bulk_disable(IMX327_NUM_SUPPLIES, imx327->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static int imx327_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return __imx327_power_on(imx327);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static int imx327_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) __imx327_power_off(imx327);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static int imx327_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) const struct imx327_mode *def_mode = &imx327->support_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) mutex_lock(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) mutex_unlock(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static int imx327_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (fie->index >= imx327->support_modes_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) fie->code = imx327->support_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) fie->width = imx327->support_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) fie->height = imx327->support_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) fie->interval = imx327->support_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) fie->reserved[0] = imx327->support_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define DST_WIDTH 1920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #define DST_HEIGHT 1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * The resolution of the driver configuration needs to be exactly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * the same as the current output resolution of the sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) * the input width of the isp needs to be 16 aligned,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * the input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * Can be cropped to standard resolution by this function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * otherwise it will crop out strange resolution according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * to the alignment rules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static int imx327_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) sel->r.left = CROP_START(imx327->cur_mode->width, DST_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) sel->r.width = DST_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (imx327->bus_cfg.bus_type == V4L2_MBUS_CCP2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (imx327->cur_mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) sel->r.top = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) sel->r.top = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) sel->r.top = CROP_START(imx327->cur_mode->height, DST_HEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) sel->r.height = DST_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) static const struct dev_pm_ops imx327_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) SET_RUNTIME_PM_OPS(imx327_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) imx327_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static const struct v4l2_subdev_internal_ops imx327_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .open = imx327_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) static const struct v4l2_subdev_core_ops imx327_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .s_power = imx327_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .ioctl = imx327_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .compat_ioctl32 = imx327_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static const struct v4l2_subdev_video_ops imx327_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .s_stream = imx327_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .g_frame_interval = imx327_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static const struct v4l2_subdev_pad_ops imx327_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .enum_mbus_code = imx327_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .enum_frame_size = imx327_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .enum_frame_interval = imx327_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .get_fmt = imx327_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .set_fmt = imx327_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .get_selection = imx327_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .get_mbus_config = imx327_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static const struct v4l2_subdev_ops imx327_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .core = &imx327_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .video = &imx327_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .pad = &imx327_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) static int imx327_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) struct imx327 *imx327 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) struct imx327, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) struct i2c_client *client = imx327->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) u32 shs1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) u32 vts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) max = imx327->cur_mode->height + ctrl->val - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) __v4l2_ctrl_modify_range(imx327->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) imx327->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) imx327->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) imx327->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) if (imx327->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) shs1 = imx327->cur_vts - ctrl->val - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) ret = imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) IMX327_REG_SHS1_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) IMX327_FETCH_HIGH_BYTE_EXP(shs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) ret |= imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) IMX327_REG_SHS1_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) IMX327_FETCH_MID_BYTE_EXP(shs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) ret |= imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) IMX327_REG_SHS1_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) IMX327_FETCH_LOW_BYTE_EXP(shs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) dev_dbg(&client->dev, "set exposure 0x%x, cur_vts 0x%x,shs1 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) ctrl->val, imx327->cur_vts, shs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (imx327->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) ret = imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) IMX327_REG_LF_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) dev_dbg(&client->dev, "set analog gain 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) vts = ctrl->val + imx327->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) imx327->cur_vts = vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (imx327->cur_mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) vts /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) ret = imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) IMX327_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) IMX327_FETCH_HIGH_BYTE_VTS(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) ret |= imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) IMX327_REG_VTS_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) IMX327_FETCH_MID_BYTE_VTS(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) ret |= imx327_write_reg(imx327->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) IMX327_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) IMX327_FETCH_LOW_BYTE_VTS(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) dev_dbg(&client->dev, "set vts 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) vts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) #ifdef USED_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) ret = imx327_enable_test_pattern(imx327, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) ret = imx327_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) IMX327_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) val |= MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) val &= ~MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) ret |= imx327_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) IMX327_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) imx327->flip = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ret = imx327_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) IMX327_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) val |= FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) val &= ~FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) ret |= imx327_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) IMX327_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) IMX327_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) imx327->flip = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) static const struct v4l2_ctrl_ops imx327_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .s_ctrl = imx327_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) static int imx327_initialize_controls(struct imx327 *imx327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) const struct imx327_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) s32 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) s64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) handler = &imx327->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) mode = imx327->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) handler->lock = &imx327->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) imx327->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) 1, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (imx327->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) dst_pixel_rate = IMX327_PIXEL_RATE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) dst_link_freq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) dst_pixel_rate = IMX327_PIXEL_RATE_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) __v4l2_ctrl_s_ctrl(imx327->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) imx327->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) 0, IMX327_PIXEL_RATE_HDR, 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) imx327->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if (imx327->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) imx327->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) imx327->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) imx327->vblank = v4l2_ctrl_new_std(handler, &imx327_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) IMX327_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) exposure_max = mode->vts_def - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) imx327->exposure = v4l2_ctrl_new_std(handler, &imx327_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) V4L2_CID_EXPOSURE, IMX327_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) exposure_max, IMX327_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) imx327->anal_gain = v4l2_ctrl_new_std(handler, &imx327_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) V4L2_CID_ANALOGUE_GAIN, IMX327_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) IMX327_GAIN_MAX, IMX327_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) IMX327_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #ifdef USED_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) imx327->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) &imx327_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) ARRAY_SIZE(imx327_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) 0, 0, imx327_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) imx327->h_flip = v4l2_ctrl_new_std(handler, &imx327_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) imx327->v_flip = v4l2_ctrl_new_std(handler, &imx327_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) imx327->flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) dev_err(&imx327->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) imx327->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) imx327->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static int imx327_check_sensor_id(struct imx327 *imx327,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) struct device *dev = &imx327->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) ret = imx327_read_reg(client, IMX327_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) IMX327_REG_VALUE_08BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) static int imx327_configure_regulators(struct imx327 *imx327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) for (i = 0; i < IMX327_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) imx327->supplies[i].supply = imx327_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) return devm_regulator_bulk_get(&imx327->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) IMX327_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) imx327->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) static int imx327_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) struct imx327 *imx327;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) imx327 = devm_kzalloc(dev, sizeof(*imx327), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) if (!imx327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) &imx327->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) &imx327->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) &imx327->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) &imx327->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) &imx327->bus_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) if (imx327->bus_cfg.bus_type == V4L2_MBUS_CCP2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) imx327->support_modes = lvds_supported_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) imx327->support_modes_num = ARRAY_SIZE(lvds_supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) imx327->support_modes = mipi_supported_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) imx327->support_modes_num = ARRAY_SIZE(mipi_supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) imx327->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) imx327->cur_mode = &imx327->support_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) imx327->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if (IS_ERR(imx327->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) imx327->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) if (IS_ERR(imx327->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) imx327->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (IS_ERR(imx327->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) ret = imx327_configure_regulators(imx327);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) imx327->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (!IS_ERR(imx327->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) imx327->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) pinctrl_lookup_state(imx327->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) if (IS_ERR(imx327->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) imx327->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) pinctrl_lookup_state(imx327->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (IS_ERR(imx327->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) mutex_init(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) sd = &imx327->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) v4l2_i2c_subdev_init(sd, client, &imx327_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) ret = imx327_initialize_controls(imx327);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) ret = __imx327_power_on(imx327);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) ret = imx327_check_sensor_id(imx327, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) dev_err(dev, "set the video v4l2 subdev api\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) sd->internal_ops = &imx327_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) dev_err(dev, "set the media controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) imx327->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) ret = media_entity_pads_init(&sd->entity, 1, &imx327->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) if (strcmp(imx327->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) imx327->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) IMX327_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) g_isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) add_sysfs_interfaces(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) dev_err(dev, "v4l2 async register subdev success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) __imx327_power_off(imx327);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) v4l2_ctrl_handler_free(&imx327->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) mutex_destroy(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) static int imx327_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) struct imx327 *imx327 = to_imx327(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) v4l2_ctrl_handler_free(&imx327->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) mutex_destroy(&imx327->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) __imx327_power_off(imx327);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) static const struct of_device_id imx327_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) { .compatible = "sony,imx327" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) MODULE_DEVICE_TABLE(of, imx327_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static const struct i2c_device_id imx327_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) { "sony,imx327", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) static struct i2c_driver imx327_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .name = IMX327_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .pm = &imx327_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .of_match_table = of_match_ptr(imx327_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .probe = &imx327_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .remove = &imx327_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .id_table = imx327_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) return i2c_add_driver(&imx327_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) i2c_del_driver(&imx327_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) MODULE_DESCRIPTION("Sony imx327 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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