^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * imx323 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* 74.25Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX323_PIXEL_RATE (74250 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX323_XVCLK_FREQ 37125000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CHIP_ID 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX323_REG_CHIP_ID 0x0112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX323_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX323_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX323_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX323_REG_EXPOSURE 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX323_EXPOSURE_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX323_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX323_VTS_MAX 0x465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX323_REG_ANALOG_GAIN 0x301e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ANALOG_GAIN_MIN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ANALOG_GAIN_MAX 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ANALOG_GAIN_DEFAULT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX323_REG_VTS 0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX323_REG_ORIENTATION 0x0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX323_ORIENTATION_H 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX323_ORIENTATION_V 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX323_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX323_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX323_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* h_offs 35 v_offs 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PIX_FORMAT MEDIA_BUS_FMT_SBGGR10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX323_NAME "imx323"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct cam_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const struct cam_regulator imx323_regulator[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {"avdd", 2800000}, /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {"dovdd", 1800000}, /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {"dvdd", 1200000}, /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX323_NUM_SUPPLIES ARRAY_SIZE(imx323_regulator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct imx323_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct imx323 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct regulator_bulk_data supplies[IMX323_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct imx323_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define to_imx323(sd) container_of(sd, struct imx323, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Pclk 74.25Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * linelength 2200(0x44c * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * framelength 1125(0x465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * grabwindow_width 1920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * grabwindow_height 1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * dvp bt656 10bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct regval imx323_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0x0009, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0x0340, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0x0341, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x0342, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x0343, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x3000, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x3002, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0x3011, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x3013, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x3016, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x301a, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x301f, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x3021, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x3022, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x3027, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x302c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x302d, 0x48}, /* low 10bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x304f, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x3054, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x307a, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x307b, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x3117, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct imx323_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .width = 2200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .height = 1125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .exp_def = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .hts_def = 0x044c * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .vts_def = 0x0465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .reg_list = imx323_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const char * const imx323_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int imx323_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int imx323_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = imx323_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) IMX323_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int imx323_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int imx323_get_reso_dist(const struct imx323_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct imx323_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) imx323_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dist = imx323_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int imx323_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct imx323 *imx323 = to_imx323(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) const struct imx323_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mutex_lock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mode = imx323_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) fmt->format.code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mutex_unlock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) imx323->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) __v4l2_ctrl_modify_range(imx323->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) __v4l2_ctrl_modify_range(imx323->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) IMX323_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mutex_unlock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int imx323_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct imx323 *imx323 = to_imx323(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) const struct imx323_mode *mode = imx323->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) mutex_lock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) mutex_unlock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) fmt->format.code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) mutex_unlock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int imx323_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) code->code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int imx323_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (fse->code != PIX_FORMAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int imx323_enable_test_pattern(struct imx323 *imx323, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void imx323_get_module_inf(struct imx323 *imx323,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) strlcpy(inf->base.sensor, IMX323_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) strlcpy(inf->base.module, imx323->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) strlcpy(inf->base.lens, imx323->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static long imx323_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct imx323 *imx323 = to_imx323(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) imx323_get_module_inf(imx323, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) imx323_write_reg(imx323->client, IMX323_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) IMX323_REG_VALUE_08BIT, IMX323_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) imx323_write_reg(imx323->client, IMX323_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) IMX323_REG_VALUE_08BIT, IMX323_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case RKMODULE_GET_BT656_INTF_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) *(__u32 *)arg = BT656_SONY_RAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static long imx323_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) __u32 intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = imx323_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = imx323_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret = imx323_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case RKMODULE_GET_BT656_INTF_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) intf = BT656_SONY_RAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = copy_to_user(up, &intf, sizeof(intf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int __imx323_start_stream(struct imx323 *imx323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = imx323_write_array(imx323->client, imx323->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mutex_unlock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ret = v4l2_ctrl_handler_setup(&imx323->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) mutex_lock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return imx323_write_reg(imx323->client, IMX323_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) IMX323_REG_VALUE_08BIT, IMX323_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int __imx323_stop_stream(struct imx323 *imx323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return imx323_write_reg(imx323->client, IMX323_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) IMX323_REG_VALUE_08BIT, IMX323_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int imx323_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct imx323 *imx323 = to_imx323(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct i2c_client *client = imx323->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mutex_lock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (on == imx323->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ret = __imx323_start_stream(imx323);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) __imx323_stop_stream(imx323);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) imx323->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mutex_unlock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int imx323_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct imx323 *imx323 = to_imx323(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) const struct imx323_mode *mode = imx323->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) mutex_lock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mutex_unlock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int imx323_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct imx323 *imx323 = to_imx323(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct i2c_client *client = imx323->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) mutex_lock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (imx323->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) imx323->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) imx323->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mutex_unlock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static inline u32 imx323_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return DIV_ROUND_UP(cycles, IMX323_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int __imx323_power_on(struct imx323 *imx323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u32 i, delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct device *dev = &imx323->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = clk_set_rate(imx323->xvclk, IMX323_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dev_err(dev, "Failed to set xvclk rate (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) IMX323_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (clk_get_rate(imx323->xvclk) != IMX323_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_warn(dev, "xvclk mismatched, modes are based on %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) IMX323_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ret = clk_prepare_enable(imx323->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!IS_ERR(imx323->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) gpiod_set_value_cansleep(imx323->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) for (i = 0; i < IMX323_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) regulator_set_voltage(imx323->supplies[i].consumer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) imx323_regulator[i].val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) imx323_regulator[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret = regulator_bulk_enable(IMX323_NUM_SUPPLIES, imx323->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (!IS_ERR(imx323->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) gpiod_set_value_cansleep(imx323->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (!IS_ERR(imx323->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) gpiod_set_value_cansleep(imx323->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) delay_us = imx323_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) clk_disable_unprepare(imx323->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static void __imx323_power_off(struct imx323 *imx323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (!IS_ERR(imx323->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) gpiod_set_value_cansleep(imx323->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) clk_disable_unprepare(imx323->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (!IS_ERR(imx323->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) gpiod_set_value_cansleep(imx323->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) regulator_bulk_disable(IMX323_NUM_SUPPLIES, imx323->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static int imx323_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct imx323 *imx323 = to_imx323(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return __imx323_power_on(imx323);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int imx323_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct imx323 *imx323 = to_imx323(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) __imx323_power_off(imx323);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static int imx323_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct imx323 *imx323 = to_imx323(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) const struct imx323_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mutex_lock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) try_fmt->code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) mutex_unlock(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static int imx323_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) config->type = V4L2_MBUS_BT656;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) V4L2_MBUS_VSYNC_ACTIVE_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) V4L2_MBUS_PCLK_SAMPLE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int imx323_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (fie->code != PIX_FORMAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const struct dev_pm_ops imx323_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) SET_RUNTIME_PM_OPS(imx323_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) imx323_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static const struct v4l2_subdev_internal_ops imx323_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .open = imx323_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const struct v4l2_subdev_core_ops imx323_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .s_power = imx323_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .ioctl = imx323_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .compat_ioctl32 = imx323_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static const struct v4l2_subdev_video_ops imx323_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .s_stream = imx323_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .g_frame_interval = imx323_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static const struct v4l2_subdev_pad_ops imx323_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .enum_mbus_code = imx323_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .enum_frame_size = imx323_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .enum_frame_interval = imx323_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .get_fmt = imx323_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .set_fmt = imx323_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .get_mbus_config = imx323_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const struct v4l2_subdev_ops imx323_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .core = &imx323_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .video = &imx323_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .pad = &imx323_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int imx323_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct imx323 *imx323 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct imx323, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct i2c_client *client = imx323->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ret = imx323_write_reg(imx323->client, IMX323_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) IMX323_REG_VALUE_16BIT, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = imx323_write_reg(imx323->client, IMX323_REG_ANALOG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) IMX323_REG_VALUE_08BIT, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = imx323_write_reg(imx323->client, IMX323_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) IMX323_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ctrl->val + imx323->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = imx323_enable_test_pattern(imx323, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static const struct v4l2_ctrl_ops imx323_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .s_ctrl = imx323_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static int imx323_initialize_controls(struct imx323 *imx323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) const struct imx323_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) handler = &imx323->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) mode = imx323->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) handler->lock = &imx323->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) 0, IMX323_PIXEL_RATE, 1, IMX323_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) imx323->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (imx323->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) imx323->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) imx323->vblank = v4l2_ctrl_new_std(handler, &imx323_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) IMX323_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) exposure_max = mode->vts_def - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) imx323->exposure = v4l2_ctrl_new_std(handler, &imx323_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) V4L2_CID_EXPOSURE, IMX323_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) exposure_max, IMX323_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) imx323->anal_gain = v4l2_ctrl_new_std(handler, &imx323_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) imx323->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) &imx323_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ARRAY_SIZE(imx323_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) 0, 0, imx323_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) dev_err(&imx323->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) imx323->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static int imx323_check_sensor_id(struct imx323 *imx323,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct device *dev = &imx323->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ret = imx323_read_reg(client, IMX323_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) IMX323_REG_VALUE_08BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dev_err(dev, "Unexpected sensor id(%x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) dev_info(dev, "Detected IMX323 sensor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static int imx323_configure_regulators(struct imx323 *imx323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) for (i = 0; i < IMX323_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) imx323->supplies[i].supply =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) imx323_regulator[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return devm_regulator_bulk_get(&imx323->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) IMX323_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) imx323->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int imx323_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct imx323 *imx323;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) imx323 = devm_kzalloc(dev, sizeof(*imx323), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (!imx323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) &imx323->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) &imx323->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) &imx323->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) &imx323->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) imx323->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) imx323->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) imx323->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (IS_ERR(imx323->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) imx323->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (IS_ERR(imx323->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) imx323->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (IS_ERR(imx323->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ret = imx323_configure_regulators(imx323);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) mutex_init(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) sd = &imx323->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) v4l2_i2c_subdev_init(sd, client, &imx323_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ret = imx323_initialize_controls(imx323);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ret = __imx323_power_on(imx323);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ret = imx323_check_sensor_id(imx323, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) sd->internal_ops = &imx323_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) imx323->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ret = media_entity_pads_init(&sd->entity, 1, &imx323->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (strcmp(imx323->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) imx323->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) IMX323_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) __imx323_power_off(imx323);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) v4l2_ctrl_handler_free(&imx323->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) mutex_destroy(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static int imx323_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct imx323 *imx323 = to_imx323(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) v4l2_ctrl_handler_free(&imx323->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) mutex_destroy(&imx323->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) __imx323_power_off(imx323);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static const struct of_device_id imx323_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) { .compatible = "sony,imx323" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) MODULE_DEVICE_TABLE(of, imx323_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static const struct i2c_device_id imx323_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) { "sony,imx323", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static struct i2c_driver imx323_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .name = IMX323_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .pm = &imx323_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .of_match_table = of_match_ptr(imx323_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .probe = &imx323_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .remove = &imx323_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .id_table = imx323_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return i2c_add_driver(&imx323_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) i2c_del_driver(&imx323_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) MODULE_DESCRIPTION("Sony imx323 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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