^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * imx317 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 adjust exposue and gain control issues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X05 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * V0.0X01.0X06 add function g_mbus_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MIPI_FREQ 360000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX317_PIXEL_RATE (MIPI_FREQ * 2LL * 4LL / 10LL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX317_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CHIP_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX317_REG_CHIP_ID 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX317_REG_CTRL_MODE 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX317_MODE_SW_STANDBY 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX317_MODE_STREAMING 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX317_REG_EXPOSURE_H 0x300D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX317_REG_EXPOSURE_L 0x300C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX317_EXPOSURE_MIN 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX317_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX317_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX317_REG_GAIN_H 0x300B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX317_REG_GAIN_L 0x300A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX317_GAIN_H_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX317_GAIN_H_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX317_GAIN_L_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX317_GAIN_MIN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX317_GAIN_MAX (22U * IMX317_GAIN_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX317_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX317_GAIN_DEFAULT (20U * IMX317_GAIN_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX317_REG_VTS_H 0x30FA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX317_REG_VTS_M 0x30F9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX317_REG_VTS_L 0x30F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX317_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX317_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX317_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX317_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX317_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX317_NAME "imx317"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IMX317_MEDIA_BUS_FMT MEDIA_BUS_FMT_SRGGB10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const struct regval *imx317_global_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const char * const imx317_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX317_NUM_SUPPLIES ARRAY_SIZE(imx317_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct imx317_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct imx317 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct regulator_bulk_data supplies[IMX317_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct imx317_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define to_imx317(sd) container_of(sd, struct imx317, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct regval imx317_global_regs_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x3000, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x303E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x3120, 0xF0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x3121, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x3122, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x3123, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x3129, 0x9C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x312A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x312D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x3AC4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x310B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x30EE, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x3304, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x3306, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x3590, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x3686, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x3045, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x301A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x304C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x304D, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x331C, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x3502, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3529, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x352A, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x352B, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3538, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3539, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x3553, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x357D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x357F, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3581, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3583, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3587, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x35BB, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x35BC, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x35BD, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x35BE, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x35BF, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x366E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x366F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3670, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3671, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3004, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3005, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3006, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3007, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x300E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x300F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3037, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3038, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3039, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x303A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x303B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x30DD, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x30DE, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x30DF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x30E0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x30E1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x30E2, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x30F6, 0xE0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x30F7, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x30F8, 0xDA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x30F9, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x30FA, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3130, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3131, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3132, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3133, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3A54, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3A55, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3342, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3343, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3344, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3528, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3554, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3555, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3556, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3557, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3558, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3559, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x355A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x35BA, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x366A, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x366B, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x366C, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x366D, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x33A6, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x306B, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3A41, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3134, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3135, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3136, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3137, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3138, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3139, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x313A, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x313B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x313C, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x313D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x313E, 0xDF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x313F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3140, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3141, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3142, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3143, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x3144, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3145, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3A85, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3A86, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3A87, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3A43, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x303E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {REG_DELAY, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x30F4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3018, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x300a, 0x9c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x300b, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x300c, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x300d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x312e, 0x01}, //CSI_LANE_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3aa2, 0x01}, //PHYSICAL_LANE_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3001, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * mipi_datarate per lane 720Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * 2 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const struct regval imx317_1932x1094_regs_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3000, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3004, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3005, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3006, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3007, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* crop and scale*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3037, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3038, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x3039, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x303A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x303B, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x30E2, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x30F6, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x30F7, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x30F8, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x30F9, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x30FA, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3130, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3131, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3132, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3133, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x3a54, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x3a55, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x3344, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3554, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * mipi_datarate per lane 720Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * 2 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct regval imx317_3864x2174_regs_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3000, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x3004, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x3005, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3006, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3007, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* crop and scale*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x3037, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x3038, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3039, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x303A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x303B, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x30E2, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x30F6, 0xE0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x30F7, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x30F8, 0xDA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x30F9, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x30FA, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3130, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3131, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x3132, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x3133, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x3A54, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x3A55, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x3344, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x3554, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x3A43, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct regval imx317_global_regs_4lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x3000, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x303E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3120, 0xF0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3121, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3122, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3123, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3129, 0x9C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x312A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x312D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3AC4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x310B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x30EE, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x3304, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x3306, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x3590, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3686, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3045, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x301A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x304C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x304D, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x331C, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x3502, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x3529, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x352A, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x352B, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3538, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3539, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3553, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x357D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x357F, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x3581, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x3583, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x3587, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x35BB, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x35BC, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x35BD, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x35BE, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x35BF, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x366E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x366F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x3670, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x3671, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x3004, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x3005, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x3006, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x3007, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x300E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x300F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x3037, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x3038, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x3039, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x303A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x303B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x30DD, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x30DE, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x30DF, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x30E0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x30E1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x30E2, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x30F6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x30F7, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x30F8, 0xc6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x30F9, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x30FA, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3130, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3131, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3132, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3133, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3A54, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x3A55, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x3342, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x3343, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x3344, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x3345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x3528, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x3554, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x3555, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x3556, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3557, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3558, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x3559, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x355A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x35BA, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x366A, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x366B, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x366C, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x366D, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x33A6, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x306B, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x3A41, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x3134, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x3135, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x3136, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x3137, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x3138, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x3139, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x313A, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x313B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x313C, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x313D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x313E, 0xDF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x313F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x3140, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x3141, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x3142, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x3143, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x3144, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x3145, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x3A85, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x3A86, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x3A87, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x3A43, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x303E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {REG_DELAY, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x30F4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3018, 0xA2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x300a, 0x9c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x300b, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x300c, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x300d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x312e, 0x03}, //CSI_LANE_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x3aa2, 0x03}, //PHYSICAL_LANE_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x3001, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * mipi_datarate per lane 720Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * 4 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct regval imx317_1932x1094_regs_4lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x3000, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3004, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x3005, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x3006, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x3007, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* crop and scale*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x3037, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x3038, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x3039, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x303A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x303B, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x30E2, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x30F6, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x30F7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x30F8, 0xD0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x30F9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x30FA, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x3130, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x3131, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x3132, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x3133, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x3a54, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x3a55, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x3344, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x3554, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x3A43, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * mipi_datarate per lane 720Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * 4 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const struct regval imx317_3864x2174_regs_4lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x3000, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x3004, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x3005, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x3006, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x3007, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* crop and scale*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x3037, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x3038, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x3039, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x303A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x303B, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x30E2, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x30F6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x30F7, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x30F8, 0xc6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x30F9, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x30FA, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x3130, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x3131, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x3132, 0x7E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x3133, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x3A54, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x3A55, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x3344, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x3554, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x3A43, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const struct imx317_mode supported_modes_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .exp_def = 0x000C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .hts_def = 0x0276,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .vts_def = 0x0f0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .reg_list = imx317_1932x1094_regs_2lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .width = 3840,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .height = 2160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .denominator = 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .exp_def = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .hts_def = 0x04E0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .vts_def = 0x16DA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .reg_list = imx317_3864x2174_regs_2lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static const struct imx317_mode supported_modes_4lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .exp_def = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .hts_def = 0x011E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .vts_def = 0x20D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .reg_list = imx317_1932x1094_regs_4lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .width = 3840,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .height = 2160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .exp_def = 0x000C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .hts_def = 0x0210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .vts_def = 0x11C6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .reg_list = imx317_3864x2174_regs_4lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const struct imx317_mode *supported_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) MIPI_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static const char * const imx317_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int imx317_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int imx317_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (regs[i].addr == REG_DELAY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) usleep_range(regs[i].val, 2 * regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ret = imx317_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) IMX317_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static int imx317_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int imx317_get_reso_dist(const struct imx317_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static const struct imx317_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) imx317_find_best_fit(struct imx317 *imx317,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) for (i = 0; i < imx317->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dist = imx317_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static int imx317_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct imx317 *imx317 = to_imx317(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) const struct imx317_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mutex_lock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) mode = imx317_find_best_fit(imx317, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) fmt->format.code = IMX317_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) mutex_unlock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) imx317->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) h_blank = mode->hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) __v4l2_ctrl_modify_range(imx317->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) __v4l2_ctrl_modify_range(imx317->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) IMX317_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mutex_unlock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static int imx317_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct imx317 *imx317 = to_imx317(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) const struct imx317_mode *mode = imx317->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mutex_lock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) mutex_unlock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) fmt->format.code = IMX317_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) mutex_unlock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static int imx317_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) code->code = IMX317_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static int imx317_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct imx317 *imx317 = to_imx317(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (fse->index >= imx317->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (fse->code != IMX317_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int imx317_enable_test_pattern(struct imx317 *imx317, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int imx317_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct imx317 *imx317 = to_imx317(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) const struct imx317_mode *mode = imx317->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) mutex_lock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) mutex_unlock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static void imx317_get_module_inf(struct imx317 *imx317,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) strlcpy(inf->base.sensor, IMX317_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) strlcpy(inf->base.module, imx317->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) strlcpy(inf->base.lens, imx317->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static long imx317_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct imx317 *imx317 = to_imx317(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) imx317_get_module_inf(imx317, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) imx317_write_reg(imx317->client, IMX317_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) IMX317_REG_VALUE_08BIT, IMX317_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) imx317_write_reg(imx317->client, IMX317_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) IMX317_REG_VALUE_08BIT, IMX317_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static long imx317_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ret = imx317_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ret = imx317_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret = imx317_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static int __imx317_start_stream(struct imx317 *imx317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ret = imx317_write_array(imx317->client, imx317->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) mutex_unlock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ret = v4l2_ctrl_handler_setup(&imx317->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) mutex_lock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return imx317_write_reg(imx317->client, IMX317_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) IMX317_REG_VALUE_08BIT, IMX317_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static int __imx317_stop_stream(struct imx317 *imx317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return imx317_write_reg(imx317->client, IMX317_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) IMX317_REG_VALUE_08BIT, IMX317_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int imx317_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct imx317 *imx317 = to_imx317(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct i2c_client *client = imx317->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) imx317->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) imx317->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) DIV_ROUND_CLOSEST(imx317->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) imx317->cur_mode->max_fps.numerator));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) mutex_lock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (on == imx317->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = __imx317_start_stream(imx317);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) __imx317_stop_stream(imx317);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) imx317->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) mutex_unlock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static int imx317_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct imx317 *imx317 = to_imx317(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct i2c_client *client = imx317->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) mutex_lock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (imx317->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret = imx317_write_array(imx317->client, imx317_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) imx317->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) imx317->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) mutex_unlock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static inline u32 imx317_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return DIV_ROUND_UP(cycles, IMX317_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static int __imx317_power_on(struct imx317 *imx317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct device *dev = &imx317->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (!IS_ERR(imx317->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) gpiod_set_value_cansleep(imx317->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (!IS_ERR_OR_NULL(imx317->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ret = pinctrl_select_state(imx317->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) imx317->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ret = clk_set_rate(imx317->xvclk, IMX317_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (clk_get_rate(imx317->xvclk) != IMX317_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ret = clk_prepare_enable(imx317->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (!IS_ERR(imx317->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) gpiod_set_value_cansleep(imx317->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ret = regulator_bulk_enable(IMX317_NUM_SUPPLIES, imx317->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (!IS_ERR(imx317->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) gpiod_set_value_cansleep(imx317->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (!IS_ERR(imx317->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) gpiod_set_value_cansleep(imx317->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) delay_us = imx317_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) clk_disable_unprepare(imx317->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static void __imx317_power_off(struct imx317 *imx317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct device *dev = &imx317->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (!IS_ERR(imx317->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) gpiod_set_value_cansleep(imx317->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) clk_disable_unprepare(imx317->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (!IS_ERR(imx317->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) gpiod_set_value_cansleep(imx317->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (!IS_ERR_OR_NULL(imx317->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ret = pinctrl_select_state(imx317->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) imx317->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (!IS_ERR(imx317->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) gpiod_set_value_cansleep(imx317->power_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) regulator_bulk_disable(IMX317_NUM_SUPPLIES, imx317->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static int imx317_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) struct imx317 *imx317 = to_imx317(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return __imx317_power_on(imx317);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static int imx317_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct imx317 *imx317 = to_imx317(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) __imx317_power_off(imx317);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static int imx317_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) struct imx317 *imx317 = to_imx317(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) const struct imx317_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) mutex_lock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) try_fmt->code = IMX317_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) mutex_unlock(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static int imx317_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct imx317 *imx317 = to_imx317(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (fie->index >= imx317->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (fie->code != IMX317_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static int imx317_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct imx317 *imx317 = to_imx317(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) val = 1 << (imx317->lane_num - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static const struct dev_pm_ops imx317_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) SET_RUNTIME_PM_OPS(imx317_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) imx317_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static const struct v4l2_subdev_internal_ops imx317_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .open = imx317_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static const struct v4l2_subdev_core_ops imx317_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .s_power = imx317_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .ioctl = imx317_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .compat_ioctl32 = imx317_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static const struct v4l2_subdev_video_ops imx317_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .s_stream = imx317_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .g_frame_interval = imx317_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static const struct v4l2_subdev_pad_ops imx317_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .enum_mbus_code = imx317_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .enum_frame_size = imx317_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .enum_frame_interval = imx317_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .get_fmt = imx317_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .set_fmt = imx317_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .get_mbus_config = imx317_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static const struct v4l2_subdev_ops imx317_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .core = &imx317_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .video = &imx317_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .pad = &imx317_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static int imx317_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct imx317 *imx317 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct imx317, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct i2c_client *client = imx317->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) u32 vts_tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) max = imx317->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) __v4l2_ctrl_modify_range(imx317->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) imx317->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) imx317->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) imx317->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* calculate actual integration time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ret = imx317_read_reg(imx317->client, IMX317_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) IMX317_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) vts_tmp = (val & 0xff) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ret |= imx317_read_reg(imx317->client, IMX317_REG_VTS_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) IMX317_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) vts_tmp = vts_tmp | ((val & 0xff) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ret |= imx317_read_reg(imx317->client, IMX317_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) IMX317_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) vts_tmp = vts_tmp | (val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) ctrl->val = vts_tmp + 1 - ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ret = imx317_write_reg(imx317->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) IMX317_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) IMX317_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) (ctrl->val & 0xFF00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ret |= imx317_write_reg(imx317->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) IMX317_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) IMX317_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) ctrl->val & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (ctrl->val > IMX317_GAIN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ctrl->val = IMX317_GAIN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (ctrl->val < IMX317_GAIN_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ctrl->val = IMX317_GAIN_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) val = 2048 - (2048 * IMX317_GAIN_MIN) / ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ret = imx317_write_reg(imx317->client, IMX317_REG_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) IMX317_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) (val >> IMX317_GAIN_H_SHIFT) & IMX317_GAIN_H_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ret |= imx317_write_reg(imx317->client, IMX317_REG_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) IMX317_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) val & IMX317_GAIN_L_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) val = ctrl->val + imx317->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) ret = imx317_write_reg(imx317->client, IMX317_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) IMX317_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) (val & 0x0F0000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) ret |= imx317_write_reg(imx317->client, IMX317_REG_VTS_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) IMX317_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) (val & 0x00FF00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ret |= imx317_write_reg(imx317->client, IMX317_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) IMX317_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) val & 0x0000FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) ret = imx317_enable_test_pattern(imx317, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static const struct v4l2_ctrl_ops imx317_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .s_ctrl = imx317_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static int imx317_initialize_controls(struct imx317 *imx317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) const struct imx317_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) handler = &imx317->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) mode = imx317->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) handler->lock = &imx317->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) imx317->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) V4L2_CID_LINK_FREQ, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) 0, imx317->pixel_rate, 1, imx317->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) h_blank = mode->hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) imx317->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (imx317->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) imx317->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) imx317->vblank = v4l2_ctrl_new_std(handler, &imx317_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) IMX317_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) imx317->exposure = v4l2_ctrl_new_std(handler, &imx317_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) V4L2_CID_EXPOSURE, IMX317_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) exposure_max, IMX317_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) imx317->anal_gain = v4l2_ctrl_new_std(handler, &imx317_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) V4L2_CID_ANALOGUE_GAIN, IMX317_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) IMX317_GAIN_MAX, IMX317_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) IMX317_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) imx317->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) &imx317_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) ARRAY_SIZE(imx317_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) 0, 0, imx317_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) dev_err(&imx317->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) imx317->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static int imx317_check_sensor_id(struct imx317 *imx317,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct device *dev = &imx317->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ret = imx317_read_reg(client, IMX317_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) IMX317_REG_VALUE_08BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static int imx317_configure_regulators(struct imx317 *imx317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) for (i = 0; i < IMX317_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) imx317->supplies[i].supply = imx317_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return devm_regulator_bulk_get(&imx317->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) IMX317_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) imx317->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static int imx317_parse_of(struct imx317 *imx317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct device *dev = &imx317->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) fwnode = of_fwnode_handle(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) of_node_put(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (rval <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) dev_warn(dev, " Get mipi lane num failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) imx317->lane_num = rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (4 == imx317->lane_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) imx317->cur_mode = &supported_modes_4lane[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) supported_modes = supported_modes_4lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) imx317->cfg_num = ARRAY_SIZE(supported_modes_4lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) imx317_global_regs = imx317_global_regs_4lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) imx317->pixel_rate = MIPI_FREQ * 2U * imx317->lane_num / 10U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) imx317->lane_num, imx317->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) imx317->cur_mode = &supported_modes_2lane[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) supported_modes = supported_modes_2lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) imx317->cfg_num = ARRAY_SIZE(supported_modes_2lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) imx317_global_regs = imx317_global_regs_2lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /*pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) imx317->pixel_rate = MIPI_FREQ * 2U * (imx317->lane_num) / 10U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) dev_info(dev, "lane_num(%d) pixel_rate(%u), not supported yet!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) imx317->lane_num, imx317->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static int imx317_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) struct imx317 *imx317;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) imx317 = devm_kzalloc(dev, sizeof(*imx317), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (!imx317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) &imx317->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) &imx317->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) &imx317->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) &imx317->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) imx317->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) imx317->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) imx317->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (IS_ERR(imx317->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) imx317->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (IS_ERR(imx317->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) dev_warn(dev, "Failed to get power-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) imx317->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (IS_ERR(imx317->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) imx317->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (IS_ERR(imx317->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ret = imx317_parse_of(imx317);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) imx317->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (!IS_ERR(imx317->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) imx317->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) pinctrl_lookup_state(imx317->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (IS_ERR(imx317->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) imx317->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) pinctrl_lookup_state(imx317->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (IS_ERR(imx317->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) ret = imx317_configure_regulators(imx317);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) mutex_init(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) sd = &imx317->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) v4l2_i2c_subdev_init(sd, client, &imx317_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ret = imx317_initialize_controls(imx317);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ret = __imx317_power_on(imx317);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) ret = imx317_check_sensor_id(imx317, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) sd->internal_ops = &imx317_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) imx317->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) ret = media_entity_pads_init(&sd->entity, 1, &imx317->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (strcmp(imx317->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) imx317->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) IMX317_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) __imx317_power_off(imx317);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) v4l2_ctrl_handler_free(&imx317->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) mutex_destroy(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static int imx317_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) struct imx317 *imx317 = to_imx317(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) v4l2_ctrl_handler_free(&imx317->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) mutex_destroy(&imx317->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) __imx317_power_off(imx317);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static const struct of_device_id imx317_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) { .compatible = "sony,imx317" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) MODULE_DEVICE_TABLE(of, imx317_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static const struct i2c_device_id imx317_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) { "sony,imx317", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) static struct i2c_driver imx317_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .name = IMX317_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .pm = &imx317_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .of_match_table = of_match_ptr(imx317_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .probe = &imx317_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .remove = &imx317_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .id_table = imx317_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) return i2c_add_driver(&imx317_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) i2c_del_driver(&imx317_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) MODULE_DESCRIPTION("OmniVision imx317 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags