^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * imx307 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * v1.0x01.0x01 support lvds interface,include linear and hdr transmission via vipcap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * support mipi linear mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * v1.0x01.0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 1.fixed lvds output data offset, because lvds regards ob line as valid data output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2.support test pattern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * v1.0x01.0x03 update frame rate from 25fps to 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * v1.0x01.0x04 update max exposure and formula
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * shs1 = vts - (line + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * V0.0X01.0X05 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * V0.0X01.0X06 support lvds 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX307_LINK_FREQ_111M 111370000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX307_LINK_FREQ_222M 222750000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX307_2LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX307_4LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX307_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX307_PIXEL_RATE_NORMAL (IMX307_LINK_FREQ_111M * 2 / 10 * IMX307_4LANES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX307_PIXEL_RATE_HDR (IMX307_LINK_FREQ_222M * 2 / 10 * IMX307_4LANES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX307_XVCLK_FREQ 37125000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CHIP_ID 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX307_REG_CHIP_ID 0x301e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX307_REG_CTRL_MODE 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX307_MODE_SW_STANDBY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX307_MODE_STREAMING 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX307_REG_SHS1_H 0x3022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX307_REG_SHS1_M 0x3021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX307_REG_SHS1_L 0x3020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX307_REG_SHS2_H 0x3026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX307_REG_SHS2_M 0x3025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX307_REG_SHS2_L 0x3024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX307_REG_RHS1_H 0x3032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX307_REG_RHS1_M 0x3031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX307_REG_RHS1_L 0x3030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX307_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 16) & 0x0F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX307_FETCH_MID_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX307_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX307_EXPOSURE_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX307_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX307_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX307_GAIN_SWITCH_REG 0x3009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX307_REG_LF_GAIN 0x3014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX307_REG_SF_GAIN 0x30f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX307_GAIN_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX307_GAIN_MAX 0xee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX307_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX307_GAIN_DEFAULT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX307_GROUP_HOLD_REG 0x3001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX307_GROUP_HOLD_START 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IMX307_GROUP_HOLD_END 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define USED_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #ifdef USED_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX307_REG_TEST_PATTERN 0x308c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX307_TEST_PATTERN_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX307_REG_VTS_H 0x301a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX307_REG_VTS_M 0x3019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX307_REG_VTS_L 0x3018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX307_FETCH_HIGH_BYTE_VTS(VAL) (((VAL) >> 16) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX307_FETCH_MID_BYTE_VTS(VAL) (((VAL) >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX307_FETCH_LOW_BYTE_VTS(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX307_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX307_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX307_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static bool g_isHCG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX307_NAME "imx307"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX307_FLIP_REG 0x3007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MIRROR_BIT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define FLIP_BIT_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RHS1 0X0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const char * const imx307_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX307_NUM_SUPPLIES ARRAY_SIZE(imx307_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct imx307_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct rkmodule_lvds_cfg lvds_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct imx307 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct regulator_bulk_data supplies[IMX307_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct v4l2_ctrl *h_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct v4l2_ctrl *v_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #ifdef USED_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const struct imx307_mode *support_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 support_modes_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) const struct imx307_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct v4l2_fwnode_endpoint bus_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define to_imx307(sd) container_of(sd, struct imx307, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct regval imx307_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * lvds_datarate per lane 111Mbps 2 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct regval imx307_linear_1920x1080_30fps_lvds_2lane_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3003, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3007, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3009, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x300a, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3010, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3011, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3018, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3019, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x301c, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x301d, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3046, 0xD0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x304b, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x305c, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x305d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x305e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x305f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x309e, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x309f, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x311c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3128, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3129, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x313b, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x315e, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3164, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x317c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x31ec, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3480, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * max_framerate 15fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * lvds_datarate per lane 222Mbps 2 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct regval imx307_hdr2_1920x1080_lvds_2lane_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3003, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3007, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x3009, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x300a, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x300c, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3010, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3011, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3014, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3018, 0x65},/* VMAX L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3019, 0x04},/* VMAX M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x301c, 0x30},/* HMAX L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x301d, 0x11},/* HMAX H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3020, 0x02},//hdr+ shs1 l short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x3021, 0x00},//hdr+ shs1 m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3024, 0x49},//hdr+ shs2 l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3025, 0x04},//hdr+ shs2 m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3030, RHS1},//hdr+ IMX327_RHS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3031, 0x00},//hdr+IMX327_RHS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3045, 0x03},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3046, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x305c, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x305d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x305e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x305f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x309e, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x309f, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x30d2, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x30d7, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3106, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x311c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x3128, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3129, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x313b, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x315e, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3164, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x317c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x31ec, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3480, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x31a0, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x31a1, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x303c, 0x04},//Y offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x303d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x303e, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x303f, 0x04},//height
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x303A, 0x08},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3010, 0x61},//hdr+ gain 1frame FPGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3014, 0x00},//hdr+ gain 1frame long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x30F0, 0x64},//hdr+ gain 2frame FPGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x30f2, 0x00},//hdr+ gain 2frame short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x304B, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * lvds_datarate per lane 222.75Mbps 4 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct regval imx307_linear_1920x1080_30fps_lvds_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x3003, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x3007, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3009, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x300a, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x3010, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3011, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3018, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x3019, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x301c, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x301d, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3046, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x304b, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x305c, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x305d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x305e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x305f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x309e, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x309f, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x311c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x3128, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3129, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x313b, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x315e, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x3164, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x317c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x31ec, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x3480, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * max_framerate 60fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * lvds_datarate per lane 445.5Mbps 4 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct regval imx307_linear_1920x1080_60fps_lvds_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3003, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x3007, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x3009, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x300a, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x3010, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x3011, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3018, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3019, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x301c, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x301d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x3046, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x304b, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x305c, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x305d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x305e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x305f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x309e, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x309f, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x311c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x3128, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3129, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x313b, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x315e, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x3164, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x317c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x31ec, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x3480, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * lvds_datarate per lane 445.5Mbps 4 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const struct regval imx307_hdr2_1920x1080_lvds_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x3003, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x3007, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x3009, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x300a, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x300c, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x3011, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x3018, 0xc4},/* VMAX L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x3019, 0x04},/* VMAX M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x301c, 0xec},/* HMAX L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x301d, 0x07},/* HMAX H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3020, 0x02},//hdr+ shs1 l short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x3021, 0x00},//hdr+ shs1 m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x3024, 0xc9},//hdr+ shs2 l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3025, 0x07},//hdr+ shs2 m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3030, 0xe1},//hdr+ IMX327_RHS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3031, 0x00},//hdr+IMX327_RHS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3045, 0x03},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3046, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x304b, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x305c, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x305d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x305e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x305f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x309e, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x309f, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x30d2, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x30d7, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3106, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3129, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x313b, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x315e, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x3164, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x317c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x31ec, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x3414, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x3415, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x3480, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x31a0, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x31a1, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x303c, 0x04},//Y offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x303d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x303e, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x303f, 0x04},//height
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x303A, 0x08},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x3010, 0x61},//hdr+ gain 1frame FPGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x3014, 0x00},//hdr+ gain 1frame long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x30F0, 0x64},//hdr+ gain 2frame FPGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x30f2, 0x00},//hdr+ gain 2frame short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * mipi_datarate per lane 222.75Mbps 4 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const struct regval imx307_linear_1920x1080_mipi_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x3003, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x3007, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3009, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x300A, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x3010, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x3011, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x3018, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x3019, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x301C, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x301D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x3046, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x304B, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x305C, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x305D, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x305E, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x305F, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x309E, 0x4A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x309F, 0x4A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x311c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x3128, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x3129, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x313B, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x315E, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x3164, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x317C, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x31EC, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x3405, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x3407, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x3414, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x3418, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x3419, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x3441, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x3442, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x3443, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x3444, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x3445, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x3446, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x3447, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x3448, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x3449, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x344A, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x344B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x344C, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x344D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x344E, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x344F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x3450, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x3451, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x3452, 0x0F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x3453, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x3454, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x3455, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x3472, 0x9c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x3473, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x3480, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * Xclk 37.125Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * mipi_datarate per lane 445.5Mbps 4 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct regval imx307_hdr2_1920x1080_mipi_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x3003, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x3000, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x3002, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x3007, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x3009, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x300a, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x300c, 0x11}, //hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x3011, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x3018, 0xc4},/* VMAX L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x3019, 0x04},/* VMAX M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x301a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x301c, 0xEc},/* HMAX L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x301d, 0x07},/* HMAX H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x3045, 0x05},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x3046, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x304b, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x305c, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x305d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x305e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x305f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x309e, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x309f, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x30d2, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x30d7, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x3106, 0x11},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x3129, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x313b, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x315e, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x3164, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x317c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x31ec, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x3405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x3407, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x3414, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x3415, 0x00},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x3418, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x3419, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x3441, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x3442, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x3443, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x3444, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x3445, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x3446, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x3447, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x3448, 0x37},//37?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x3449, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x344a, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x344b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x344c, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x344d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x344e, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x344f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x3450, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x3451, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x3452, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x3453, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x3454, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x3455, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x3472, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x3473, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x347b, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x3480, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x31a0, 0xb4},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x31a1, 0x02},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x3020, 0x02},//hdr+ shs1 l short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x3021, 0x00},//hdr+ shs1 m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x3022, 0x00},//hdr+ shs1 h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x3030, 0xe1},//hdr+ IMX307_RHS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x3031, 0x00},//hdr+IMX307_RHS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x3032, 0x00},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x31A0, 0xe8},//hdr+ HBLANK1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x31A1, 0x01},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x303c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x303d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x303e, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {0x303f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0x303A, 0x08},//hdr+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x3024, 0xc9},//hdr+ shs2 l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x3025, 0x06},//hdr+ shs2 m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x3026, 0x00},//hdr+ shs2 h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x3010, 0x61},//hdr+ gain 1frame FPGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x3014, 0x00},//hdr+ gain 1frame long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x30F0, 0x64},//hdr+ gain 2frame FPGC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x30f2, 0x00},//hdr+ gain 2frame short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * The width and height must be configured to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * the same as the current output resolution of the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * The input width of the isp needs to be 16 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * The input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * If the width or height does not meet the alignment rules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * you can configure the cropping parameters with the following function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * crop out the appropriate resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * struct v4l2_subdev_pad_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * .get_selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const struct imx307_mode lvds_2lane_supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .width = 1948,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .height = 1110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .exp_def = 0x03fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .hts_def = 0x1130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .vts_def = 0x0465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .reg_list = imx307_linear_1920x1080_30fps_lvds_2lane_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .lanes = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .lvds_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .mode = LS_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .frm_sync_code[LVDS_CODE_GRP_LINEAR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .odd_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .sav = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .eav = 0x274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .sav = 0x2ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .eav = 0x2d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .width = 1948,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .height = 1098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .denominator = 150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .exp_def = 0x0473,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .hts_def = 0x07ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .vts_def = 0x04c4 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .reg_list = imx307_hdr2_1920x1080_lvds_2lane_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .lanes = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .lvds_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .mode = SONY_DOL_HDR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .frm_sync_code[LVDS_CODE_GRP_LONG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .odd_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .sav = 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .eav = 0x075,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .sav = 0x0ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .eav = 0x0d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .even_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .sav = 0x101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .eav = 0x175,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .sav = 0x1ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .eav = 0x1d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .frm_sync_code[LVDS_CODE_GRP_SHORT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .odd_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .sav = 0x002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .eav = 0x076,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .sav = 0x0ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .eav = 0x0d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .even_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .sav = 0x102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .eav = 0x176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .sav = 0x1ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .eav = 0x1d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static const struct imx307_mode lvds_supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .width = 1948,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .height = 1110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .exp_def = 0x03fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .hts_def = 0x0889,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .vts_def = 0x0465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .reg_list = imx307_linear_1920x1080_60fps_lvds_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .lvds_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .mode = LS_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .frm_sync_code[LVDS_CODE_GRP_LINEAR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .odd_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .sav = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .eav = 0x274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .sav = 0x2ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .eav = 0x2d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .width = 1948,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .height = 1110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .exp_def = 0x03fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .hts_def = 0x1130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .vts_def = 0x0465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .reg_list = imx307_linear_1920x1080_30fps_lvds_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .lvds_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .mode = LS_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .frm_sync_code[LVDS_CODE_GRP_LINEAR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .odd_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .sav = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .eav = 0x274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .sav = 0x2ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .eav = 0x2d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .width = 1948,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .height = 1098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .exp_def = 0x0473,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .hts_def = 0x07ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .vts_def = 0x04c4 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .reg_list = imx307_hdr2_1920x1080_lvds_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .lvds_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .mode = SONY_DOL_HDR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .frm_sync_code[LVDS_CODE_GRP_LONG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .odd_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .sav = 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .eav = 0x075,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .sav = 0x0ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .eav = 0x0d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .even_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .sav = 0x101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .eav = 0x175,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .sav = 0x1ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .eav = 0x1d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .frm_sync_code[LVDS_CODE_GRP_SHORT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .odd_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .sav = 0x002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .eav = 0x076,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .sav = 0x0ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .eav = 0x0d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .even_sync_code = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .act = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .sav = 0x102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .eav = 0x176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .blk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .sav = 0x1ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .eav = 0x1d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static const struct imx307_mode mipi_supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .width = 1948,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .height = 1097,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .exp_def = 0x03fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .hts_def = 0x1130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .vts_def = 0x0465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .reg_list = imx307_linear_1920x1080_mipi_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .width = 1952,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .height = 1089,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .exp_def = 0x0473,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .hts_def = 0x07ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .vts_def = 0x04c4 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .reg_list = imx307_hdr2_1920x1080_mipi_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .lanes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) IMX307_LINK_FREQ_111M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) IMX307_LINK_FREQ_222M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #ifdef USED_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const char * const imx307_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) "Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) "Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) "Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) "Bar Type 4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) "Bar Type 5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) "Bar Type 6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) "Bar Type 7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) "Bar Type 8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) "Bar Type 9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) "Bar Type 10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) "Bar Type 11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) "Bar Type 12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) "Bar Type 13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) "Bar Type 14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) "Bar Type 15"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static int imx307_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static int imx307_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (unlikely(regs[i].addr == REG_DELAY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) usleep_range(regs[i].val * 1000, regs[i].val * 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ret = imx307_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static int imx307_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static int imx307_get_reso_dist(const struct imx307_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static const struct imx307_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) imx307_find_best_fit(struct imx307 *imx307, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) for (i = 0; i < imx307->support_modes_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dist = imx307_get_reso_dist(&imx307->support_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return &imx307->support_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static int imx307_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) const struct imx307_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) s32 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) s64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) mutex_lock(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) mode = imx307_find_best_fit(imx307, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) mutex_unlock(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) imx307->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) __v4l2_ctrl_modify_range(imx307->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) __v4l2_ctrl_modify_range(imx307->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) IMX307_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) dst_link_freq = mode->freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dst_pixel_rate = (u32)link_freq_menu_items[mode->freq_idx] / mode->bpp * 2 * mode->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) __v4l2_ctrl_s_ctrl_int64(imx307->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) __v4l2_ctrl_s_ctrl(imx307->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) imx307->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) mutex_unlock(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static int imx307_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) const struct imx307_mode *mode = imx307->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) mutex_lock(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) mutex_unlock(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) mutex_unlock(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static int imx307_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) const struct imx307_mode *mode = imx307->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) code->code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static int imx307_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (fse->index >= imx307->support_modes_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (fse->code != imx307->support_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) fse->min_width = imx307->support_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) fse->max_width = imx307->support_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) fse->max_height = imx307->support_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) fse->min_height = imx307->support_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #ifdef USED_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static int imx307_enable_test_pattern(struct imx307 *imx307, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) imx307_read_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) IMX307_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (pattern) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) val = ((pattern - 1) << 4) | IMX307_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) 0x300a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) 0x300e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) val &= ~IMX307_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) 0x300a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) 0x300e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) IMX307_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static int imx307_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) const struct imx307_mode *mode = imx307->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) mutex_lock(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) mutex_unlock(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static int imx307_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) val = 1 << (imx307->cur_mode->lanes - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) config->type = imx307->bus_cfg.bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static int imx307_set_hdrae(struct imx307 *imx307,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) u32 l_gain, m_gain, s_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) u32 shs1, shs2, rhs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) u32 gain_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) u8 cg_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) u32 fsc = imx307->cur_vts;//The HDR mode vts is double by default to workaround T-line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (!imx307->has_init_exp && !imx307->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) imx307->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) imx307->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) dev_dbg(&imx307->client->dev, "imx307 don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) l_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) m_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) s_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (imx307->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) //2 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) l_gain = m_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) cg_mode = ae->middle_cg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dev_dbg(&imx307->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) "rev exp req: L_time=%d, gain=%d, S_time=%d, gain=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) l_exp_time, l_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) s_exp_time, s_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ret = imx307_read_reg(imx307->client, IMX307_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) IMX307_REG_VALUE_08BIT, &gain_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (!g_isHCG && cg_mode == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) gain_switch |= 0x0110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) g_isHCG = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) } else if (g_isHCG && cg_mode == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) gain_switch &= 0xef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) gain_switch |= 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) g_isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) //long exposure and short exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (imx307->cur_mode->lanes == 2 && imx307->bus_cfg.bus_type == V4L2_MBUS_CCP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) rhs1 = RHS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) rhs1 = 0xe1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) shs1 = rhs1 - s_exp_time - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) shs2 = fsc - l_exp_time - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (shs1 < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) shs1 = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (shs2 < (rhs1 + 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) shs2 = rhs1 + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) else if (shs2 > (fsc - 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) shs2 = fsc - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ret |= imx307_write_reg(imx307->client, IMX307_REG_SHS1_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) IMX307_FETCH_LOW_BYTE_EXP(shs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ret |= imx307_write_reg(imx307->client, IMX307_REG_SHS1_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) IMX307_FETCH_MID_BYTE_EXP(shs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) ret |= imx307_write_reg(imx307->client, IMX307_REG_SHS1_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) IMX307_FETCH_HIGH_BYTE_EXP(shs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ret |= imx307_write_reg(imx307->client, IMX307_REG_SHS2_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) IMX307_FETCH_LOW_BYTE_EXP(shs2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) ret |= imx307_write_reg(imx307->client, IMX307_REG_SHS2_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) IMX307_FETCH_MID_BYTE_EXP(shs2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ret |= imx307_write_reg(imx307->client, IMX307_REG_SHS2_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) IMX307_FETCH_HIGH_BYTE_EXP(shs2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ret |= imx307_write_reg(imx307->client, IMX307_REG_LF_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) l_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ret |= imx307_write_reg(imx307->client, IMX307_REG_SF_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) s_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (gain_switch & 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) ret |= imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) IMX307_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) IMX307_GROUP_HOLD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ret |= imx307_write_reg(imx307->client, IMX307_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) IMX307_REG_VALUE_08BIT, gain_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) ret |= imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) IMX307_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) IMX307_GROUP_HOLD_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) dev_dbg(&imx307->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) "set l_gain:0x%x s_gain:0x%x shs2:0x%x shs1:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) l_gain, s_gain, shs2, shs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static void imx307_get_module_inf(struct imx307 *imx307,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) strlcpy(inf->base.sensor, IMX307_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) strlcpy(inf->base.module, imx307->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) strlcpy(inf->base.lens, imx307->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static int imx307_set_conversion_gain(struct imx307 *imx307, u32 *cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) struct i2c_client *client = imx307->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) int cur_cg = *cg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) u32 gain_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ret = imx307_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) IMX307_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) &gain_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (g_isHCG && cur_cg == GAIN_MODE_LCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) gain_switch &= 0xef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) gain_switch |= 0x0100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) g_isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) } else if (!g_isHCG && cur_cg == GAIN_MODE_HCG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) gain_switch |= 0x0110;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) g_isHCG = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (gain_switch & 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ret |= imx307_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) IMX307_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) IMX307_GROUP_HOLD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) ret |= imx307_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) IMX307_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) gain_switch & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ret |= imx307_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) IMX307_GROUP_HOLD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) IMX307_GROUP_HOLD_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) //ag: echo 0 > /sys/devices/platform/ff510000.i2c/i2c-1/1-0037/cam_s_cg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static ssize_t set_conversion_gain_status(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) ret = kstrtoint(buf, 0, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (!ret && status >= 0 && status < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) imx307_set_conversion_gain(imx307, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) dev_err(dev, "input 0 for LCG, 1 for HCG, cur %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static struct device_attribute attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) __ATTR(cam_s_cg, S_IWUSR, NULL, set_conversion_gain_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static int add_sysfs_interfaces(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) for (i = 0; i < ARRAY_SIZE(attributes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (device_create_file(dev, attributes + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) goto undo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) undo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) for (i--; i >= 0 ; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) device_remove_file(dev, attributes + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) dev_err(dev, "%s: failed to create sysfs interface\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static long imx307_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct rkmodule_lvds_cfg *lvds_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) const struct imx307_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) s64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) s32 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) imx307_get_module_inf(imx307, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ret = imx307_set_hdrae(imx307, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (imx307->cur_mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) hdr->esp.mode = HDR_ID_CODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) hdr->hdr_mode = imx307->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) for (i = 0; i < imx307->support_modes_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (imx307->support_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) imx307->cur_mode = &imx307->support_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (i == imx307->support_modes_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) dev_err(&imx307->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) "not find hdr mode:%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) hdr->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) mode = imx307->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) w = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) h = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) __v4l2_ctrl_modify_range(imx307->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) __v4l2_ctrl_modify_range(imx307->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) IMX307_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) dst_link_freq = mode->freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) dst_pixel_rate = (u32)link_freq_menu_items[mode->freq_idx] / mode->bpp * 2 * mode->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) __v4l2_ctrl_s_ctrl_int64(imx307->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) __v4l2_ctrl_s_ctrl(imx307->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) imx307->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) ret = imx307_set_conversion_gain(imx307, (u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) case RKMODULE_GET_LVDS_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) lvds_cfg = (struct rkmodule_lvds_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (imx307->bus_cfg.bus_type == V4L2_MBUS_CCP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) memcpy(lvds_cfg, &imx307->cur_mode->lvds_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) sizeof(struct rkmodule_lvds_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) ret = imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) IMX307_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ret = imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) IMX307_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static long imx307_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) u32 cg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ret = imx307_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ret = imx307_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) ret = imx307_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) ret = imx307_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) ret = imx307_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) ret = copy_from_user(&cg, up, sizeof(cg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) ret = imx307_ioctl(sd, cmd, &cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) ret = imx307_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) static int imx307_init_conversion_gain(struct imx307 *imx307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) struct i2c_client *client = imx307->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) ret = imx307_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) IMX307_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) val &= 0xef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) ret |= imx307_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) IMX307_GAIN_SWITCH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) g_isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static int __imx307_start_stream(struct imx307 *imx307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) ret = imx307_write_array(imx307->client, imx307->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ret = imx307_init_conversion_gain(imx307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) ret = __v4l2_ctrl_handler_setup(&imx307->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (imx307->has_init_exp && imx307->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) ret = imx307_ioctl(&imx307->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) &imx307->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) dev_err(&imx307->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) ret = imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) IMX307_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) static int __imx307_stop_stream(struct imx307 *imx307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) IMX307_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) static int imx307_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) struct i2c_client *client = imx307->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) mutex_lock(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if (on == imx307->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) ret = __imx307_start_stream(imx307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) __imx307_stop_stream(imx307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) imx307->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) mutex_unlock(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static int imx307_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) struct i2c_client *client = imx307->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) mutex_lock(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) if (imx307->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) ret = imx307_write_array(imx307->client, imx307_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) imx307->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) imx307->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) mutex_unlock(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static inline u32 imx307_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return DIV_ROUND_UP(cycles, IMX307_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static int __imx307_power_on(struct imx307 *imx307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) struct device *dev = &imx307->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (!IS_ERR_OR_NULL(imx307->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) ret = pinctrl_select_state(imx307->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) imx307->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) ret = clk_set_rate(imx307->xvclk, IMX307_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) dev_warn(dev, "Failed to set xvclk rate (37.125M Hz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (clk_get_rate(imx307->xvclk) != IMX307_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) dev_warn(dev, "xvclk mismatched,based on 24M Hz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) ret = clk_prepare_enable(imx307->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) ret = regulator_bulk_enable(IMX307_NUM_SUPPLIES, imx307->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (!IS_ERR(imx307->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) gpiod_set_value_cansleep(imx307->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (!IS_ERR(imx307->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) gpiod_set_value_cansleep(imx307->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) if (!IS_ERR(imx307->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) gpiod_set_value_cansleep(imx307->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) delay_us = imx307_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) clk_disable_unprepare(imx307->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static void __imx307_power_off(struct imx307 *imx307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) struct device *dev = &imx307->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (!IS_ERR(imx307->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) gpiod_set_value_cansleep(imx307->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) clk_disable_unprepare(imx307->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) if (!IS_ERR(imx307->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) gpiod_set_value_cansleep(imx307->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if (!IS_ERR_OR_NULL(imx307->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) ret = pinctrl_select_state(imx307->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) imx307->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) regulator_bulk_disable(IMX307_NUM_SUPPLIES, imx307->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) static int imx307_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) return __imx307_power_on(imx307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static int imx307_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) __imx307_power_off(imx307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) static int imx307_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) const struct imx307_mode *def_mode = &imx307->support_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) mutex_lock(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) mutex_unlock(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) static int imx307_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (fie->index >= imx307->support_modes_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) fie->code = imx307->support_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) fie->width = imx307->support_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) fie->height = imx307->support_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) fie->interval = imx307->support_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) fie->reserved[0] = imx307->support_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) #define DST_WIDTH 1920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #define DST_HEIGHT 1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) * The resolution of the driver configuration needs to be exactly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) * the same as the current output resolution of the sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) * the input width of the isp needs to be 16 aligned,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) * the input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) * Can be cropped to standard resolution by this function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) * otherwise it will crop out strange resolution according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) * to the alignment rules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static int imx307_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) sel->r.left = CROP_START(imx307->cur_mode->width, DST_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) sel->r.width = DST_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (imx307->bus_cfg.bus_type == V4L2_MBUS_CCP2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (imx307->cur_mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) sel->r.top = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) sel->r.top = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) sel->r.top = CROP_START(imx307->cur_mode->height, DST_HEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) sel->r.height = DST_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static const struct dev_pm_ops imx307_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) SET_RUNTIME_PM_OPS(imx307_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) imx307_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static const struct v4l2_subdev_internal_ops imx307_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .open = imx307_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) static const struct v4l2_subdev_core_ops imx307_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .s_power = imx307_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .ioctl = imx307_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .compat_ioctl32 = imx307_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static const struct v4l2_subdev_video_ops imx307_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .s_stream = imx307_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .g_frame_interval = imx307_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static const struct v4l2_subdev_pad_ops imx307_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .enum_mbus_code = imx307_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .enum_frame_size = imx307_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .enum_frame_interval = imx307_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .get_fmt = imx307_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .set_fmt = imx307_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .get_selection = imx307_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .get_mbus_config = imx307_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static const struct v4l2_subdev_ops imx307_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .core = &imx307_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .video = &imx307_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .pad = &imx307_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) static int imx307_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) struct imx307 *imx307 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) struct imx307, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) struct i2c_client *client = imx307->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) u32 shs1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) u32 vts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) max = imx307->cur_mode->height + ctrl->val - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) __v4l2_ctrl_modify_range(imx307->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) imx307->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) imx307->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) imx307->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) if (imx307->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) shs1 = imx307->cur_vts - (ctrl->val + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) ret = imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) IMX307_REG_SHS1_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) IMX307_FETCH_HIGH_BYTE_EXP(shs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ret |= imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) IMX307_REG_SHS1_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) IMX307_FETCH_MID_BYTE_EXP(shs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) ret |= imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) IMX307_REG_SHS1_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) IMX307_FETCH_LOW_BYTE_EXP(shs1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) dev_dbg(&client->dev, "set exposure 0x%x, cur_vts 0x%x,shs1 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) ctrl->val, imx307->cur_vts, shs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) if (imx307->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) ret = imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) IMX307_REG_LF_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) dev_dbg(&client->dev, "set analog gain 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) vts = ctrl->val + imx307->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) imx307->cur_vts = vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (imx307->cur_mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) vts /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) ret = imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) IMX307_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) IMX307_FETCH_HIGH_BYTE_VTS(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) ret |= imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) IMX307_REG_VTS_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) IMX307_FETCH_MID_BYTE_VTS(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) ret |= imx307_write_reg(imx307->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) IMX307_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) IMX307_FETCH_LOW_BYTE_VTS(vts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) dev_dbg(&client->dev, "set vts 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) vts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) #ifdef USED_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) ret = imx307_enable_test_pattern(imx307, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) ret = imx307_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) IMX307_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) val |= MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) val &= ~MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) ret |= imx307_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) IMX307_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) imx307->flip = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) ret = imx307_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) IMX307_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) val |= FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) val &= ~FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) ret |= imx307_write_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) IMX307_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) IMX307_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) imx307->flip = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) static const struct v4l2_ctrl_ops imx307_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .s_ctrl = imx307_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) static int imx307_initialize_controls(struct imx307 *imx307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) const struct imx307_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) s32 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) s64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) handler = &imx307->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) mode = imx307->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) handler->lock = &imx307->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) imx307->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) 1, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) dst_link_freq = mode->freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) dst_pixel_rate = (u32)link_freq_menu_items[mode->freq_idx] / mode->bpp * 2 * mode->lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) __v4l2_ctrl_s_ctrl(imx307->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) imx307->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) 0, IMX307_PIXEL_RATE_HDR, 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) imx307->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (imx307->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) imx307->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) imx307->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) imx307->vblank = v4l2_ctrl_new_std(handler, &imx307_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) IMX307_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) imx307->exposure = v4l2_ctrl_new_std(handler, &imx307_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) V4L2_CID_EXPOSURE, IMX307_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) exposure_max, IMX307_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) imx307->anal_gain = v4l2_ctrl_new_std(handler, &imx307_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) V4L2_CID_ANALOGUE_GAIN, IMX307_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) IMX307_GAIN_MAX, IMX307_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) IMX307_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) #ifdef USED_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) imx307->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) &imx307_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) ARRAY_SIZE(imx307_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) 0, 0, imx307_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) imx307->h_flip = v4l2_ctrl_new_std(handler, &imx307_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) imx307->v_flip = v4l2_ctrl_new_std(handler, &imx307_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) imx307->flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) dev_err(&imx307->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) imx307->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) imx307->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) static int imx307_check_sensor_id(struct imx307 *imx307,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) struct device *dev = &imx307->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) ret = imx307_read_reg(client, IMX307_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) IMX307_REG_VALUE_08BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) static int imx307_configure_regulators(struct imx307 *imx307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) for (i = 0; i < IMX307_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) imx307->supplies[i].supply = imx307_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) return devm_regulator_bulk_get(&imx307->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) IMX307_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) imx307->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) static int imx307_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) struct imx307 *imx307;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) imx307 = devm_kzalloc(dev, sizeof(*imx307), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (!imx307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) &imx307->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) &imx307->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) &imx307->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) &imx307->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) &imx307->bus_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) dev_warn(dev, "could not get bus config!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) if (imx307->bus_cfg.bus_type == V4L2_MBUS_CCP2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) if (imx307->bus_cfg.bus.mipi_csi1.data_lane == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) imx307->support_modes = lvds_2lane_supported_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) imx307->support_modes_num = ARRAY_SIZE(lvds_2lane_supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) } else if (imx307->bus_cfg.bus.mipi_csi1.data_lane == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) imx307->support_modes = lvds_supported_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) imx307->support_modes_num = ARRAY_SIZE(lvds_supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) dev_err(dev, "lvds lanes err!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) imx307->support_modes = mipi_supported_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) imx307->support_modes_num = ARRAY_SIZE(mipi_supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) imx307->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) imx307->cur_mode = &imx307->support_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) imx307->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) if (IS_ERR(imx307->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) imx307->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) if (IS_ERR(imx307->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) imx307->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) if (IS_ERR(imx307->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) ret = imx307_configure_regulators(imx307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) imx307->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) if (!IS_ERR(imx307->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) imx307->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) pinctrl_lookup_state(imx307->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) if (IS_ERR(imx307->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) imx307->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) pinctrl_lookup_state(imx307->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) if (IS_ERR(imx307->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) mutex_init(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) sd = &imx307->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) v4l2_i2c_subdev_init(sd, client, &imx307_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) ret = imx307_initialize_controls(imx307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) ret = __imx307_power_on(imx307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) ret = imx307_check_sensor_id(imx307, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) dev_err(dev, "set the video v4l2 subdev api\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) sd->internal_ops = &imx307_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) dev_err(dev, "set the media controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) imx307->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) ret = media_entity_pads_init(&sd->entity, 1, &imx307->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) if (strcmp(imx307->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) imx307->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) IMX307_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) g_isHCG = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) add_sysfs_interfaces(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) dev_err(dev, "v4l2 async register subdev success\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) __imx307_power_off(imx307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) v4l2_ctrl_handler_free(&imx307->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) mutex_destroy(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) static int imx307_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) struct imx307 *imx307 = to_imx307(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) v4l2_ctrl_handler_free(&imx307->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) mutex_destroy(&imx307->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) __imx307_power_off(imx307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) static const struct of_device_id imx307_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) { .compatible = "sony,imx307" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) MODULE_DEVICE_TABLE(of, imx307_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) static const struct i2c_device_id imx307_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) { "sony,imx307", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) static struct i2c_driver imx307_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .name = IMX307_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .pm = &imx307_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .of_match_table = of_match_ptr(imx307_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .probe = &imx307_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .remove = &imx307_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .id_table = imx307_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) return i2c_add_driver(&imx307_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) i2c_del_driver(&imx307_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) MODULE_DESCRIPTION("Sony imx307 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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