^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Sony IMX290 CMOS Image Sensor Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 FRAMOS GmbH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2019 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX290_STANDBY 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX290_REGHOLD 0x3001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX290_XMSTA 0x3002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX290_FR_FDG_SEL 0x3009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX290_BLKLEVEL_LOW 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX290_BLKLEVEL_HIGH 0x300b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX290_GAIN 0x3014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX290_HMAX_LOW 0x301c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX290_HMAX_HIGH 0x301d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX290_PGCTRL 0x308c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX290_PHY_LANE_NUM 0x3407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX290_CSI_LANE_MODE 0x3443
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX290_PGCTRL_REGEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX290_PGCTRL_THRU BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX290_PGCTRL_MODE(n) ((n) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const char * const imx290_supply_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "vdda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "vddd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "vdddo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX290_NUM_SUPPLIES ARRAY_SIZE(imx290_supply_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct imx290_regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct imx290_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 hmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 link_freq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const struct imx290_regval *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct imx290 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk *xclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 nlanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct v4l2_mbus_framefmt current_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const struct imx290_mode *current_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct gpio_desc *rst_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct v4l2_ctrl_handler ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct imx290_pixfmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const struct imx290_pixfmt imx290_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { MEDIA_BUS_FMT_SRGGB10_1X10, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { MEDIA_BUS_FMT_SRGGB12_1X12, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct regmap_config imx290_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .reg_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const char * const imx290_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "Sequence Pattern 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "Horizontal Color-bar Chart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "Vertical Color-bar Chart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "Sequence Pattern 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "Gradation Pattern 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "Gradation Pattern 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "000/555h Toggle Pattern",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct imx290_regval imx290_global_init_settings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { 0x3007, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { 0x3018, 0x65 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { 0x3019, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { 0x301a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { 0x3444, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { 0x3445, 0x25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { 0x303a, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 0x3040, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 0x3041, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 0x303c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 0x303d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 0x3042, 0x9c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { 0x3043, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { 0x303e, 0x49 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { 0x303f, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 0x304b, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { 0x300f, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { 0x3010, 0x21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { 0x3012, 0x64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 0x3016, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 0x3070, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 0x3071, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { 0x309b, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { 0x309c, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { 0x30a2, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { 0x30a6, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { 0x30a8, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { 0x30aa, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { 0x30ac, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { 0x30b0, 0x43 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { 0x3119, 0x9e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { 0x311c, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { 0x311e, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { 0x3128, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { 0x313d, 0x83 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { 0x3150, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { 0x317e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { 0x32b8, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { 0x32b9, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { 0x32ba, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { 0x32bb, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { 0x32c8, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { 0x32c9, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 0x32ca, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { 0x32cb, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { 0x332c, 0xd3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { 0x332d, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 0x332e, 0x0d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 0x3358, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 0x3359, 0xe1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { 0x335a, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { 0x3360, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 0x3361, 0x61 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 0x3362, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 0x33b0, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 0x33b2, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 0x33b3, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct imx290_regval imx290_1080p_settings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* mode settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { 0x3007, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { 0x303a, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { 0x3414, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { 0x3472, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { 0x3473, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { 0x3418, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { 0x3419, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { 0x3012, 0x64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { 0x3013, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 0x305c, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 0x305d, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 0x305e, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 0x305f, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 0x315e, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 0x3164, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 0x3480, 0x49 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* data rate settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 0x3405, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { 0x3446, 0x57 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { 0x3447, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { 0x3448, 0x37 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { 0x3449, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { 0x344a, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { 0x344b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { 0x344c, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { 0x344d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { 0x344e, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { 0x344f, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { 0x3450, 0x77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 0x3451, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 0x3452, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 0x3453, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { 0x3454, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { 0x3455, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct imx290_regval imx290_720p_settings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* mode settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { 0x3007, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { 0x303a, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { 0x3414, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { 0x3472, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { 0x3473, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { 0x3418, 0xd0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { 0x3419, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { 0x3012, 0x64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { 0x3013, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { 0x305c, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { 0x305d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { 0x305e, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { 0x305f, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { 0x315e, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 0x3164, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 0x3480, 0x49 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* data rate settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { 0x3405, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 0x3446, 0x4f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 0x3447, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 0x3448, 0x2f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 0x3449, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 0x344a, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 0x344b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 0x344c, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { 0x344d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 0x344e, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { 0x344f, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 0x3450, 0x57 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { 0x3451, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 0x3452, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 0x3453, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { 0x3454, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { 0x3455, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const struct imx290_regval imx290_10bit_settings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { 0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { 0x3046, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { 0x3129, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 0x317c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 0x31ec, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 0x3441, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { 0x3442, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { 0x300a, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { 0x300b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const struct imx290_regval imx290_12bit_settings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { 0x3005, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { 0x3046, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { 0x3129, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { 0x317c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { 0x31ec, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { 0x3441, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { 0x3442, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { 0x300a, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { 0x300b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* supported link frequencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define FREQ_INDEX_1080P 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define FREQ_INDEX_720P 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const s64 imx290_link_freq_2lanes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [FREQ_INDEX_1080P] = 445500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [FREQ_INDEX_720P] = 297000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const s64 imx290_link_freq_4lanes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [FREQ_INDEX_1080P] = 222750000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) [FREQ_INDEX_720P] = 148500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * In this function and in the similar ones below We rely on imx290_probe()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * to ensure that nlanes is either 2 or 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (imx290->nlanes == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return imx290_link_freq_2lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return imx290_link_freq_4lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static inline int imx290_link_freqs_num(const struct imx290 *imx290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (imx290->nlanes == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return ARRAY_SIZE(imx290_link_freq_2lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ARRAY_SIZE(imx290_link_freq_4lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Mode configs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct imx290_mode imx290_modes_2lanes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .hmax = 0x1130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .link_freq_index = FREQ_INDEX_1080P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .data = imx290_1080p_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .data_size = ARRAY_SIZE(imx290_1080p_settings),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .height = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .hmax = 0x19c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .link_freq_index = FREQ_INDEX_720P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .data = imx290_720p_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .data_size = ARRAY_SIZE(imx290_720p_settings),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct imx290_mode imx290_modes_4lanes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .hmax = 0x0898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .link_freq_index = FREQ_INDEX_1080P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .data = imx290_1080p_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .data_size = ARRAY_SIZE(imx290_1080p_settings),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .height = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .hmax = 0x0ce4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .link_freq_index = FREQ_INDEX_720P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .data = imx290_720p_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .data_size = ARRAY_SIZE(imx290_720p_settings),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (imx290->nlanes == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return imx290_modes_2lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return imx290_modes_4lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static inline int imx290_modes_num(const struct imx290 *imx290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (imx290->nlanes == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return ARRAY_SIZE(imx290_modes_2lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return ARRAY_SIZE(imx290_modes_4lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return container_of(_sd, struct imx290, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static inline int imx290_read_reg(struct imx290 *imx290, u16 addr, u8 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = regmap_read(imx290->regmap, addr, ®val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_err(imx290->dev, "I2C read failed for addr: %x\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *value = regval & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int imx290_write_reg(struct imx290 *imx290, u16 addr, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = regmap_write(imx290->regmap, addr, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_err(imx290->dev, "I2C write failed for addr: %x\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int imx290_set_register_array(struct imx290 *imx290,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) const struct imx290_regval *settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int num_settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) for (i = 0; i < num_settings; ++i, ++settings) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret = imx290_write_reg(imx290, settings->reg, settings->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Provide 10ms settle time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int imx290_write_buffered_reg(struct imx290 *imx290, u16 address_low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u8 nr_regs, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = imx290_write_reg(imx290, IMX290_REGHOLD, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_err(imx290->dev, "Error setting hold register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) for (i = 0; i < nr_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = imx290_write_reg(imx290, address_low + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) (u8)(value >> (i * 8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_err(imx290->dev, "Error writing buffered registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = imx290_write_reg(imx290, IMX290_REGHOLD, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_err(imx290->dev, "Error setting hold register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int imx290_set_gain(struct imx290 *imx290, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = imx290_write_buffered_reg(imx290, IMX290_GAIN, 1, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err(imx290->dev, "Unable to write gain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Stop streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int imx290_stop_streaming(struct imx290 *imx290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = imx290_write_reg(imx290, IMX290_STANDBY, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return imx290_write_reg(imx290, IMX290_XMSTA, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int imx290_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct imx290 *imx290 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct imx290, ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* V4L2 controls values will be applied only when power is already up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!pm_runtime_get_if_in_use(imx290->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case V4L2_CID_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = imx290_set_gain(imx290, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ctrl->val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) imx290_write_reg(imx290, IMX290_BLKLEVEL_HIGH, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) imx290_write_reg(imx290, IMX290_PGCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) (u8)(IMX290_PGCTRL_REGEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) IMX290_PGCTRL_THRU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) IMX290_PGCTRL_MODE(ctrl->val)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) imx290_write_reg(imx290, IMX290_PGCTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (imx290->bpp == 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) else /* 12 bits per pixel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) imx290_write_reg(imx290, IMX290_BLKLEVEL_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) imx290_write_reg(imx290, IMX290_BLKLEVEL_HIGH, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pm_runtime_put(imx290->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const struct v4l2_ctrl_ops imx290_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .s_ctrl = imx290_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int imx290_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (code->index >= ARRAY_SIZE(imx290_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) code->code = imx290_formats[code->index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int imx290_enum_frame_size(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) const struct imx290 *imx290 = to_imx290(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if ((fse->code != imx290_formats[0].code) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) (fse->code != imx290_formats[1].code))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (fse->index >= imx290_modes_num(imx290))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) fse->min_width = imx290_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) fse->max_width = imx290_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) fse->min_height = imx290_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) fse->max_height = imx290_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int imx290_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct imx290 *imx290 = to_imx290(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct v4l2_mbus_framefmt *framefmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mutex_lock(&imx290->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) framefmt = v4l2_subdev_get_try_format(&imx290->sd, cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) framefmt = &imx290->current_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) fmt->format = *framefmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mutex_unlock(&imx290->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static inline u8 imx290_get_link_freq_index(struct imx290 *imx290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return imx290->current_mode->link_freq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static s64 imx290_get_link_freq(struct imx290 *imx290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u8 index = imx290_get_link_freq_index(imx290);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return *(imx290_link_freqs_ptr(imx290) + index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static u64 imx290_calc_pixel_rate(struct imx290 *imx290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) s64 link_freq = imx290_get_link_freq(imx290);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u8 nlanes = imx290->nlanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u64 pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* pixel rate = link_freq * 2 * nr_of_lanes / bits_per_sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pixel_rate = link_freq * 2 * nlanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) do_div(pixel_rate, imx290->bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int imx290_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct imx290 *imx290 = to_imx290(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) const struct imx290_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct v4l2_mbus_framefmt *format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) mutex_lock(&imx290->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) imx290_modes_num(imx290), width, height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) fmt->format.width, fmt->format.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) for (i = 0; i < ARRAY_SIZE(imx290_formats); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (imx290_formats[i].code == fmt->format.code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (i >= ARRAY_SIZE(imx290_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) fmt->format.code = imx290_formats[i].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) format = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) format = &imx290->current_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) imx290->current_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) imx290->bpp = imx290_formats[i].bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (imx290->link_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) __v4l2_ctrl_s_ctrl(imx290->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) imx290_get_link_freq_index(imx290));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (imx290->pixel_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) __v4l2_ctrl_s_ctrl_int64(imx290->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) imx290_calc_pixel_rate(imx290));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) *format = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) mutex_unlock(&imx290->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int imx290_entity_init_cfg(struct v4l2_subdev *subdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct v4l2_subdev_pad_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct v4l2_subdev_format fmt = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) fmt.which = cfg ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) fmt.format.width = 1920;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) fmt.format.height = 1080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) imx290_set_fmt(subdev, cfg, &fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static int imx290_write_current_format(struct imx290 *imx290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) switch (imx290->current_format.code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) case MEDIA_BUS_FMT_SRGGB10_1X10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ret = imx290_set_register_array(imx290, imx290_10bit_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ARRAY_SIZE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) imx290_10bit_settings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dev_err(imx290->dev, "Could not set format registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case MEDIA_BUS_FMT_SRGGB12_1X12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = imx290_set_register_array(imx290, imx290_12bit_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ARRAY_SIZE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) imx290_12bit_settings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_err(imx290->dev, "Could not set format registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_err(imx290->dev, "Unknown pixel format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int imx290_set_hmax(struct imx290 *imx290, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ret = imx290_write_reg(imx290, IMX290_HMAX_LOW, (val & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_err(imx290->dev, "Error setting HMAX register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = imx290_write_reg(imx290, IMX290_HMAX_HIGH, ((val >> 8) & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_err(imx290->dev, "Error setting HMAX register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* Start streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int imx290_start_streaming(struct imx290 *imx290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* Set init register settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = imx290_set_register_array(imx290, imx290_global_init_settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ARRAY_SIZE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) imx290_global_init_settings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_err(imx290->dev, "Could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* Apply the register values related to current frame format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ret = imx290_write_current_format(imx290);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dev_err(imx290->dev, "Could not set frame format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Apply default values of current mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ret = imx290_set_register_array(imx290, imx290->current_mode->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) imx290->current_mode->data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_err(imx290->dev, "Could not set current mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ret = imx290_set_hmax(imx290, imx290->current_mode->hmax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Apply customized values from user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ret = v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dev_err(imx290->dev, "Could not sync v4l2 controls\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret = imx290_write_reg(imx290, IMX290_STANDBY, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Start streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return imx290_write_reg(imx290, IMX290_XMSTA, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static int imx290_set_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct imx290 *imx290 = to_imx290(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ret = pm_runtime_get_sync(imx290->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) pm_runtime_put_noidle(imx290->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = imx290_start_streaming(imx290);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_err(imx290->dev, "Start stream failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) pm_runtime_put(imx290->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) imx290_stop_streaming(imx290);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) pm_runtime_put(imx290->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static int imx290_get_regulators(struct device *dev, struct imx290 *imx290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) for (i = 0; i < IMX290_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) imx290->supplies[i].supply = imx290_supply_name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return devm_regulator_bulk_get(dev, IMX290_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) imx290->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int imx290_set_data_lanes(struct imx290 *imx290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int ret = 0, laneval, frsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) switch (imx290->nlanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) laneval = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) frsel = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) laneval = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) frsel = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * We should never hit this since the data lane count is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * validated in probe itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dev_err(imx290->dev, "Lane configuration not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ret = imx290_write_reg(imx290, IMX290_PHY_LANE_NUM, laneval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dev_err(imx290->dev, "Error setting Physical Lane number register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ret = imx290_write_reg(imx290, IMX290_CSI_LANE_MODE, laneval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev_err(imx290->dev, "Error setting CSI Lane mode register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ret = imx290_write_reg(imx290, IMX290_FR_FDG_SEL, frsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dev_err(imx290->dev, "Error setting FR/FDG SEL register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static int imx290_power_on(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct imx290 *imx290 = to_imx290(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = clk_prepare_enable(imx290->xclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev_err(imx290->dev, "Failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ret = regulator_bulk_enable(IMX290_NUM_SUPPLIES, imx290->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev_err(imx290->dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) clk_disable_unprepare(imx290->xclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) usleep_range(1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) gpiod_set_value_cansleep(imx290->rst_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) usleep_range(30000, 31000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* Set data lane count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) imx290_set_data_lanes(imx290);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static int imx290_power_off(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct imx290 *imx290 = to_imx290(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) clk_disable_unprepare(imx290->xclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) gpiod_set_value_cansleep(imx290->rst_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) regulator_bulk_disable(IMX290_NUM_SUPPLIES, imx290->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static const struct dev_pm_ops imx290_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) SET_RUNTIME_PM_OPS(imx290_power_off, imx290_power_on, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static const struct v4l2_subdev_video_ops imx290_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .s_stream = imx290_set_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static const struct v4l2_subdev_pad_ops imx290_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .init_cfg = imx290_entity_init_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .enum_mbus_code = imx290_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .enum_frame_size = imx290_enum_frame_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .get_fmt = imx290_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .set_fmt = imx290_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static const struct v4l2_subdev_ops imx290_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .video = &imx290_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .pad = &imx290_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static const struct media_entity_operations imx290_subdev_entity_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .link_validate = v4l2_subdev_link_validate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * Returns 0 if all link frequencies used by the driver for the given number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * of MIPI data lanes are mentioned in the device tree, or the value of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * first missing frequency otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static s64 imx290_check_link_freqs(const struct imx290 *imx290,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) const struct v4l2_fwnode_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) const s64 *freqs = imx290_link_freqs_ptr(imx290);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int freqs_count = imx290_link_freqs_num(imx290);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) for (i = 0; i < freqs_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) for (j = 0; j < ep->nr_of_link_frequencies; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (freqs[i] == ep->link_frequencies[j])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (j == ep->nr_of_link_frequencies)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return freqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static int imx290_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct fwnode_handle *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* Only CSI2 is supported for now: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct v4l2_fwnode_endpoint ep = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .bus_type = V4L2_MBUS_CSI2_DPHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct imx290 *imx290;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u32 xclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) s64 fq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (!imx290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) imx290->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) imx290->regmap = devm_regmap_init_i2c(client, &imx290_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (IS_ERR(imx290->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dev_err(dev, "Unable to initialize I2C\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dev_err(dev, "Endpoint node not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) fwnode_handle_put(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (ret == -ENXIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dev_err(dev, "Unsupported bus type, should be CSI2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) goto free_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) } else if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dev_err(dev, "Parsing endpoint node failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) goto free_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* Get number of data lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (imx290->nlanes != 2 && imx290->nlanes != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) dev_err(dev, "Invalid data lanes: %d\n", imx290->nlanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) goto free_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) dev_dbg(dev, "Using %u data lanes\n", imx290->nlanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (!ep.nr_of_link_frequencies) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) dev_err(dev, "link-frequency property not found in DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) goto free_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* Check that link frequences for all the modes are in device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) fq = imx290_check_link_freqs(imx290, &ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (fq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) dev_err(dev, "Link frequency of %lld is not supported\n", fq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) goto free_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /* get system clock (xclk) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) imx290->xclk = devm_clk_get(dev, "xclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (IS_ERR(imx290->xclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dev_err(dev, "Could not get xclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ret = PTR_ERR(imx290->xclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) goto free_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) &xclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) dev_err(dev, "Could not get xclk frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) goto free_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* external clock must be 37.125 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (xclk_freq != 37125000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dev_err(dev, "External clock frequency %u is not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) xclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) goto free_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ret = clk_set_rate(imx290->xclk, xclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) dev_err(dev, "Could not set xclk frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) goto free_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ret = imx290_get_regulators(dev, imx290);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dev_err(dev, "Cannot get regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) goto free_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (IS_ERR(imx290->rst_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dev_err(dev, "Cannot get reset gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ret = PTR_ERR(imx290->rst_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) goto free_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) mutex_init(&imx290->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * Initialize the frame format. In particular, imx290->current_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * and imx290->bpp are set to defaults: imx290_calc_pixel_rate() call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * below relies on these fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) imx290_entity_init_cfg(&imx290->sd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) v4l2_ctrl_handler_init(&imx290->ctrls, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) V4L2_CID_GAIN, 0, 72, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) imx290->link_freq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) imx290_link_freqs_num(imx290) - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) imx290_link_freqs_ptr(imx290));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (imx290->link_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) imx290->pixel_rate = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) 1, INT_MAX, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) imx290_calc_pixel_rate(imx290));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ARRAY_SIZE(imx290_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) 0, 0, imx290_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) imx290->sd.ctrl_handler = &imx290->ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (imx290->ctrls.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dev_err(dev, "Control initialization error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) imx290->ctrls.error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ret = imx290->ctrls.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) goto free_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) imx290->sd.dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) imx290->sd.entity.ops = &imx290_subdev_entity_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) imx290->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) dev_err(dev, "Could not register media entity\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) goto free_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ret = v4l2_async_register_subdev(&imx290->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) dev_err(dev, "Could not register v4l2 device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) goto free_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* Power on the device to match runtime PM state below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ret = imx290_power_on(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) dev_err(dev, "Could not power on the device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) goto free_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) v4l2_fwnode_endpoint_free(&ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) free_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) media_entity_cleanup(&imx290->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) free_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) v4l2_ctrl_handler_free(&imx290->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) mutex_destroy(&imx290->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) free_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) v4l2_fwnode_endpoint_free(&ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static int imx290_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct imx290 *imx290 = to_imx290(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) v4l2_ctrl_handler_free(sd->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) mutex_destroy(&imx290->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) pm_runtime_disable(imx290->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (!pm_runtime_status_suspended(imx290->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) imx290_power_off(imx290->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) pm_runtime_set_suspended(imx290->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static const struct of_device_id imx290_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) { .compatible = "sony,imx290" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) MODULE_DEVICE_TABLE(of, imx290_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static struct i2c_driver imx290_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .probe_new = imx290_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .remove = imx290_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .name = "imx290",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .pm = &imx290_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .of_match_table = of_match_ptr(imx290_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) module_i2c_driver(imx290_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) MODULE_DESCRIPTION("Sony IMX290 CMOS Image Sensor Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) MODULE_AUTHOR("FRAMOS GmbH");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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