^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * imx274.c - IMX274 CMOS Image Sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017, Leopard Imaging, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Leon Luo <leonl@leopardimaging.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Edwin Zou <edwinz@leopardimaging.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Luca Ceresoli <luca@lucaceresoli.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * See "SHR, SVR Setting" in datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX274_DEFAULT_FRAME_LENGTH (4550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX274_MAX_FRAME_LENGTH (0x000fffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * See "Frame Rate Adjustment" in datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX274_PIXCLK_CONST1 (72000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX274_PIXCLK_CONST2 (1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * The input gain is shifted by IMX274_GAIN_SHIFT to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * decimal number. The real gain is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * (float)input_gain_value / (1 << IMX274_GAIN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX274_GAIN_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX274_GAIN_SHIFT_MASK ((1 << IMX274_GAIN_SHIFT) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * See "Analog Gain" and "Digital Gain" in datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * min gain is 1X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * max gain is calculated based on IMX274_GAIN_REG_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX274_GAIN_REG_MAX (1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX274_MIN_GAIN (0x01 << IMX274_GAIN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX274_MAX_ANALOG_GAIN ((2048 << IMX274_GAIN_SHIFT)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) / (2048 - IMX274_GAIN_REG_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX274_MAX_DIGITAL_GAIN (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX274_DEF_GAIN (20 << IMX274_GAIN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX274_GAIN_CONST (2048) /* for gain formula */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * 1 line time in us = (HMAX / 72), minimal is 4 lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX274_MIN_EXPOSURE_TIME (4 * 260 / 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX274_DEFAULT_BINNING IMX274_BINNING_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX274_MAX_WIDTH (3840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX274_MAX_HEIGHT (2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX274_MAX_FRAME_RATE (120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX274_MIN_FRAME_RATE (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX274_DEF_FRAME_RATE (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * register SHR is limited to (SVR value + 1) x VMAX value - 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX274_SHR_LIMIT_CONST (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Min and max sensor reset delay (microseconds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX274_RESET_DELAY1 (2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX274_RESET_DELAY2 (2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * shift and mask constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX274_SHIFT_8_BITS (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX274_SHIFT_16_BITS (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IMX274_MASK_LSB_2_BITS (0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX274_MASK_LSB_3_BITS (0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX274_MASK_LSB_4_BITS (0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IMX274_MASK_LSB_8_BITS (0x00ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DRIVER_NAME "IMX274"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * IMX274 register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX274_SHR_REG_MSB 0x300D /* SHR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX274_SHR_REG_LSB 0x300C /* SHR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX274_SVR_REG_MSB 0x300F /* SVR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX274_SVR_REG_LSB 0x300E /* SVR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX274_HTRIM_EN_REG 0x3037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX274_HTRIM_START_REG_LSB 0x3038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX274_HTRIM_START_REG_MSB 0x3039
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX274_HTRIM_END_REG_LSB 0x303A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX274_HTRIM_END_REG_MSB 0x303B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX274_VWIDCUTEN_REG 0x30DD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX274_VWIDCUT_REG_LSB 0x30DE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX274_VWIDCUT_REG_MSB 0x30DF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX274_VWINPOS_REG_LSB 0x30E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX274_VWINPOS_REG_MSB 0x30E1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX274_WRITE_VSIZE_REG_LSB 0x3130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX274_WRITE_VSIZE_REG_MSB 0x3131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX274_Y_OUT_SIZE_REG_LSB 0x3132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX274_Y_OUT_SIZE_REG_MSB 0x3133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX274_VMAX_REG_1 0x30FA /* VMAX, MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX274_VMAX_REG_2 0x30F9 /* VMAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX274_VMAX_REG_3 0x30F8 /* VMAX, LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX274_HMAX_REG_MSB 0x30F7 /* HMAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX274_HMAX_REG_LSB 0x30F6 /* HMAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX274_ANALOG_GAIN_ADDR_LSB 0x300A /* ANALOG GAIN LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX274_ANALOG_GAIN_ADDR_MSB 0x300B /* ANALOG GAIN MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX274_DIGITAL_GAIN_REG 0x3012 /* Digital Gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX274_VFLIP_REG 0x301A /* VERTICAL FLIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX274_TEST_PATTERN_REG 0x303D /* TEST PATTERN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX274_STANDBY_REG 0x3000 /* STANDBY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX274_TABLE_WAIT_MS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX274_TABLE_END 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * imx274 I2C operation related structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct reg_8 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct regmap_config imx274_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .reg_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) enum imx274_binning {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) IMX274_BINNING_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) IMX274_BINNING_2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) IMX274_BINNING_3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Parameters for each imx274 readout mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * These are the values to configure the sensor in one of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * implemented modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @init_regs: registers to initialize the mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @bin_ratio: downscale factor (e.g. 3 for 3:1 binning)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @min_frame_len: Minimum frame length for each mode (see "Frame Rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Adjustment (CSI-2)" in the datasheet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @min_SHR: Minimum SHR register value (see "Shutter Setting (CSI-2)" in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * datasheet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @max_fps: Maximum frames per second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @nocpiop: Number of clocks per internal offset period (see "Integration Time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * in Each Readout Drive Mode (CSI-2)" in the datasheet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct imx274_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) const struct reg_8 *init_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int bin_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int min_frame_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int min_SHR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int nocpiop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * imx274 test pattern related structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) TEST_PATTERN_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) TEST_PATTERN_ALL_000H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) TEST_PATTERN_ALL_FFFH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) TEST_PATTERN_ALL_555H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) TEST_PATTERN_ALL_AAAH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) TEST_PATTERN_VSP_5AH, /* VERTICAL STRIPE PATTERN 555H/AAAH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) TEST_PATTERN_VSP_A5H, /* VERTICAL STRIPE PATTERN AAAH/555H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) TEST_PATTERN_VSP_05H, /* VERTICAL STRIPE PATTERN 000H/555H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) TEST_PATTERN_VSP_50H, /* VERTICAL STRIPE PATTERN 555H/000H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) TEST_PATTERN_VSP_0FH, /* VERTICAL STRIPE PATTERN 000H/FFFH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) TEST_PATTERN_VSP_F0H, /* VERTICAL STRIPE PATTERN FFFH/000H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) TEST_PATTERN_H_COLOR_BARS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) TEST_PATTERN_V_COLOR_BARS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const char * const tp_qmenu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "All 000h Pattern",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "All FFFh Pattern",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "All 555h Pattern",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "All AAAh Pattern",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "Vertical Stripe (555h / AAAh)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "Vertical Stripe (AAAh / 555h)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "Vertical Stripe (000h / 555h)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "Vertical Stripe (555h / 000h)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "Vertical Stripe (000h / FFFh)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "Vertical Stripe (FFFh / 000h)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "Vertical Color Bars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "Horizontal Color Bars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * All-pixel scan mode (10-bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * imx274 mode1(refer to datasheet) register configuration with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * 3840x2160 resolution, raw10 data and mipi four lane output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct reg_8 imx274_mode1_3840x2160_raw10[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3004, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3005, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3006, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3007, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3018, 0xA2}, /* output XVS, HVS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x306B, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x30E2, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x30EE, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3342, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3343, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3344, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x33A6, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3528, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3554, 0x1F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3555, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3556, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3557, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3558, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3559, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x355A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x35BA, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x366A, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x366B, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x366C, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x366D, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3A41, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {IMX274_TABLE_END, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Horizontal/vertical 2/2-line binning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * (Horizontal and vertical weightedbinning, 10-bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * imx274 mode3(refer to datasheet) register configuration with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * 1920x1080 resolution, raw10 data and mipi four lane output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct reg_8 imx274_mode3_1920x1080_raw10[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3004, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3005, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3006, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3007, 0xb1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3018, 0xA2}, /* output XVS, HVS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x306B, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x30E2, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x30EE, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3342, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3343, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3344, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x33A6, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3528, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3554, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3555, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3556, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3557, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3558, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3559, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x355A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x35BA, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x366A, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x366B, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x366C, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x366D, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x3A41, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {IMX274_TABLE_END, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Vertical 2/3 subsampling binning horizontal 3 binning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * imx274 mode5(refer to datasheet) register configuration with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * 1280x720 resolution, raw10 data and mipi four lane output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct reg_8 imx274_mode5_1280x720_raw10[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3004, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x3005, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x3006, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x3007, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x3018, 0xA2}, /* output XVS, HVS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x306B, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x30E2, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x30EE, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3342, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3343, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3344, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x33A6, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x3528, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x3554, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3555, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3556, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x3557, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x3558, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x3559, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x355A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x35BA, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x366A, 0x1B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x366B, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x366C, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x366D, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3A41, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {IMX274_TABLE_END, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * imx274 first step register configuration for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * starting stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct reg_8 imx274_start_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {IMX274_STANDBY_REG, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* PLRD: clock settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x3120, 0xF0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x3121, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3122, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x3129, 0x9C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x312A, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x312D, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x310B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* PLSTMG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x304C, 0x00}, /* PLSTMG01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x304D, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x331C, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x331D, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x3502, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x3529, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x352A, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x352B, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x3538, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x3539, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3553, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x357D, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x357F, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3581, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3583, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x3587, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x35BB, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x35BC, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x35BD, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x35BE, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x35BF, 0x0E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x366E, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x366F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3670, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3671, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* PSMIPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x3304, 0x32}, /* PSMIPI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x3305, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x3306, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x3307, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x3590, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x3591, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3686, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3687, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {IMX274_TABLE_END, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * imx274 second step register configuration for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * starting stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct reg_8 imx274_start_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {IMX274_STANDBY_REG, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x303E, 0x02}, /* SYS_MODE = 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {IMX274_TABLE_END, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * imx274 third step register configuration for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * starting stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const struct reg_8 imx274_start_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x30F4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x3018, 0xA2}, /* XHS VHS OUTPUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {IMX274_TABLE_END, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * imx274 register configuration for stopping stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const struct reg_8 imx274_stop[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {IMX274_STANDBY_REG, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {IMX274_TABLE_END, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * imx274 disable test pattern register configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const struct reg_8 imx274_tp_disabled[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x303C, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x377F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3781, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x370B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {IMX274_TABLE_END, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * imx274 test pattern register configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * reg 0x303D defines the test pattern modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct reg_8 imx274_tp_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x303C, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x370E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x377F, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3781, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x370B, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {IMX274_TABLE_END, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* nocpiop happens to be the same number for the implemented modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const struct imx274_mode imx274_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* mode 1, 4K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .bin_ratio = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .init_regs = imx274_mode1_3840x2160_raw10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .min_frame_len = 4550,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .min_SHR = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .max_fps = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .nocpiop = 112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* mode 3, 1080p */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .bin_ratio = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .init_regs = imx274_mode3_1920x1080_raw10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .min_frame_len = 2310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .min_SHR = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .max_fps = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .nocpiop = 112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* mode 5, 720p */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .bin_ratio = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .init_regs = imx274_mode5_1280x720_raw10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .min_frame_len = 2310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .min_SHR = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .max_fps = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .nocpiop = 112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * struct imx274_ctrls - imx274 ctrl structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * @handler: V4L2 ctrl handler structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * @exposure: Pointer to expsure ctrl structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * @gain: Pointer to gain ctrl structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * @vflip: Pointer to vflip ctrl structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * @test_pattern: Pointer to test pattern ctrl structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct imx274_ctrls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct v4l2_ctrl_handler handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct v4l2_ctrl *gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct v4l2_ctrl *vflip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * struct stim274 - imx274 device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * @sd: V4L2 subdevice structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * @pad: Media pad structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * @client: Pointer to I2C client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * @ctrls: imx274 control structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * @crop: rect to be captured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * @compose: compose rect, i.e. output resolution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * @format: V4L2 media bus frame format structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * (width and height are in sync with the compose rect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * @frame_rate: V4L2 frame rate structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * @regmap: Pointer to regmap structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * @reset_gpio: Pointer to reset gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * @lock: Mutex structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * @mode: Parameters for the selected readout mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct stimx274 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct imx274_ctrls ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct v4l2_rect crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct v4l2_mbus_framefmt format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct v4l2_fract frame_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct mutex lock; /* mutex lock for operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) const struct imx274_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define IMX274_ROUND(dim, step, flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ((flags) & V4L2_SEL_FLAG_GE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ? roundup((dim), (step)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) : ((flags) & V4L2_SEL_FLAG_LE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ? rounddown((dim), (step)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) : rounddown((dim) + (step) / 2, (step))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * Function declaration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int imx274_set_gain(struct stimx274 *priv, struct v4l2_ctrl *ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int imx274_set_exposure(struct stimx274 *priv, int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static int imx274_set_vflip(struct stimx274 *priv, int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int imx274_set_test_pattern(struct stimx274 *priv, int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int imx274_set_frame_interval(struct stimx274 *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct v4l2_fract frame_interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static inline void msleep_range(unsigned int delay_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) usleep_range(delay_base * 1000, delay_base * 1000 + 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * v4l2_ctrl and v4l2_subdev related operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return &container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct stimx274, ctrls.handler)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static inline struct stimx274 *to_imx274(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return container_of(sd, struct stimx274, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * Writing a register table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * @priv: Pointer to device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * @table: Table containing register values (with optional delays)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * This is used to write register table into sensor's reg map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * Return: 0 on success, errors otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int imx274_write_table(struct stimx274 *priv, const struct reg_8 table[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct regmap *regmap = priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) const struct reg_8 *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int range_start = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int range_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u8 range_vals[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int max_range_vals = ARRAY_SIZE(range_vals);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) for (next = table;; next++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if ((next->addr != range_start + range_count) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) (next->addr == IMX274_TABLE_END) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) (next->addr == IMX274_TABLE_WAIT_MS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) (range_count == max_range_vals)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (range_count == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) err = regmap_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) range_start, range_vals[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) else if (range_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) err = regmap_bulk_write(regmap, range_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) &range_vals[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) range_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) range_start = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) range_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Handle special address values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (next->addr == IMX274_TABLE_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (next->addr == IMX274_TABLE_WAIT_MS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) msleep_range(next->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) val = next->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (range_start == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) range_start = next->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) range_vals[range_count++] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static inline int imx274_write_reg(struct stimx274 *priv, u16 addr, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) err = regmap_write(priv->regmap, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_err(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "%s : i2c write failed, %x = %x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_dbg(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) "%s : addr 0x%x, val=0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * Read a multibyte register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * Uses a bulk read where possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * @addr: Address of the LSB register. Other registers must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * consecutive, least-to-most significant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * @val: Pointer to store the register value (cpu endianness)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * @nbytes: Number of bytes to read (range: [1..3]).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * Other bytes are zet to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * Return: 0 on success, errors otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int imx274_read_mbreg(struct stimx274 *priv, u16 addr, u32 *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) size_t nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) __le32 val_le = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) err = regmap_bulk_read(priv->regmap, addr, &val_le, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dev_err(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) "%s : i2c bulk read failed, %x (%zu bytes)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) __func__, addr, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) *val = le32_to_cpu(val_le);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dev_dbg(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) "%s : addr 0x%x, val=0x%x (%zu bytes)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) __func__, addr, *val, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * Write a multibyte register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * Uses a bulk write where possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * @addr: Address of the LSB register. Other registers must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * consecutive, least-to-most significant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * @val: Value to be written to the register (cpu endianness)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * @nbytes: Number of bytes to write (range: [1..3])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static int imx274_write_mbreg(struct stimx274 *priv, u16 addr, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) size_t nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) __le32 val_le = cpu_to_le32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) err = regmap_bulk_write(priv->regmap, addr, &val_le, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dev_err(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) "%s : i2c bulk write failed, %x = %x (%zu bytes)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) __func__, addr, val, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev_dbg(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) "%s : addr 0x%x, val=0x%x (%zu bytes)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) __func__, addr, val, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * Set mode registers to start stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * Return: 0 on success, errors otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int imx274_mode_regs(struct stimx274 *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) err = imx274_write_table(priv, imx274_start_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) err = imx274_write_table(priv, priv->mode->init_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * imx274_start_stream - Function for starting stream per mode index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * Return: 0 on success, errors otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static int imx274_start_stream(struct stimx274 *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * Refer to "Standby Cancel Sequence when using CSI-2" in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * imx274 datasheet, it should wait 10ms or more here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * give it 1 extra ms for margin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) msleep_range(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) err = imx274_write_table(priv, imx274_start_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * Refer to "Standby Cancel Sequence when using CSI-2" in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * imx274 datasheet, it should wait 7ms or more here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * give it 1 extra ms for margin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) msleep_range(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) err = imx274_write_table(priv, imx274_start_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * imx274_reset - Function called to reset the sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * @rst: Input value for determining the sensor's end state after reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * Set the senor in reset and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * if rst = 0, keep it in reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * if rst = 1, bring it out of reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static void imx274_reset(struct stimx274 *priv, int rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) gpiod_set_value_cansleep(priv->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) usleep_range(IMX274_RESET_DELAY1, IMX274_RESET_DELAY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) gpiod_set_value_cansleep(priv->reset_gpio, !!rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) usleep_range(IMX274_RESET_DELAY1, IMX274_RESET_DELAY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * imx274_s_ctrl - This is used to set the imx274 V4L2 controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * @ctrl: V4L2 control to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * This function is used to set the V4L2 controls for the imx274 sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * Return: 0 on success, errors otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static int imx274_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct stimx274 *imx274 = to_imx274(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dev_dbg(&imx274->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) "%s : s_ctrl: %s, value: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ctrl->name, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dev_dbg(&imx274->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) "%s : set V4L2_CID_EXPOSURE\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = imx274_set_exposure(imx274, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) case V4L2_CID_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dev_dbg(&imx274->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "%s : set V4L2_CID_GAIN\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ret = imx274_set_gain(imx274, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dev_dbg(&imx274->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) "%s : set V4L2_CID_VFLIP\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ret = imx274_set_vflip(imx274, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_dbg(&imx274->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) "%s : set V4L2_CID_TEST_PATTERN\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ret = imx274_set_test_pattern(imx274, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static int imx274_binning_goodness(struct stimx274 *imx274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int w, int ask_w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) int h, int ask_h, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct device *dev = &imx274->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) const int goodness = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (flags & V4L2_SEL_FLAG_GE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (w < ask_w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) val -= goodness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (h < ask_h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) val -= goodness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (flags & V4L2_SEL_FLAG_LE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (w > ask_w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) val -= goodness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (h > ask_h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) val -= goodness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) val -= abs(w - ask_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) val -= abs(h - ask_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dev_dbg(dev, "%s: ask %dx%d, size %dx%d, goodness %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) __func__, ask_w, ask_h, w, h, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * Helper function to change binning and set both compose and format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * We have two entry points to change binning: set_fmt and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * set_selection(COMPOSE). Both have to compute the new output size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * and set it in both the compose rect and the frame format size. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * also need to do the same things after setting cropping to restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * 1:1 binning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * This function contains the common code for these three cases, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * has many arguments in order to accommodate the needs of all of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * Must be called with imx274->lock locked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * @imx274: The device object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * @cfg: The pad config we are editing for TRY requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * @which: V4L2_SUBDEV_FORMAT_ACTIVE or V4L2_SUBDEV_FORMAT_TRY from the caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * @width: Input-output parameter: set to the desired width before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * the call, contains the chosen value after returning successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * @height: Input-output parameter for height (see @width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * @flags: Selection flags from struct v4l2_subdev_selection, or 0 if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * available (when called from set_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static int __imx274_change_compose(struct stimx274 *imx274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u32 which,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u32 *width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u32 *height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct device *dev = &imx274->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) const struct v4l2_rect *cur_crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct v4l2_mbus_framefmt *tgt_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) const struct imx274_mode *best_mode = &imx274_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int best_goodness = INT_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) cur_crop = &cfg->try_crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) tgt_fmt = &cfg->try_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) cur_crop = &imx274->crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) tgt_fmt = &imx274->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) for (i = 0; i < ARRAY_SIZE(imx274_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) unsigned int ratio = imx274_modes[i].bin_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) int goodness = imx274_binning_goodness(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) imx274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) cur_crop->width / ratio, *width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) cur_crop->height / ratio, *height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (goodness >= best_goodness) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) best_goodness = goodness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) best_mode = &imx274_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) *width = cur_crop->width / best_mode->bin_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) *height = cur_crop->height / best_mode->bin_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) imx274->mode = best_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dev_dbg(dev, "%s: selected %u:1 binning\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) __func__, best_mode->bin_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) tgt_fmt->width = *width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) tgt_fmt->height = *height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) tgt_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * imx274_get_fmt - Get the pad format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * @sd: Pointer to V4L2 Sub device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * @cfg: Pointer to sub device pad information structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * @fmt: Pointer to pad level media bus format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * This function is used to get the pad format information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * Return: 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static int imx274_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct stimx274 *imx274 = to_imx274(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) mutex_lock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) fmt->format = imx274->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) mutex_unlock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * imx274_set_fmt - This is used to set the pad format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * @sd: Pointer to V4L2 Sub device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * @cfg: Pointer to sub device pad information structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * @format: Pointer to pad level media bus format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * This function is used to set the pad format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * Return: 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static int imx274_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct v4l2_mbus_framefmt *fmt = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct stimx274 *imx274 = to_imx274(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) mutex_lock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) err = __imx274_change_compose(imx274, cfg, format->which,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) &fmt->width, &fmt->height, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * __imx274_change_compose already set width and height in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * applicable format, but we need to keep all other format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * values, so do a full copy here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (format->which == V4L2_SUBDEV_FORMAT_TRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) cfg->try_fmt = *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) imx274->format = *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) mutex_unlock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static int imx274_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct stimx274 *imx274 = to_imx274(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) const struct v4l2_rect *src_crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) const struct v4l2_mbus_framefmt *src_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (sel->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) sel->r.top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) sel->r.width = IMX274_MAX_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) sel->r.height = IMX274_MAX_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) src_crop = &cfg->try_crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) src_fmt = &cfg->try_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) src_crop = &imx274->crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) src_fmt = &imx274->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) mutex_lock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) switch (sel->target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) case V4L2_SEL_TGT_CROP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) sel->r = *src_crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) case V4L2_SEL_TGT_COMPOSE_BOUNDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) sel->r.top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) sel->r.width = src_crop->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) sel->r.height = src_crop->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case V4L2_SEL_TGT_COMPOSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) sel->r.top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) sel->r.width = src_fmt->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) sel->r.height = src_fmt->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) mutex_unlock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static int imx274_set_selection_crop(struct stimx274 *imx274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct v4l2_rect *tgt_crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct v4l2_rect new_crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) bool size_changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * h_step could be 12 or 24 depending on the binning. But we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * won't know the binning until we choose the mode later in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * __imx274_change_compose(). Thus let's be safe and use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * most conservative value in all cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) const u32 h_step = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) new_crop.width = min_t(u32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) IMX274_ROUND(sel->r.width, h_step, sel->flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) IMX274_MAX_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* Constraint: HTRIMMING_END - HTRIMMING_START >= 144 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (new_crop.width < 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) new_crop.width = 144;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) new_crop.left = min_t(u32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) IMX274_ROUND(sel->r.left, h_step, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) IMX274_MAX_WIDTH - new_crop.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) new_crop.height = min_t(u32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) IMX274_ROUND(sel->r.height, 2, sel->flags),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) IMX274_MAX_HEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) new_crop.top = min_t(u32, IMX274_ROUND(sel->r.top, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) IMX274_MAX_HEIGHT - new_crop.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) sel->r = new_crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (sel->which == V4L2_SUBDEV_FORMAT_TRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) tgt_crop = &cfg->try_crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) tgt_crop = &imx274->crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) mutex_lock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) size_changed = (new_crop.width != tgt_crop->width ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) new_crop.height != tgt_crop->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* __imx274_change_compose needs the new size in *tgt_crop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) *tgt_crop = new_crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /* if crop size changed then reset the output image size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (size_changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) __imx274_change_compose(imx274, cfg, sel->which,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) &new_crop.width, &new_crop.height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) sel->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) mutex_unlock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static int imx274_set_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct stimx274 *imx274 = to_imx274(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (sel->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (sel->target == V4L2_SEL_TGT_CROP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return imx274_set_selection_crop(imx274, cfg, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (sel->target == V4L2_SEL_TGT_COMPOSE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) mutex_lock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) err = __imx274_change_compose(imx274, cfg, sel->which,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) &sel->r.width, &sel->r.height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) sel->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) mutex_unlock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * __imx274_change_compose already set width and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * height in set->r, we still need to set top-left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) sel->r.top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static int imx274_apply_trimming(struct stimx274 *imx274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) u32 h_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) u32 h_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) u32 hmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) u32 v_cut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) s32 v_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) u32 write_v_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) u32 y_out_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) h_start = imx274->crop.left + 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) h_end = h_start + imx274->crop.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* Use the minimum allowed value of HMAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* Note: except in mode 1, (width / 16 + 23) is always < hmax_min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* Note: 260 is the minimum HMAX in all implemented modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) hmax = max_t(u32, 260, (imx274->crop.width) / 16 + 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* invert v_pos if VFLIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) v_pos = imx274->ctrls.vflip->cur.val ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) (-imx274->crop.top / 2) : (imx274->crop.top / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) v_cut = (IMX274_MAX_HEIGHT - imx274->crop.height) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) write_v_size = imx274->crop.height + 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) y_out_size = imx274->crop.height + 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) err = imx274_write_mbreg(imx274, IMX274_HMAX_REG_LSB, hmax, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) err = imx274_write_mbreg(imx274, IMX274_HTRIM_EN_REG, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) err = imx274_write_mbreg(imx274, IMX274_HTRIM_START_REG_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) h_start, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) err = imx274_write_mbreg(imx274, IMX274_HTRIM_END_REG_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) h_end, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) err = imx274_write_mbreg(imx274, IMX274_VWIDCUTEN_REG, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) err = imx274_write_mbreg(imx274, IMX274_VWIDCUT_REG_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) v_cut, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) err = imx274_write_mbreg(imx274, IMX274_VWINPOS_REG_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) v_pos, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) err = imx274_write_mbreg(imx274, IMX274_WRITE_VSIZE_REG_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) write_v_size, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) err = imx274_write_mbreg(imx274, IMX274_Y_OUT_SIZE_REG_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) y_out_size, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * imx274_g_frame_interval - Get the frame interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * @sd: Pointer to V4L2 Sub device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * @fi: Pointer to V4l2 Sub device frame interval structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * This function is used to get the frame interval.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * Return: 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static int imx274_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) struct stimx274 *imx274 = to_imx274(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) fi->interval = imx274->frame_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) dev_dbg(&imx274->client->dev, "%s frame rate = %d / %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) __func__, imx274->frame_interval.numerator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) imx274->frame_interval.denominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * imx274_s_frame_interval - Set the frame interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * @sd: Pointer to V4L2 Sub device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * @fi: Pointer to V4l2 Sub device frame interval structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * This function is used to set the frame intervavl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * Return: 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static int imx274_s_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct stimx274 *imx274 = to_imx274(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct v4l2_ctrl *ctrl = imx274->ctrls.exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) int min, max, def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) mutex_lock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ret = imx274_set_frame_interval(imx274, fi->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) fi->interval = imx274->frame_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * exposure time range is decided by frame interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * need to update it after frame interval changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) min = IMX274_MIN_EXPOSURE_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) max = fi->interval.numerator * 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) / fi->interval.denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) def = max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (__v4l2_ctrl_modify_range(ctrl, min, max, 1, def)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) dev_err(&imx274->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) "Exposure ctrl range update failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* update exposure time accordingly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) imx274_set_exposure(imx274, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) dev_dbg(&imx274->client->dev, "set frame interval to %uus\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) fi->interval.numerator * 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) / fi->interval.denominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) mutex_unlock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * imx274_load_default - load default control values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * Return: 0 on success, errors otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static int imx274_load_default(struct stimx274 *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /* load default control values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) priv->frame_interval.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) priv->frame_interval.denominator = IMX274_DEF_FRAME_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) priv->ctrls.exposure->val = 1000000 / IMX274_DEF_FRAME_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) priv->ctrls.gain->val = IMX274_DEF_GAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) priv->ctrls.vflip->val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) priv->ctrls.test_pattern->val = TEST_PATTERN_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) /* update frame rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ret = imx274_set_frame_interval(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) priv->frame_interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /* update exposure time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ret = v4l2_ctrl_s_ctrl(priv->ctrls.exposure, priv->ctrls.exposure->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* update gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) ret = v4l2_ctrl_s_ctrl(priv->ctrls.gain, priv->ctrls.gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /* update vflip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ret = v4l2_ctrl_s_ctrl(priv->ctrls.vflip, priv->ctrls.vflip->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * imx274_s_stream - It is used to start/stop the streaming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * @sd: V4L2 Sub device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * @on: Flag (True / False)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * This function controls the start or stop of streaming for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * imx274 sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * Return: 0 on success, errors otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static int imx274_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct stimx274 *imx274 = to_imx274(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) dev_dbg(&imx274->client->dev, "%s : %s, mode index = %td\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) on ? "Stream Start" : "Stream Stop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) imx274->mode - &imx274_modes[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) mutex_lock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* load mode registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ret = imx274_mode_regs(imx274);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ret = imx274_apply_trimming(imx274);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * update frame rate & expsoure. if the last mode is different,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * HMAX could be changed. As the result, frame rate & exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * are changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * gain is not affected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ret = imx274_set_frame_interval(imx274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) imx274->frame_interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* update exposure time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ret = __v4l2_ctrl_s_ctrl(imx274->ctrls.exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) imx274->ctrls.exposure->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* start stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret = imx274_start_stream(imx274);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /* stop stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) ret = imx274_write_table(imx274, imx274_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) mutex_unlock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) dev_dbg(&imx274->client->dev, "%s : Done\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) mutex_unlock(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) dev_err(&imx274->client->dev, "s_stream failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) * imx274_get_frame_length - Function for obtaining current frame length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * @val: Pointer to obainted value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * frame_length = vmax x (svr + 1), in unit of hmax.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * Return: 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static int imx274_get_frame_length(struct stimx274 *priv, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) u32 svr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) u32 vmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) err = imx274_read_mbreg(priv, IMX274_SVR_REG_LSB, &svr, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) err = imx274_read_mbreg(priv, IMX274_VMAX_REG_3, &vmax, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) *val = vmax * (svr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static int imx274_clamp_coarse_time(struct stimx274 *priv, u32 *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) u32 *frame_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) err = imx274_get_frame_length(priv, frame_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (*frame_length < priv->mode->min_frame_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) *frame_length = priv->mode->min_frame_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) *val = *frame_length - *val; /* convert to raw shr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (*val > *frame_length - IMX274_SHR_LIMIT_CONST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) *val = *frame_length - IMX274_SHR_LIMIT_CONST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) else if (*val < priv->mode->min_SHR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) *val = priv->mode->min_SHR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) * imx274_set_digital gain - Function called when setting digital gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * @dgain: Value of digital gain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) * Digital gain has only 4 steps: 1x, 2x, 4x, and 8x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * Return: 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static int imx274_set_digital_gain(struct stimx274 *priv, u32 dgain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) u8 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) reg_val = ffs(dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (reg_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) reg_val--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) reg_val = clamp(reg_val, (u8)0, (u8)3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return imx274_write_reg(priv, IMX274_DIGITAL_GAIN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) reg_val & IMX274_MASK_LSB_4_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * imx274_set_gain - Function called when setting gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * @val: Value of gain. the real value = val << IMX274_GAIN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * @ctrl: v4l2 control pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * Set the gain based on input value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * The caller should hold the mutex lock imx274->lock if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) * Return: 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static int imx274_set_gain(struct stimx274 *priv, struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) u32 gain, analog_gain, digital_gain, gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) gain = (u32)(ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) dev_dbg(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) "%s : input gain = %d.%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) gain >> IMX274_GAIN_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ((gain & IMX274_GAIN_SHIFT_MASK) * 100) >> IMX274_GAIN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (gain > IMX274_MAX_DIGITAL_GAIN * IMX274_MAX_ANALOG_GAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) gain = IMX274_MAX_DIGITAL_GAIN * IMX274_MAX_ANALOG_GAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) else if (gain < IMX274_MIN_GAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) gain = IMX274_MIN_GAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (gain <= IMX274_MAX_ANALOG_GAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) digital_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) else if (gain <= IMX274_MAX_ANALOG_GAIN * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) digital_gain = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) else if (gain <= IMX274_MAX_ANALOG_GAIN * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) digital_gain = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) digital_gain = IMX274_MAX_DIGITAL_GAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) analog_gain = gain / digital_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) dev_dbg(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) "%s : digital gain = %d, analog gain = %d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) __func__, digital_gain, analog_gain >> IMX274_GAIN_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) ((analog_gain & IMX274_GAIN_SHIFT_MASK) * 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) >> IMX274_GAIN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) err = imx274_set_digital_gain(priv, digital_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* convert to register value, refer to imx274 datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) gain_reg = (u32)IMX274_GAIN_CONST -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) (IMX274_GAIN_CONST << IMX274_GAIN_SHIFT) / analog_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (gain_reg > IMX274_GAIN_REG_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) gain_reg = IMX274_GAIN_REG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) err = imx274_write_mbreg(priv, IMX274_ANALOG_GAIN_ADDR_LSB, gain_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (IMX274_GAIN_CONST - gain_reg == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) /* convert register value back to gain value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) ctrl->val = (IMX274_GAIN_CONST << IMX274_GAIN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) / (IMX274_GAIN_CONST - gain_reg) * digital_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) dev_dbg(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) "%s : GAIN control success, gain_reg = %d, new gain = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) __func__, gain_reg, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * imx274_set_coarse_time - Function called when setting SHR value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) * @val: Value for exposure time in number of line_length, or [HMAX]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * Set SHR value based on input value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * Return: 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) static int imx274_set_coarse_time(struct stimx274 *priv, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) u32 coarse_time, frame_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) coarse_time = *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) /* convert exposure_time to appropriate SHR value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) err = imx274_clamp_coarse_time(priv, &coarse_time, &frame_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) err = imx274_write_mbreg(priv, IMX274_SHR_REG_LSB, coarse_time, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) *val = frame_length - coarse_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) * imx274_set_exposure - Function called when setting exposure time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) * @val: Variable for exposure time, in the unit of micro-second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) * Set exposure time based on input value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) * The caller should hold the mutex lock imx274->lock if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) * Return: 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static int imx274_set_exposure(struct stimx274 *priv, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) u32 hmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) u32 coarse_time; /* exposure time in unit of line (HMAX)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) dev_dbg(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) "%s : EXPOSURE control input = %d\n", __func__, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) /* step 1: convert input exposure_time (val) into number of 1[HMAX] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) err = imx274_read_mbreg(priv, IMX274_HMAX_REG_LSB, &hmax, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) if (hmax == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) coarse_time = (IMX274_PIXCLK_CONST1 / IMX274_PIXCLK_CONST2 * val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) - priv->mode->nocpiop) / hmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) /* step 2: convert exposure_time into SHR value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) /* set SHR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) err = imx274_set_coarse_time(priv, &coarse_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) priv->ctrls.exposure->val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) (coarse_time * hmax + priv->mode->nocpiop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) / (IMX274_PIXCLK_CONST1 / IMX274_PIXCLK_CONST2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) dev_dbg(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) "%s : EXPOSURE control success\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * imx274_set_vflip - Function called when setting vertical flip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) * @val: Value for vflip setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * Set vertical flip based on input value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * val = 0: normal, no vertical flip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * val = 1: vertical flip enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) * The caller should hold the mutex lock imx274->lock if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) * Return: 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static int imx274_set_vflip(struct stimx274 *priv, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) err = imx274_write_reg(priv, IMX274_VFLIP_REG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) dev_err(&priv->client->dev, "VFLIP control error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) dev_dbg(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) "%s : VFLIP control success\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) * imx274_set_test_pattern - Function called when setting test pattern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) * @val: Variable for test pattern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) * Set to different test patterns based on input value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) * Return: 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) static int imx274_set_test_pattern(struct stimx274 *priv, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (val == TEST_PATTERN_DISABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) err = imx274_write_table(priv, imx274_tp_disabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) } else if (val <= TEST_PATTERN_V_COLOR_BARS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) err = imx274_write_reg(priv, IMX274_TEST_PATTERN_REG, val - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) err = imx274_write_table(priv, imx274_tp_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) dev_dbg(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) "%s : TEST PATTERN control success\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) * imx274_set_frame_length - Function called when setting frame length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) * @val: Variable for frame length (= VMAX, i.e. vertical drive period length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) * Set frame length based on input value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) * Return: 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static int imx274_set_frame_length(struct stimx274 *priv, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) u32 frame_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) dev_dbg(&priv->client->dev, "%s : input length = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) __func__, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) frame_length = (u32)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) err = imx274_write_mbreg(priv, IMX274_VMAX_REG_3, frame_length, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) * imx274_set_frame_interval - Function called when setting frame interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) * @priv: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) * @frame_interval: Variable for frame interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) * Change frame interval by updating VMAX value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * The caller should hold the mutex lock imx274->lock if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) * Return: 0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static int imx274_set_frame_interval(struct stimx274 *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) struct v4l2_fract frame_interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) u32 frame_length, req_frame_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) u32 svr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) u32 hmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) dev_dbg(&priv->client->dev, "%s: input frame interval = %d / %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) __func__, frame_interval.numerator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) frame_interval.denominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) if (frame_interval.numerator == 0 || frame_interval.denominator == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) frame_interval.denominator = IMX274_DEF_FRAME_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) frame_interval.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) req_frame_rate = (u32)(frame_interval.denominator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) / frame_interval.numerator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) /* boundary check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (req_frame_rate > priv->mode->max_fps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) frame_interval.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) frame_interval.denominator = priv->mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) } else if (req_frame_rate < IMX274_MIN_FRAME_RATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) frame_interval.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) frame_interval.denominator = IMX274_MIN_FRAME_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * VMAX = 1/frame_rate x 72M / (SVR+1) / HMAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * frame_length (i.e. VMAX) = (frame_interval) x 72M /(SVR+1) / HMAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) err = imx274_read_mbreg(priv, IMX274_SVR_REG_LSB, &svr, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) dev_dbg(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) "%s : register SVR = %d\n", __func__, svr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) err = imx274_read_mbreg(priv, IMX274_HMAX_REG_LSB, &hmax, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) dev_dbg(&priv->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) "%s : register HMAX = %d\n", __func__, hmax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) if (hmax == 0 || frame_interval.denominator == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) frame_length = IMX274_PIXCLK_CONST1 / (svr + 1) / hmax
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) * frame_interval.numerator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) / frame_interval.denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) err = imx274_set_frame_length(priv, frame_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) priv->frame_interval = frame_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) dev_err(&priv->client->dev, "%s error = %d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static const struct v4l2_subdev_pad_ops imx274_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .get_fmt = imx274_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .set_fmt = imx274_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .get_selection = imx274_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .set_selection = imx274_set_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) static const struct v4l2_subdev_video_ops imx274_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .g_frame_interval = imx274_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .s_frame_interval = imx274_s_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .s_stream = imx274_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) static const struct v4l2_subdev_ops imx274_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .pad = &imx274_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .video = &imx274_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) static const struct v4l2_ctrl_ops imx274_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .s_ctrl = imx274_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) static const struct of_device_id imx274_of_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) { .compatible = "sony,imx274" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) MODULE_DEVICE_TABLE(of, imx274_of_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) static const struct i2c_device_id imx274_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) { "IMX274", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) MODULE_DEVICE_TABLE(i2c, imx274_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) static int imx274_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct stimx274 *imx274;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) /* initialize imx274 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) imx274 = devm_kzalloc(&client->dev, sizeof(*imx274), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (!imx274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) mutex_init(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) /* initialize format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) imx274->mode = &imx274_modes[IMX274_DEFAULT_BINNING];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) imx274->crop.width = IMX274_MAX_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) imx274->crop.height = IMX274_MAX_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) imx274->format.width = imx274->crop.width / imx274->mode->bin_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) imx274->format.height = imx274->crop.height / imx274->mode->bin_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) imx274->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) imx274->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) imx274->format.colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) imx274->frame_interval.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) imx274->frame_interval.denominator = IMX274_DEF_FRAME_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) /* initialize regmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) imx274->regmap = devm_regmap_init_i2c(client, &imx274_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) if (IS_ERR(imx274->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) "regmap init failed: %ld\n", PTR_ERR(imx274->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) goto err_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) /* initialize subdevice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) imx274->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) sd = &imx274->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) v4l2_i2c_subdev_init(sd, client, &imx274_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) /* initialize subdev media pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) imx274->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) ret = media_entity_pads_init(&sd->entity, 1, &imx274->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) "%s : media entity init Failed %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) goto err_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) /* initialize sensor reset gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) imx274->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (IS_ERR(imx274->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) if (PTR_ERR(imx274->reset_gpio) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) dev_err(&client->dev, "Reset GPIO not setup in DT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) ret = PTR_ERR(imx274->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) goto err_me;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) /* pull sensor out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) imx274_reset(imx274, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) /* initialize controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ret = v4l2_ctrl_handler_init(&imx274->ctrls.handler, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) "%s : ctrl handler init Failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) goto err_me;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) imx274->ctrls.handler.lock = &imx274->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) /* add new controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) imx274->ctrls.test_pattern = v4l2_ctrl_new_std_menu_items(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) &imx274->ctrls.handler, &imx274_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) ARRAY_SIZE(tp_qmenu) - 1, 0, 0, tp_qmenu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) imx274->ctrls.gain = v4l2_ctrl_new_std(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) &imx274->ctrls.handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) &imx274_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) V4L2_CID_GAIN, IMX274_MIN_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) IMX274_MAX_DIGITAL_GAIN * IMX274_MAX_ANALOG_GAIN, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) IMX274_DEF_GAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) imx274->ctrls.exposure = v4l2_ctrl_new_std(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) &imx274->ctrls.handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) &imx274_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) V4L2_CID_EXPOSURE, IMX274_MIN_EXPOSURE_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) 1000000 / IMX274_DEF_FRAME_RATE, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) IMX274_MIN_EXPOSURE_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) imx274->ctrls.vflip = v4l2_ctrl_new_std(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) &imx274->ctrls.handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) &imx274_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) imx274->sd.ctrl_handler = &imx274->ctrls.handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (imx274->ctrls.handler.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) ret = imx274->ctrls.handler.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) goto err_ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) /* setup default controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) ret = v4l2_ctrl_handler_setup(&imx274->ctrls.handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) "Error %d setup default controls\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) goto err_ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) /* load default control values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) ret = imx274_load_default(imx274);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) "%s : imx274_load_default failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) goto err_ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) /* register subdevice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) ret = v4l2_async_register_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) "%s : v4l2_async_register_subdev failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) goto err_ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) dev_info(&client->dev, "imx274 : imx274 probe success !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) err_ctrls:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) v4l2_ctrl_handler_free(&imx274->ctrls.handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) err_me:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) err_regmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) mutex_destroy(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) static int imx274_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) struct stimx274 *imx274 = to_imx274(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) /* stop stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) imx274_write_table(imx274, imx274_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) v4l2_ctrl_handler_free(&imx274->ctrls.handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) mutex_destroy(&imx274->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) static struct i2c_driver imx274_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .of_match_table = imx274_of_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .probe_new = imx274_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .remove = imx274_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .id_table = imx274_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) module_i2c_driver(imx274_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) MODULE_AUTHOR("Leon Luo <leonl@leopardimaging.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) MODULE_DESCRIPTION("IMX274 CMOS Image Sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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