^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * imx258 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X05 add function g_mbus_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * V0.0X01.0X06 support capture spd data and embedded data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "imx258_eeprom_head.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX258_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX258_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX258_LINK_FREQ_498MHZ 498000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX258_LINK_FREQ_399MHZ 399000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX258_PIXEL_RATE_FULL_SIZE 398400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX258_PIXEL_RATE_BINNING 319200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX258_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CHIP_ID 0x0258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX258_REG_CHIP_ID 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX258_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX258_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX258_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX258_REG_EXPOSURE 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX258_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX258_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX258_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX258_REG_GAIN_H 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX258_REG_GAIN_L 0x0205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX258_GAIN_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX258_GAIN_MAX 0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX258_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX258_GAIN_DEFAULT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX258_REG_TEST_PATTERN 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX258_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX258_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX258_REG_VTS 0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX258_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX258_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX258_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX258_NAME "imx258"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const char * const imx258_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX258_NUM_SUPPLIES ARRAY_SIZE(imx258_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct other_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct imx258_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Shield Pix Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) const struct other_data *spd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* embedded Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const struct other_data *ebd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct imx258 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct regulator_bulk_data supplies[IMX258_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct imx258_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct imx258_otp_info *otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct rkmodule_inf module_inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct rkmodule_awb_cfg awb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct rkmodule_lsc_cfg lsc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 spd_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 ebd_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define to_imx258(sd) container_of(sd, struct imx258, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct imx258_id_name {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) char name[RKMODULE_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct imx258_id_name imx258_module_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x36, "GuangDongLiteArray"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x0d, "CameraKing"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x00, "Unknown"}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct imx258_id_name imx258_lens_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x47, "Sunny 3923C"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x07, "Largen 9611A6"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x00, "Unknown"}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct regval imx258_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x0136, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x0137, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3051, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x6b11, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x7ff0, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x7ff1, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x7ff2, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x7ff3, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x7ff4, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x7ff5, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x7ff6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x7ff7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x7ff8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x7ff9, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x7ffa, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x7ffb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x7ffc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x7ffd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x7ffe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x7fff, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x7f76, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x7f77, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x7fa8, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x7fa9, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x7b24, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x7b25, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x6564, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x6b0d, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x653d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x6b05, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x6b06, 0xf9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x6b08, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x6b09, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x6b0a, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x6b0b, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x6700, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x6707, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x5f04, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x5f05, 0xed},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x94c7, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x94c8, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x94c9, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x95c7, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x95c8, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x95c9, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x94c4, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x94c5, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x94c6, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x95c4, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x95c5, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x95c6, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x94c1, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x94c2, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x94c3, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x95c1, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x95c2, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x95c3, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x94be, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x94bf, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x94c0, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x95be, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x95bf, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x95c0, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x94d0, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x94d1, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x94d2, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x95d0, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x95d1, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x95d2, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x94cd, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x94ce, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x94cf, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x95cd, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x95ce, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x95cf, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x94ca, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x94cb, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x94cc, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x95ca, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x95cb, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x95cc, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x900e, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x94e2, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x94e3, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x94e4, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x95e2, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x95e3, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x95e4, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x94df, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x94e0, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x94e1, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x95df, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x95e0, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x95e1, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x7fcc, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x7b78, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x9401, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x9403, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x9405, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x9406, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x9407, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x9408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x9409, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x940a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x940b, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x940d, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x940f, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x9411, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x9413, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x9415, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x9417, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x941d, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x941f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x9421, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x9423, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x9425, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x9427, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x9429, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x942b, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x942d, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x942f, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x9431, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x9433, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x9435, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x9437, 0x6b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x9439, 0x7c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x943b, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x9443, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x9445, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x9447, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x9449, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x944b, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x944d, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x944f, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x9451, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x9453, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x9455, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x9457, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x9459, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x945d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x945e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x945f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x946d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x946f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x9471, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x9473, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x9475, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x9477, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x9478, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x947b, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x947c, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x947d, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x947e, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x947f, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x9480, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x9483, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x9485, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x9487, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x9501, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x9503, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x9505, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x9507, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x9509, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x950b, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x950d, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x950f, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x9511, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x9513, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x9515, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x9517, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x951d, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x951f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x9521, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x9523, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x9525, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x9527, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x9529, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x952b, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x952d, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x952f, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x9531, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x9533, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x9535, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x9537, 0x6b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x9539, 0x7c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x953b, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x9543, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x9545, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x9547, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x9549, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x954b, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x954d, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x954f, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x9551, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x9553, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x9555, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x9557, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x9559, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x955d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x955e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x955f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x956d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x956f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x9571, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x9573, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x9575, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x9577, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x9578, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x957b, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x957c, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x957d, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x957e, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x957f, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x9580, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x9583, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x9585, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x9587, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x7f78, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x7f89, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x7f93, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x924b, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x924c, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x9304, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x9315, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x9250, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x9251, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x9252, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x0112, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x0113, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x0303, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x0305, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x0306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x0307, 0xa6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x0309, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x030b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x030d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x030e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x030f, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x0310, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x0820, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x0821, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x0822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x0823, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x4648, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x7420, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x7421, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x7422, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x7423, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x9104, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x0342, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x0343, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x0340, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x0341, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x0348, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x0349, 0x6f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x034a, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x034b, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x0381, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x0383, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x0385, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x0387, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x0900, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x0901, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x040a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x040b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x040c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x040d, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x040e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x040f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x3038, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x303a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x303b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x300d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x034c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x034d, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x034e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x034f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x0202, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x0203, 0x7e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x0204, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x0205, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x020e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x020f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x0210, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x0212, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x0213, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x0214, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x0215, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x7bcd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x94dc, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x94dd, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x94de, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x95dc, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x95dd, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x95de, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x7fb0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x9010, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x9419, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x941b, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x9519, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x951b, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x3030, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3032, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x0220, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * mipi_datarate per lane 600Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const struct regval imx258_2096x1560_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x0112, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x0113, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x0303, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x0305, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x0306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x0307, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x0309, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x030b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x030d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x030e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x030f, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x0310, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x0820, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x0821, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x0822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x0823, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x4648, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x7420, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x7421, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x7422, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x7423, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x9104, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x0342, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x0343, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x0340, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x0341, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x0348, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x0349, 0x6f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x034a, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x034b, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x0381, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x0383, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x0385, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x0387, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x0900, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x0901, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x0401, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x0405, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x0409, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x040a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x040b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x040c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x040d, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x040e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x040f, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x3038, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x303a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x303b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x300d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x034c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x034d, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x034e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x034f, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * max_framerate 7fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * mipi_datarate per lane 600Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static const struct regval imx258_4208x3120_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x0112, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x0113, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x0303, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x0305, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x0306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x0307, 0xa6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x0309, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x030b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x030d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x030e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x030f, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x0310, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x0820, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x0821, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x0822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x0823, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x4648, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x7420, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x7421, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x7422, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x7423, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x9104, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x0342, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x0343, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x0340, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x0341, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x0348, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x0349, 0x6f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x034a, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x034b, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x0381, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x0383, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x0385, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {0x0387, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0x0900, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x0901, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x040a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x040b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x040c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x040d, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x040e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x040f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x3038, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x303a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x303b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x300d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x034c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x034d, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x034e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x034f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const struct regval imx258_4208_3120_spd_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {0x3030, 0x01},//shield output size:80x1920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {0x3032, 0x01},//shield BYTE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #ifdef SPD_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /*DEBUG mode,spd data output with active pixel*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {0x7bcd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {0x0b00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {0x3051, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0x3052, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {0x7bca, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {0x7bcb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {0x7bc8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static const struct other_data imx258_full_spd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .width = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .height = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .bus_fmt = MEDIA_BUS_FMT_SPD_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static const struct other_data imx258_full_ebd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .width = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .height = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .bus_fmt = MEDIA_BUS_FMT_EBD_1X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static const struct imx258_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .width = 4208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .height = 3120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .denominator = 200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .exp_def = 0x0E7E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .hts_def = 0x14E8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .vts_def = 0x0E88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .reg_list = imx258_4208x3120_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .spd = &imx258_full_spd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .ebd = &imx258_full_ebd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .width = 2096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .height = 1560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .exp_def = 0x07BA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .hts_def = 0x14E8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .vts_def = 0x07C4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .reg_list = imx258_2096x1560_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .spd = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .ebd = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) IMX258_LINK_FREQ_498MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) IMX258_LINK_FREQ_399MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static const char * const imx258_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int imx258_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static int imx258_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ret = imx258_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) IMX258_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static int imx258_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static int imx258_get_reso_dist(const struct imx258_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static const struct imx258_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) imx258_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dist = imx258_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static int imx258_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct imx258 *imx258 = to_imx258(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) const struct imx258_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) mutex_lock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) mode = imx258_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) fmt->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) mutex_unlock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) imx258->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) __v4l2_ctrl_modify_range(imx258->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) __v4l2_ctrl_modify_range(imx258->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) IMX258_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (mode->width == 2096 && mode->height == 1560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) __v4l2_ctrl_s_ctrl(imx258->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) link_freq_menu_items[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) __v4l2_ctrl_s_ctrl_int64(imx258->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) IMX258_PIXEL_RATE_BINNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) __v4l2_ctrl_s_ctrl(imx258->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) link_freq_menu_items[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) __v4l2_ctrl_s_ctrl_int64(imx258->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) IMX258_PIXEL_RATE_FULL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) mutex_unlock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static int imx258_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct imx258 *imx258 = to_imx258(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) const struct imx258_mode *mode = imx258->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) mutex_lock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) mutex_unlock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) fmt->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* to csi rawwr3, other rawwr also can use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (fmt->pad == imx258->spd_id && mode->spd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) fmt->format.width = mode->spd->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) fmt->format.height = mode->spd->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) fmt->format.code = mode->spd->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) //Set the vc channel to be consistent with the valid data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) fmt->reserved[0] = V4L2_MBUS_CSI2_CHANNEL_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) } else if (fmt->pad == imx258->ebd_id && mode->ebd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) fmt->format.width = mode->ebd->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) fmt->format.height = mode->ebd->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) fmt->format.code = mode->ebd->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) //Set the vc channel to be consistent with the valid data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) fmt->reserved[0] = V4L2_MBUS_CSI2_CHANNEL_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) mutex_unlock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static int imx258_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) code->code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int imx258_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (fse->code != MEDIA_BUS_FMT_SRGGB10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static int imx258_enable_test_pattern(struct imx258 *imx258, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) val = (pattern - 1) | IMX258_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) val = IMX258_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return imx258_write_reg(imx258->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) IMX258_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) IMX258_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static int imx258_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct imx258 *imx258 = to_imx258(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) const struct imx258_mode *mode = imx258->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) mutex_lock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) mutex_unlock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static void imx258_get_otp(struct imx258_otp_info *otp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* fac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (otp->flag & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) inf->fac.flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) inf->fac.year = otp->year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) inf->fac.month = otp->month;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) inf->fac.day = otp->day;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) for (i = 0; i < ARRAY_SIZE(imx258_module_info) - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (imx258_module_info[i].id == otp->module_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) strscpy(inf->fac.module, imx258_module_info[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) sizeof(inf->fac.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) for (i = 0; i < ARRAY_SIZE(imx258_lens_info) - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (imx258_lens_info[i].id == otp->lens_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) strscpy(inf->fac.lens, imx258_lens_info[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) sizeof(inf->fac.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* awb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (otp->flag & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) inf->awb.flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) inf->awb.r_value = otp->rg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) inf->awb.b_value = otp->bg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) inf->awb.gr_value = 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) inf->awb.gb_value = 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) inf->awb.golden_r_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) inf->awb.golden_b_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) inf->awb.golden_gr_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) inf->awb.golden_gb_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* af */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (otp->flag & 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) inf->af.flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) inf->af.dir_cnt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) inf->af.af_otp[0].vcm_start = otp->vcm_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) inf->af.af_otp[0].vcm_end = otp->vcm_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) inf->af.af_otp[0].vcm_dir = otp->vcm_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* lsc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (otp->flag & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) inf->lsc.flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) inf->lsc.decimal_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) inf->lsc.lsc_w = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) inf->lsc.lsc_h = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) for (i = 0; i < 126; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) inf->lsc.lsc_r[i] = otp->lenc[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) inf->lsc.lsc_gr[i] = otp->lenc[i + 126];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) inf->lsc.lsc_gb[i] = otp->lenc[i + 252];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) inf->lsc.lsc_b[i] = otp->lenc[i + 378];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static void imx258_get_module_inf(struct imx258 *imx258,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct imx258_otp_info *otp = imx258->otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) strscpy(inf->base.sensor, IMX258_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) strscpy(inf->base.module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) imx258->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) strscpy(inf->base.lens, imx258->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (otp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) imx258_get_otp(otp, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static void imx258_set_awb_cfg(struct imx258 *imx258,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct rkmodule_awb_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) mutex_lock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) memcpy(&imx258->awb_cfg, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) mutex_unlock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static void imx258_set_lsc_cfg(struct imx258 *imx258,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct rkmodule_lsc_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) mutex_lock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) memcpy(&imx258->lsc_cfg, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) mutex_unlock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static long imx258_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct imx258 *imx258 = to_imx258(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct rkmodule_hdr_cfg *hdr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) imx258_get_module_inf(imx258, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) imx258_set_awb_cfg(imx258, (struct rkmodule_awb_cfg *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) case RKMODULE_LSC_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) imx258_set_lsc_cfg(imx258, (struct rkmodule_lsc_cfg *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = imx258_write_reg(imx258->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) IMX258_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) IMX258_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) IMX258_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ret = imx258_write_reg(imx258->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) IMX258_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) IMX258_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) IMX258_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) w = imx258->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) h = imx258->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) for (i = 0; i < imx258->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) imx258->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (i == imx258->cfg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) dev_err(&imx258->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) hdr_cfg->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) w = imx258->cur_mode->hts_def - imx258->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) h = imx258->cur_mode->vts_def - imx258->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) __v4l2_ctrl_modify_range(imx258->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) __v4l2_ctrl_modify_range(imx258->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) IMX258_VTS_MAX - imx258->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) dev_info(&imx258->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) "sensor mode: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) imx258->cur_mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) hdr_cfg->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) hdr_cfg->hdr_mode = imx258->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static long imx258_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct rkmodule_awb_cfg *awb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct rkmodule_lsc_cfg *lsc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ret = imx258_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) awb_cfg = kzalloc(sizeof(*awb_cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (!awb_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ret = copy_from_user(awb_cfg, up, sizeof(*awb_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) kfree(awb_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) ret = imx258_ioctl(sd, cmd, awb_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) kfree(awb_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) case RKMODULE_LSC_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) lsc_cfg = kzalloc(sizeof(*lsc_cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (!lsc_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ret = copy_from_user(lsc_cfg, up, sizeof(*lsc_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) kfree(lsc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ret = imx258_ioctl(sd, cmd, lsc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) kfree(lsc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ret = imx258_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ret = imx258_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ret = imx258_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static int imx258_apply_otp(struct imx258 *imx258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) int R_gain, G_gain, B_gain, base_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) struct i2c_client *client = imx258->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct imx258_otp_info *otp_ptr = imx258->otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct rkmodule_awb_cfg *awb_cfg = &imx258->awb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct rkmodule_lsc_cfg *lsc_cfg = &imx258->lsc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) u32 golden_bg_ratio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) u32 golden_rg_ratio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) u32 golden_g_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) u32 bg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) u32 rg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) //u32 g_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (awb_cfg->enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) golden_g_value = (awb_cfg->golden_gb_value +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) awb_cfg->golden_gr_value) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) golden_bg_ratio = awb_cfg->golden_b_value * 0x400 / golden_g_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) golden_rg_ratio = awb_cfg->golden_r_value * 0x400 / golden_g_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* apply OTP WB Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if ((otp_ptr->flag & 0x40) && golden_bg_ratio && golden_rg_ratio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) rg_ratio = otp_ptr->rg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) bg_ratio = otp_ptr->bg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) dev_dbg(&client->dev, "rg:0x%x,bg:0x%x,gol rg:0x%x,bg:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) rg_ratio, bg_ratio, golden_rg_ratio, golden_bg_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /* calculate G gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) R_gain = golden_rg_ratio * 1000 / rg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) B_gain = golden_bg_ratio * 1000 / bg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) G_gain = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (R_gain < 1000 || B_gain < 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (R_gain < B_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) base_gain = R_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) base_gain = B_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) base_gain = G_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) R_gain = 0x100 * R_gain / (base_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) B_gain = 0x100 * B_gain / (base_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) G_gain = 0x100 * G_gain / (base_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /* update sensor WB gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (R_gain > 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) imx258_write_reg(client, 0x0210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) IMX258_REG_VALUE_08BIT, R_gain >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) imx258_write_reg(client, 0x0211,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) IMX258_REG_VALUE_08BIT, R_gain & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (G_gain > 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) imx258_write_reg(client, 0x020e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) IMX258_REG_VALUE_08BIT, G_gain >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) imx258_write_reg(client, 0x020f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) IMX258_REG_VALUE_08BIT, G_gain & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) imx258_write_reg(client, 0x0214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) IMX258_REG_VALUE_08BIT, G_gain >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) imx258_write_reg(client, 0x0215,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) IMX258_REG_VALUE_08BIT, G_gain & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (B_gain > 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) imx258_write_reg(client, 0x0212,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) IMX258_REG_VALUE_08BIT, B_gain >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) imx258_write_reg(client, 0x0213,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) IMX258_REG_VALUE_08BIT, B_gain & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) dev_dbg(&client->dev, "apply awb gain: 0x%x, 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) R_gain, G_gain, B_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /* apply OTP Lenc Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if ((otp_ptr->flag & 0x10) && lsc_cfg->enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) for (i = 0; i < 504; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) imx258_write_reg(client, 0xA300 + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) IMX258_REG_VALUE_08BIT, otp_ptr->lenc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) dev_dbg(&client->dev, "apply lenc[%d]: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) i, otp_ptr->lenc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) //choose lsc table 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) imx258_write_reg(client, 0x3021,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) IMX258_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) //enable lsc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) imx258_write_reg(client, 0x0B00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) IMX258_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) /* apply OTP SPC Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (otp_ptr->flag & 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) for (i = 0; i < 63; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) imx258_write_reg(client, 0xD04C + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) IMX258_REG_VALUE_08BIT, otp_ptr->spc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) dev_dbg(&client->dev, "apply spc[%d]: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) i, otp_ptr->spc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) imx258_write_reg(client, 0xD08C + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) IMX258_REG_VALUE_08BIT, otp_ptr->spc[i + 63]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) dev_dbg(&client->dev, "apply spc[%d]: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) i + 63, otp_ptr->spc[i + 63]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) //enable spc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) imx258_write_reg(client, 0x7BC8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) IMX258_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) static int __imx258_start_stream(struct imx258 *imx258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ret = imx258_write_array(imx258->client, imx258->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) mutex_unlock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) ret = v4l2_ctrl_handler_setup(&imx258->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) mutex_lock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (imx258->otp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) ret = imx258_apply_otp(imx258);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (imx258->cur_mode->width == 4208 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) imx258->cur_mode->height == 3120 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) imx258->cur_mode->spd != NULL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) imx258->spd_id < PAD_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ret = imx258_write_array(imx258->client, imx258_4208_3120_spd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return imx258_write_reg(imx258->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) IMX258_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) IMX258_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) IMX258_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static int __imx258_stop_stream(struct imx258 *imx258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return imx258_write_reg(imx258->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) IMX258_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) IMX258_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) IMX258_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static int imx258_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) struct imx258 *imx258 = to_imx258(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) struct i2c_client *client = imx258->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) mutex_lock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (on == imx258->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ret = __imx258_start_stream(imx258);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) __imx258_stop_stream(imx258);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) imx258->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) mutex_unlock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) static int imx258_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) struct imx258 *imx258 = to_imx258(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) struct i2c_client *client = imx258->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) mutex_lock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (imx258->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) ret = imx258_write_array(imx258->client, imx258_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) imx258->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) imx258->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) mutex_unlock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static inline u32 imx258_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return DIV_ROUND_UP(cycles, IMX258_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static int __imx258_power_on(struct imx258 *imx258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) struct device *dev = &imx258->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (!IS_ERR_OR_NULL(imx258->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) ret = pinctrl_select_state(imx258->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) imx258->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) ret = clk_set_rate(imx258->xvclk, IMX258_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (clk_get_rate(imx258->xvclk) != IMX258_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) ret = clk_prepare_enable(imx258->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (!IS_ERR(imx258->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) gpiod_set_value_cansleep(imx258->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) ret = regulator_bulk_enable(IMX258_NUM_SUPPLIES, imx258->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (!IS_ERR(imx258->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) gpiod_set_value_cansleep(imx258->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (!IS_ERR(imx258->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) gpiod_set_value_cansleep(imx258->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) delay_us = imx258_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) clk_disable_unprepare(imx258->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static void __imx258_power_off(struct imx258 *imx258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (!IS_ERR(imx258->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) gpiod_set_value_cansleep(imx258->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) clk_disable_unprepare(imx258->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (!IS_ERR(imx258->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) gpiod_set_value_cansleep(imx258->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (!IS_ERR_OR_NULL(imx258->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ret = pinctrl_select_state(imx258->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) imx258->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) dev_dbg(&imx258->client->dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) regulator_bulk_disable(IMX258_NUM_SUPPLIES, imx258->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static int imx258_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) struct imx258 *imx258 = to_imx258(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) return __imx258_power_on(imx258);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) static int imx258_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) struct imx258 *imx258 = to_imx258(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) __imx258_power_off(imx258);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static int imx258_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) struct imx258 *imx258 = to_imx258(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) const struct imx258_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) mutex_lock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) try_fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) mutex_unlock(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static int imx258_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) static int imx258_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) val = 1 << (IMX258_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) static const struct dev_pm_ops imx258_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) SET_RUNTIME_PM_OPS(imx258_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) imx258_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) static const struct v4l2_subdev_internal_ops imx258_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .open = imx258_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) static const struct v4l2_subdev_core_ops imx258_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .s_power = imx258_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .ioctl = imx258_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .compat_ioctl32 = imx258_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) static const struct v4l2_subdev_video_ops imx258_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .s_stream = imx258_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .g_frame_interval = imx258_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) static const struct v4l2_subdev_pad_ops imx258_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .enum_mbus_code = imx258_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .enum_frame_size = imx258_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .enum_frame_interval = imx258_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .get_fmt = imx258_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .set_fmt = imx258_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .get_mbus_config = imx258_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static const struct v4l2_subdev_ops imx258_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .core = &imx258_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .video = &imx258_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .pad = &imx258_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) static int imx258_set_gain_reg(struct imx258 *imx258, u32 a_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) u32 gain_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) gain_reg = (512 - (512 * 512 / a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (gain_reg > 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) gain_reg = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) ret = imx258_write_reg(imx258->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) IMX258_REG_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) IMX258_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) ((gain_reg & 0x100) >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) ret |= imx258_write_reg(imx258->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) IMX258_REG_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) IMX258_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) (gain_reg & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) static int imx258_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) struct imx258 *imx258 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) struct imx258, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) struct i2c_client *client = imx258->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) max = imx258->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) __v4l2_ctrl_modify_range(imx258->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) imx258->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) imx258->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) imx258->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) ret = imx258_write_reg(imx258->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) IMX258_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) IMX258_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) ret = imx258_set_gain_reg(imx258, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) ret = imx258_write_reg(imx258->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) IMX258_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) IMX258_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) ctrl->val + imx258->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) ret = imx258_enable_test_pattern(imx258, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static const struct v4l2_ctrl_ops imx258_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .s_ctrl = imx258_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static int imx258_initialize_controls(struct imx258 *imx258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) const struct imx258_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) handler = &imx258->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) mode = imx258->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) handler->lock = &imx258->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) imx258->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) V4L2_CID_LINK_FREQ, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) imx258->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) V4L2_CID_PIXEL_RATE, 0, IMX258_PIXEL_RATE_FULL_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) 1, IMX258_PIXEL_RATE_FULL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) imx258->hblank = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) V4L2_CID_HBLANK, h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) if (imx258->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) imx258->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) imx258->vblank = v4l2_ctrl_new_std(handler, &imx258_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) IMX258_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) imx258->exposure = v4l2_ctrl_new_std(handler, &imx258_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) V4L2_CID_EXPOSURE, IMX258_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) exposure_max, IMX258_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) imx258->anal_gain = v4l2_ctrl_new_std(handler, &imx258_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) V4L2_CID_ANALOGUE_GAIN, IMX258_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) IMX258_GAIN_MAX, IMX258_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) IMX258_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) imx258->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) &imx258_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) ARRAY_SIZE(imx258_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) 0, 0, imx258_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) dev_err(&imx258->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) imx258->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) static int imx258_check_sensor_id(struct imx258 *imx258,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) struct device *dev = &imx258->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) ret = imx258_read_reg(client, IMX258_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) IMX258_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) static int imx258_configure_regulators(struct imx258 *imx258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) for (i = 0; i < IMX258_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) imx258->supplies[i].supply = imx258_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) return devm_regulator_bulk_get(&imx258->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) IMX258_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) imx258->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) static int imx258_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct imx258 *imx258;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) struct device_node *eeprom_ctrl_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) struct i2c_client *eeprom_ctrl_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) struct v4l2_subdev *eeprom_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) struct imx258_otp_info *otp_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) imx258 = devm_kzalloc(dev, sizeof(*imx258), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (!imx258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) &imx258->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) &imx258->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) &imx258->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) &imx258->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) imx258->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) imx258->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) imx258->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) imx258->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (IS_ERR(imx258->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) imx258->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) if (IS_ERR(imx258->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) imx258->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) if (IS_ERR(imx258->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) ret = of_property_read_u32(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) "rockchip,spd-id",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) &imx258->spd_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) imx258->spd_id = PAD_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) "failed get spd_id, will not to use spd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) ret = of_property_read_u32(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) "rockchip,ebd-id",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) &imx258->ebd_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) imx258->ebd_id = PAD_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) "failed get ebd_id, will not to use ebd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) ret = imx258_configure_regulators(imx258);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) imx258->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (!IS_ERR(imx258->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) imx258->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) pinctrl_lookup_state(imx258->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (IS_ERR(imx258->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) imx258->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) pinctrl_lookup_state(imx258->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (IS_ERR(imx258->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) mutex_init(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) sd = &imx258->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) v4l2_i2c_subdev_init(sd, client, &imx258_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) ret = imx258_initialize_controls(imx258);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) ret = __imx258_power_on(imx258);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) ret = imx258_check_sensor_id(imx258, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) eeprom_ctrl_node = of_parse_phandle(node, "eeprom-ctrl", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) if (eeprom_ctrl_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) eeprom_ctrl_client =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) of_find_i2c_device_by_node(eeprom_ctrl_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) of_node_put(eeprom_ctrl_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (IS_ERR_OR_NULL(eeprom_ctrl_client)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) dev_err(dev, "can not get node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) goto continue_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) eeprom_ctrl = i2c_get_clientdata(eeprom_ctrl_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) if (IS_ERR_OR_NULL(eeprom_ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) dev_err(dev, "can not get eeprom i2c client\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) otp_ptr = devm_kzalloc(dev, sizeof(*otp_ptr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (!otp_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) ret = v4l2_subdev_call(eeprom_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) core, ioctl, 0, otp_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) imx258->otp = otp_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) imx258->otp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) devm_kfree(dev, otp_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) continue_probe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) sd->internal_ops = &imx258_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) imx258->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) ret = media_entity_pads_init(&sd->entity, 1, &imx258->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) if (strcmp(imx258->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) imx258->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) IMX258_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) __imx258_power_off(imx258);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) v4l2_ctrl_handler_free(&imx258->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) mutex_destroy(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) static int imx258_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) struct imx258 *imx258 = to_imx258(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) v4l2_ctrl_handler_free(&imx258->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) mutex_destroy(&imx258->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) __imx258_power_off(imx258);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) static const struct of_device_id imx258_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) { .compatible = "sony,imx258" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) MODULE_DEVICE_TABLE(of, imx258_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) static const struct i2c_device_id imx258_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) { "sony,imx258", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static struct i2c_driver imx258_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .name = IMX258_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .pm = &imx258_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .of_match_table = of_match_ptr(imx258_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .probe = &imx258_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .remove = &imx258_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .id_table = imx258_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) return i2c_add_driver(&imx258_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) i2c_del_driver(&imx258_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) MODULE_DESCRIPTION("Sony imx258 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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