^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * imx214 camera driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 fix compile errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X02 add 4lane mode support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "imx214_eeprom_head.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX214_LINK_FREQ_600MHZ 600000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX214_PIXEL_RATE (IMX214_LINK_FREQ_600MHZ * 2LL * 4LL / 10LL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX214_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CHIP_ID 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX214_REG_CHIP_ID 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX214_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX214_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX214_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX214_REG_EXPOSURE 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX214_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX214_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX214_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX214_REG_GAIN_H 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX214_REG_GAIN_L 0x0205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX214_GAIN_MIN 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX214_GAIN_MAX 0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX214_GAIN_STEP 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX214_GAIN_DEFAULT 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX214_REG_TEST_PATTERN 0x5e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX214_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX214_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX214_REG_VTS 0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX214_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX214_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX214_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX214_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX214_NAME "imx214"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX214_MEDIA_BUS_FMT MEDIA_BUS_FMT_SBGGR10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* OTP MACRO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MODULE_BKX 0X01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MODULE_TYPE MODULE_BKX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #if MODULE_TYPE == MODULE_BKX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RG_Ratio_Typical_Default (0x026e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BG_Ratio_Typical_Default (0x0280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RG_Ratio_Typical_Default (0x16f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define BG_Ratio_Typical_Default (0x16f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const char * const imx214_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX214_NUM_SUPPLIES ARRAY_SIZE(imx214_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct imx214_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 link_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct imx214 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct regulator_bulk_data supplies[IMX214_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct v4l2_fwnode_endpoint bus_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const struct imx214_mode *support_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const struct imx214_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct imx214_otp_info *otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct rkmodule_inf module_inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct rkmodule_awb_cfg awb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct rkmodule_lsc_cfg lsc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define to_imx214(sd) container_of(sd, struct imx214, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct imx214_id_name {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) char name[RKMODULE_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct imx214_id_name imx214_module_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x36, "GuangDongLiteArray"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x0d, "CameraKing"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x00, "Unknown"}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct imx214_id_name imx214_lens_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x47, "Sunny 3923C"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x07, "Largen 9611A6"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x00, "Unknown"}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct regval imx214_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x0136, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x0137, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x0101, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x0105, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x0106, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x4550, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x4601, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x4642, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x6227, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x6276, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x900E, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0xA802, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0xA803, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0xA804, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0xA805, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0xA806, 0xAE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0xA807, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0xA808, 0xAE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0xA809, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0xA80A, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0xA80B, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0xAE33, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x4174, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x4175, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x4612, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x461B, 0x2C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x461F, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x4635, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x4637, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x463F, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x4641, 0x0D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x465B, 0x2C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x465F, 0x2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x4663, 0x2B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x4667, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x466F, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x470E, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x4909, 0xAB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x490B, 0x95},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x4915, 0x5D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x4A5F, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x4A61, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x4A73, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x4A85, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x4A87, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x583C, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x620E, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x6EB2, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x6EB3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x9300, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const struct regval imx214_2104x1560_30fps_regs_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x0114, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x0220, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x0221, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x0222, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x0340, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x0341, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x0342, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x0343, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x0348, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x0349, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x034A, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x034B, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x0381, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x0383, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x0385, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x0387, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x0900, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x0901, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x0902, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3000, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3054, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x305C, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x0112, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x0113, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x034C, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x034D, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x034E, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x034F, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x040A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x040B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x040C, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x040D, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x040E, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x040F, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x0303, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x0305, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x0306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x0307, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x0309, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x030B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x0310, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x0820, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x0821, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x0822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x0823, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x3A03, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3A04, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3A05, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x0B06, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x30A2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x30B4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3A02, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3011, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3013, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x4170, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x4171, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x4176, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x4177, 0x3C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0xAE20, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0xAE21, 0x5C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct regval imx214_4208x3120_15fps_regs_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x0114, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x0220, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x0221, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x0222, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x0340, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x0341, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x0342, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x0343, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x0348, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x0349, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x034A, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x034B, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x0381, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x0383, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x0385, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x0387, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x0900, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x0901, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x0902, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x3000, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x3054, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x305C, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x0112, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x0113, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x034C, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x034D, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x034E, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x034F, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x040A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x040B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x040C, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x040D, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x040E, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x040F, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x0303, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x0305, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x0306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x0307, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x0309, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x030B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x0310, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x0820, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x0821, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x0822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x0823, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x3A03, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x3A04, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3A05, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x0B06, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x30A2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x30B4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x3A02, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x3011, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3013, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x4170, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x4171, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x4176, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x4177, 0x3C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0xAE20, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0xAE21, 0x5C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct regval imx214_2104x1560_30fps_regs_4lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x0220, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x0221, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x0222, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x0340, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x0341, 0x3E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x0342, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x0343, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x0348, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x0349, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x034A, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x034B, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x0381, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x0383, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x0385, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x0387, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x0900, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x0901, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x0902, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x3000, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x3054, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x305C, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x0112, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x0113, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x034C, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x034D, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x034E, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x034F, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x040A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x040B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x040C, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x040D, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x040E, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x040F, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x0303, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x0305, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x0306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x0307, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x0309, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x030B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x0310, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x0820, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x0821, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x0822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x0823, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x3A03, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x3A04, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x3A05, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x0B06, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x30A2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x30B4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x3A02, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x3011, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x3013, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x0202, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x0203, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x0224, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x0225, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x0204, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x0205, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x020E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x020F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x0210, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x0212, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x0213, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x0214, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x0215, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x0216, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x0217, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x4170, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x4171, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x4176, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x4177, 0x3C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0xAE20, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0xAE21, 0x5C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x0138, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static const struct regval imx214_4208x3120_30fps_regs_4lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x0114, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x0220, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x0221, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x0222, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x0340, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x0341, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x0342, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x0343, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x0344, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x0345, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x0346, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x0347, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x0348, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x0349, 0x6F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x034A, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x034B, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x0381, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x0383, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x0385, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x0387, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x0900, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x0901, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x0902, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x3000, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x3054, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x305C, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x0112, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x0113, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x034C, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x034D, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x034E, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x034F, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x0401, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x0404, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x0405, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x0408, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x0409, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x040A, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x040B, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x040C, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x040D, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x040E, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x040F, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x0301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x0303, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x0305, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x0306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x0307, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x0309, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x030B, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x0310, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x0820, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x0821, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x0822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x0823, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x3A03, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x3A04, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x3A05, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x0B06, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x30A2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x30B4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x3A02, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x3011, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x3013, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x0202, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x0203, 0x4E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x0224, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x0225, 0xF4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x0204, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x0205, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x020E, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x020F, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x0210, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x0212, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x0213, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x0214, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x0215, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x0216, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x0217, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x4170, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x4171, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x4176, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x4177, 0x3C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0xAE20, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0xAE21, 0x5C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static const struct imx214_mode supported_modes_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .width = 4208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .height = 3120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .denominator = 150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .exp_def = 0x0c70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .hts_def = 0x1390,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .vts_def = 0x0c7a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .reg_list = imx214_4208x3120_15fps_regs_2lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .width = 2104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .height = 1560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .exp_def = 0x0630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .hts_def = 0x1390,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .vts_def = 0x0640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .reg_list = imx214_2104x1560_30fps_regs_2lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const struct imx214_mode supported_modes_4lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .width = 4208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .height = 3120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .exp_def = 0x0c50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .hts_def = 0x1390,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .vts_def = 0x0c58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .reg_list = imx214_4208x3120_30fps_regs_4lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .width = 2104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .height = 1560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .exp_def = 0x083a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .hts_def = 0x1390,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .vts_def = 0x083E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .reg_list = imx214_2104x1560_30fps_regs_4lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const s64 link_freq_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) IMX214_LINK_FREQ_600MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const char * const imx214_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int imx214_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static int imx214_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret = imx214_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) IMX214_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static int imx214_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int imx214_get_reso_dist(const struct imx214_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static const struct imx214_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) imx214_find_best_fit(struct imx214 *imx214, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) for (i = 0; i < imx214->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dist = imx214_get_reso_dist(&imx214->support_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return &imx214->support_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static int imx214_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct imx214 *imx214 = to_imx214(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) const struct imx214_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u32 lane_num = imx214->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) mutex_lock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) mode = imx214_find_best_fit(imx214, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) fmt->format.code = IMX214_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) mutex_unlock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) imx214->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) __v4l2_ctrl_modify_range(imx214->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) __v4l2_ctrl_modify_range(imx214->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) IMX214_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) __v4l2_ctrl_s_ctrl_int64(imx214->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) __v4l2_ctrl_s_ctrl(imx214->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mode->link_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) mutex_unlock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static int imx214_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct imx214 *imx214 = to_imx214(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) const struct imx214_mode *mode = imx214->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) mutex_lock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) mutex_unlock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) fmt->format.code = IMX214_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) mutex_unlock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static int imx214_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) code->code = IMX214_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static int imx214_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct imx214 *imx214 = to_imx214(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (fse->index >= imx214->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (fse->code != IMX214_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) fse->min_width = imx214->support_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) fse->max_width = imx214->support_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) fse->max_height = imx214->support_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) fse->min_height = imx214->support_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static int imx214_enable_test_pattern(struct imx214 *imx214, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) val = (pattern - 1) | IMX214_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) val = IMX214_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return imx214_write_reg(imx214->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) IMX214_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) IMX214_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static int imx214_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct imx214 *imx214 = to_imx214(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) const struct imx214_mode *mode = imx214->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) mutex_lock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) mutex_unlock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static void imx214_get_otp(struct imx214_otp_info *otp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* fac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (otp->flag & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) inf->fac.flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) inf->fac.year = otp->year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) inf->fac.month = otp->month;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) inf->fac.day = otp->day;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) for (i = 0; i < ARRAY_SIZE(imx214_module_info) - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (imx214_module_info[i].id == otp->module_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) strscpy(inf->fac.module, imx214_module_info[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) sizeof(inf->fac.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) for (i = 0; i < ARRAY_SIZE(imx214_lens_info) - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (imx214_lens_info[i].id == otp->lens_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) strscpy(inf->fac.lens, imx214_lens_info[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) sizeof(inf->fac.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* awb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (otp->flag & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) inf->awb.flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) inf->awb.r_value = otp->rg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) inf->awb.b_value = otp->bg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) inf->awb.gr_value = 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) inf->awb.gb_value = 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) inf->awb.golden_r_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) inf->awb.golden_b_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) inf->awb.golden_gr_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) inf->awb.golden_gb_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* af */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (otp->flag & 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) inf->af.flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) inf->af.af_otp[0].vcm_start = otp->vcm_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) inf->af.af_otp[0].vcm_end = otp->vcm_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) inf->af.af_otp[0].vcm_dir = otp->vcm_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* lsc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (otp->flag & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) inf->lsc.flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) inf->lsc.decimal_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) inf->lsc.lsc_w = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) inf->lsc.lsc_h = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) for (i = 0; i < 126; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) inf->lsc.lsc_r[i] = otp->lenc[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) inf->lsc.lsc_gr[i] = otp->lenc[i + 126];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) inf->lsc.lsc_gb[i] = otp->lenc[i + 252];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) inf->lsc.lsc_b[i] = otp->lenc[i + 378];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static void imx214_get_module_inf(struct imx214 *imx214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct imx214_otp_info *otp = imx214->otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) strscpy(inf->base.sensor, IMX214_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) strscpy(inf->base.module, imx214->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) strscpy(inf->base.lens, imx214->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (otp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) imx214_get_otp(otp, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static void imx214_set_awb_cfg(struct imx214 *imx214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct rkmodule_awb_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) mutex_lock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) memcpy(&imx214->awb_cfg, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) mutex_unlock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static void imx214_set_lsc_cfg(struct imx214 *imx214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct rkmodule_lsc_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) mutex_lock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) memcpy(&imx214->lsc_cfg, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) mutex_unlock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static long imx214_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct imx214 *imx214 = to_imx214(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) imx214_get_module_inf(imx214, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) imx214_set_awb_cfg(imx214, (struct rkmodule_awb_cfg *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) case RKMODULE_LSC_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) imx214_set_lsc_cfg(imx214, (struct rkmodule_lsc_cfg *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ret = imx214_write_reg(imx214->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) IMX214_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) IMX214_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) IMX214_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ret = imx214_write_reg(imx214->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) IMX214_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) IMX214_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) IMX214_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static long imx214_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct rkmodule_lsc_cfg *lsc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ret = imx214_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ret = imx214_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) case RKMODULE_LSC_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) lsc_cfg = kzalloc(sizeof(*lsc_cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (!lsc_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ret = copy_from_user(lsc_cfg, up, sizeof(*lsc_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ret = imx214_ioctl(sd, cmd, lsc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) kfree(lsc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ret = imx214_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static int imx214_apply_otp(struct imx214 *imx214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) int R_gain, G_gain, B_gain, base_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct i2c_client *client = imx214->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct imx214_otp_info *otp_ptr = imx214->otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct rkmodule_awb_cfg *awb_cfg = &imx214->awb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct rkmodule_lsc_cfg *lsc_cfg = &imx214->lsc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) u32 golden_bg_ratio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) u32 golden_rg_ratio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) u32 golden_g_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) u32 bg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) u32 rg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) //u32 g_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (!otp_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (awb_cfg->enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) golden_g_value = (awb_cfg->golden_gb_value +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) awb_cfg->golden_gr_value) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (golden_g_value != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) golden_rg_ratio = awb_cfg->golden_r_value * 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) / golden_g_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) golden_bg_ratio = awb_cfg->golden_b_value * 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) / golden_g_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) golden_rg_ratio = RG_Ratio_Typical_Default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) golden_bg_ratio = BG_Ratio_Typical_Default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* apply OTP WB Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if ((otp_ptr->flag & 0x40) && golden_bg_ratio && golden_rg_ratio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) rg_ratio = otp_ptr->rg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) bg_ratio = otp_ptr->bg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) dev_dbg(&client->dev, "rg:0x%x,bg:0x%x,gol rg:0x%x,bg:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) rg_ratio, bg_ratio, golden_rg_ratio, golden_bg_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* calculate G gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) R_gain = golden_rg_ratio * 1000 / rg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) B_gain = golden_bg_ratio * 1000 / bg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) G_gain = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (R_gain < 1000 || B_gain < 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (R_gain < B_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) base_gain = R_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) base_gain = B_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) base_gain = G_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) R_gain = 0x100 * R_gain / (base_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) B_gain = 0x100 * B_gain / (base_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) G_gain = 0x100 * G_gain / (base_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* update sensor WB gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (R_gain > 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) imx214_write_reg(client, 0x0210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) IMX214_REG_VALUE_08BIT, R_gain >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) imx214_write_reg(client, 0x0211,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) IMX214_REG_VALUE_08BIT, R_gain & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (G_gain > 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) imx214_write_reg(client, 0x020e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) IMX214_REG_VALUE_08BIT, G_gain >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) imx214_write_reg(client, 0x020f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) IMX214_REG_VALUE_08BIT, G_gain & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) imx214_write_reg(client, 0x0214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) IMX214_REG_VALUE_08BIT, G_gain >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) imx214_write_reg(client, 0x0215,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) IMX214_REG_VALUE_08BIT, G_gain & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (B_gain > 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) imx214_write_reg(client, 0x0212,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) IMX214_REG_VALUE_08BIT, B_gain >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) imx214_write_reg(client, 0x0213,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) IMX214_REG_VALUE_08BIT, B_gain & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) dev_dbg(&client->dev, "apply awb gain: 0x%x, 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) R_gain, G_gain, B_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* apply OTP Lenc Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if ((otp_ptr->flag & 0x10) && lsc_cfg->enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) for (i = 0; i < 504; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) imx214_write_reg(client, 0xA300 + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) IMX214_REG_VALUE_08BIT, otp_ptr->lenc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) dev_dbg(&client->dev, "apply lenc[%d]: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) i, otp_ptr->lenc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) //choose lsc table 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) imx214_write_reg(client, 0x3021,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) IMX214_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) //enable lsc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) imx214_write_reg(client, 0x0B00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) IMX214_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* apply OTP SPC Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (otp_ptr->flag & 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) for (i = 0; i < 63; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) imx214_write_reg(client, 0xD04C + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) IMX214_REG_VALUE_08BIT, otp_ptr->spc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) dev_dbg(&client->dev, "apply spc[%d]: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) i, otp_ptr->spc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) imx214_write_reg(client, 0xD08C + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) IMX214_REG_VALUE_08BIT, otp_ptr->spc[i + 63]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) dev_dbg(&client->dev, "apply spc[%d]: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) i + 63, otp_ptr->spc[i + 63]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) //enable spc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) imx214_write_reg(client, 0x7BC8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) IMX214_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static int __imx214_start_stream(struct imx214 *imx214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ret = imx214_write_array(imx214->client, imx214->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) mutex_unlock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ret = v4l2_ctrl_handler_setup(&imx214->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) mutex_lock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ret = imx214_apply_otp(imx214);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return imx214_write_reg(imx214->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) IMX214_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) IMX214_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) IMX214_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static int __imx214_stop_stream(struct imx214 *imx214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return imx214_write_reg(imx214->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) IMX214_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) IMX214_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) IMX214_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static int imx214_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct imx214 *imx214 = to_imx214(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct i2c_client *client = imx214->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) imx214->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) imx214->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) DIV_ROUND_CLOSEST(imx214->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) imx214->cur_mode->max_fps.numerator));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) mutex_lock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (on == imx214->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) ret = __imx214_start_stream(imx214);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) __imx214_stop_stream(imx214);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) imx214->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) mutex_unlock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static int imx214_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) struct imx214 *imx214 = to_imx214(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) struct i2c_client *client = imx214->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) mutex_lock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (imx214->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ret = imx214_write_array(imx214->client, imx214_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) imx214->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) imx214->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) mutex_unlock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static inline u32 imx214_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) return DIV_ROUND_UP(cycles, IMX214_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static int __imx214_power_on(struct imx214 *imx214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct device *dev = &imx214->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (!IS_ERR(imx214->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) gpiod_set_value_cansleep(imx214->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (!IS_ERR_OR_NULL(imx214->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ret = pinctrl_select_state(imx214->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) imx214->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ret = clk_set_rate(imx214->xvclk, IMX214_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (clk_get_rate(imx214->xvclk) != IMX214_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ret = clk_prepare_enable(imx214->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (!IS_ERR(imx214->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) gpiod_set_value_cansleep(imx214->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ret = regulator_bulk_enable(IMX214_NUM_SUPPLIES, imx214->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (!IS_ERR(imx214->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) gpiod_set_value_cansleep(imx214->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (!IS_ERR(imx214->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) gpiod_set_value_cansleep(imx214->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) delay_us = imx214_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) clk_disable_unprepare(imx214->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static void __imx214_power_off(struct imx214 *imx214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct device *dev = &imx214->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (!IS_ERR(imx214->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) gpiod_set_value_cansleep(imx214->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) clk_disable_unprepare(imx214->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (!IS_ERR(imx214->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) gpiod_set_value_cansleep(imx214->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (!IS_ERR_OR_NULL(imx214->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) ret = pinctrl_select_state(imx214->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) imx214->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (!IS_ERR(imx214->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) gpiod_set_value_cansleep(imx214->power_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) regulator_bulk_disable(IMX214_NUM_SUPPLIES, imx214->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static int imx214_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) struct imx214 *imx214 = to_imx214(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) return __imx214_power_on(imx214);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static int imx214_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) struct imx214 *imx214 = to_imx214(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) __imx214_power_off(imx214);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static int imx214_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) struct imx214 *imx214 = to_imx214(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) const struct imx214_mode *def_mode = &imx214->support_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) mutex_lock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) try_fmt->code = IMX214_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) mutex_unlock(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static int imx214_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) struct imx214 *imx214 = to_imx214(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (fie->index >= imx214->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (fie->code != IMX214_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) fie->width = imx214->support_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) fie->height = imx214->support_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) fie->interval = imx214->support_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static int imx214_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) struct imx214 *imx214 = to_imx214(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) u32 lane_num = imx214->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) val = 1 << (lane_num - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define DST_WIDTH_2096 2096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define DST_HEIGHT_1560 1560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static int imx214_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) struct imx214 *imx214 = to_imx214(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (imx214->cur_mode->width == 2104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) sel->r.left = CROP_START(imx214->cur_mode->width, DST_WIDTH_2096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) sel->r.width = DST_WIDTH_2096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) sel->r.top = CROP_START(imx214->cur_mode->height, DST_HEIGHT_1560);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) sel->r.height = DST_HEIGHT_1560;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) sel->r.left = CROP_START(imx214->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) imx214->cur_mode->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) sel->r.width = imx214->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) sel->r.top = CROP_START(imx214->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) imx214->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) sel->r.height = imx214->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static const struct dev_pm_ops imx214_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) SET_RUNTIME_PM_OPS(imx214_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) imx214_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static const struct v4l2_subdev_internal_ops imx214_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .open = imx214_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static const struct v4l2_subdev_core_ops imx214_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .s_power = imx214_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .ioctl = imx214_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .compat_ioctl32 = imx214_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static const struct v4l2_subdev_video_ops imx214_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .s_stream = imx214_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .g_frame_interval = imx214_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) static const struct v4l2_subdev_pad_ops imx214_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .enum_mbus_code = imx214_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .enum_frame_size = imx214_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .enum_frame_interval = imx214_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .get_fmt = imx214_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .set_fmt = imx214_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .get_selection = imx214_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .get_mbus_config = imx214_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static const struct v4l2_subdev_ops imx214_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .core = &imx214_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .video = &imx214_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .pad = &imx214_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) static int imx214_set_gain_reg(struct imx214 *imx214, u32 a_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) u32 gain_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) gain_reg = (512 - (512 * 512 / a_gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (gain_reg > 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) gain_reg = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ret = imx214_write_reg(imx214->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) IMX214_REG_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) IMX214_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) ((gain_reg & 0x100) >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ret |= imx214_write_reg(imx214->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) IMX214_REG_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) IMX214_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) (gain_reg & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static int imx214_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) struct imx214 *imx214 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) struct imx214, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) struct i2c_client *client = imx214->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) max = imx214->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) __v4l2_ctrl_modify_range(imx214->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) imx214->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) imx214->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) imx214->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) ret = imx214_write_reg(imx214->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) IMX214_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) IMX214_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) ret = imx214_set_gain_reg(imx214, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) ret = imx214_write_reg(imx214->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) IMX214_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) IMX214_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) ctrl->val + imx214->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) ret = imx214_enable_test_pattern(imx214, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) static const struct v4l2_ctrl_ops imx214_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .s_ctrl = imx214_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) static int imx214_initialize_controls(struct imx214 *imx214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) const struct imx214_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) u32 lane_num = imx214->bus_cfg.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) handler = &imx214->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) mode = imx214->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) handler->lock = &imx214->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) imx214->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) 1, 0, link_freq_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) dst_pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) imx214->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) 0, IMX214_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) __v4l2_ctrl_s_ctrl(imx214->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) mode->link_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) imx214->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (imx214->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) imx214->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) imx214->vblank = v4l2_ctrl_new_std(handler, &imx214_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) IMX214_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) imx214->exposure = v4l2_ctrl_new_std(handler, &imx214_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) V4L2_CID_EXPOSURE, IMX214_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) exposure_max, IMX214_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) imx214->anal_gain = v4l2_ctrl_new_std(handler, &imx214_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) V4L2_CID_ANALOGUE_GAIN, IMX214_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) IMX214_GAIN_MAX, IMX214_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) IMX214_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) imx214->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) &imx214_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) ARRAY_SIZE(imx214_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) 0, 0, imx214_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) dev_err(&imx214->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) imx214->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static int imx214_check_sensor_id(struct imx214 *imx214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) struct device *dev = &imx214->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) ret = imx214_read_reg(client, IMX214_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) IMX214_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) dev_info(dev, "Detected OV%04x sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) static int imx214_configure_regulators(struct imx214 *imx214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) for (i = 0; i < IMX214_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) imx214->supplies[i].supply = imx214_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) return devm_regulator_bulk_get(&imx214->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) IMX214_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) imx214->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) static int imx214_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) struct imx214 *imx214;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) struct device_node *eeprom_ctrl_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) struct i2c_client *eeprom_ctrl_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) struct v4l2_subdev *eeprom_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) struct imx214_otp_info *otp_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) imx214 = devm_kzalloc(dev, sizeof(*imx214), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) if (!imx214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) &imx214->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) &imx214->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) &imx214->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) &imx214->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) imx214->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) &imx214->bus_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) dev_err(dev, "Failed to get bus cfg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (imx214->bus_cfg.bus.mipi_csi2.num_data_lanes == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) imx214->support_modes = supported_modes_4lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) imx214->cfg_num = ARRAY_SIZE(supported_modes_4lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) imx214->support_modes = supported_modes_2lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) imx214->cfg_num = ARRAY_SIZE(supported_modes_2lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) imx214->cur_mode = &imx214->support_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) imx214->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) if (IS_ERR(imx214->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) imx214->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) if (IS_ERR(imx214->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) imx214->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) if (IS_ERR(imx214->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) imx214->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) if (IS_ERR(imx214->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) ret = imx214_configure_regulators(imx214);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) imx214->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (!IS_ERR(imx214->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) imx214->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) pinctrl_lookup_state(imx214->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (IS_ERR(imx214->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) imx214->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) pinctrl_lookup_state(imx214->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) if (IS_ERR(imx214->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) mutex_init(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) sd = &imx214->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) v4l2_i2c_subdev_init(sd, client, &imx214_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ret = imx214_initialize_controls(imx214);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) ret = __imx214_power_on(imx214);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) ret = imx214_check_sensor_id(imx214, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) eeprom_ctrl_node = of_parse_phandle(node, "eeprom-ctrl", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if (eeprom_ctrl_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) eeprom_ctrl_client =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) of_find_i2c_device_by_node(eeprom_ctrl_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) of_node_put(eeprom_ctrl_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (IS_ERR_OR_NULL(eeprom_ctrl_client)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) dev_err(dev, "can not get node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) goto continue_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) eeprom_ctrl = i2c_get_clientdata(eeprom_ctrl_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) if (IS_ERR_OR_NULL(eeprom_ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) dev_err(dev, "can not get eeprom i2c client\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) otp_ptr = devm_kzalloc(dev, sizeof(*otp_ptr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (!otp_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ret = v4l2_subdev_call(eeprom_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) core, ioctl, 0, otp_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) imx214->otp = otp_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) imx214->otp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) devm_kfree(dev, otp_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) continue_probe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) sd->internal_ops = &imx214_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) imx214->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) ret = media_entity_pads_init(&sd->entity, 1, &imx214->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (strcmp(imx214->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) imx214->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) IMX214_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) __imx214_power_off(imx214);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) v4l2_ctrl_handler_free(&imx214->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) mutex_destroy(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static int imx214_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) struct imx214 *imx214 = to_imx214(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) v4l2_ctrl_handler_free(&imx214->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) mutex_destroy(&imx214->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) __imx214_power_off(imx214);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) static const struct of_device_id imx214_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) { .compatible = "sony,imx214" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) MODULE_DEVICE_TABLE(of, imx214_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) static const struct i2c_device_id imx214_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) { "sony,imx214", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) static struct i2c_driver imx214_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .name = IMX214_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .pm = &imx214_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .of_match_table = of_match_ptr(imx214_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .probe = &imx214_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .remove = &imx214_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .id_table = imx214_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) return i2c_add_driver(&imx214_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) i2c_del_driver(&imx214_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) MODULE_DESCRIPTION("Sony imx214 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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