^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * hi556 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 init version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-image-sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* verify default register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) //#define CHECK_REG_VALUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MIPI_FREQ 440000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HI556_PIXEL_RATE (440000000LL * 2LL * 2LL / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HI556_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CHIP_ID 0x0556
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HI556_REG_CHIP_ID 0x0f16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HI556_REG_CTRL_MODE 0x0A00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HI556_MODE_SW_STANDBY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HI556_MODE_STREAMING 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HI556_REG_EXPOSURE_H 0x0073
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HI556_REG_EXPOSURE_M 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HI556_REG_EXPOSURE_L 0x0075
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HI556_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 16) & 0xF) /* 4 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HI556_FETCH_MIDDLE_BYTE_EXP(VAL) (((VAL) >> 8) & 0xFF) /* 8 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HI556_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 8 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HI556_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HI556_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HI556_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HI556_REG_GAIN 0x0077
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HI556_GAIN_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ANALOG_GAIN_MIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ANALOG_GAIN_MAX 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ANALOG_GAIN_DEFAULT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HI556_REG_GROUP 0x0046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HI556_REG_TEST_PATTERN 0x0A05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HI556_TEST_PATTERN_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HI556_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HI556_REG_TEST_PATTERN_SELECT 0x0201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HI556_REG_VTS 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HI556_FLIP_MIRROR_REG 0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HI556_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x01 : VAL & 0xfe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HI556_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x02 : VAL & 0xfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DELAY_MS 0xEEEE /* Array delay token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HI556_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HI556_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HI556_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HI556_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HI556_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HI556_NAME "hi556"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HI556_MEDIA_BUS_FMT MEDIA_BUS_FMT_SGBRG10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct hi556_otp_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int flag; // bit[7]: info, bit[6]:wb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int lens_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int month;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int day;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int rg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int bg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const char * const hi556_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HI556_NUM_SUPPLIES ARRAY_SIZE(hi556_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct hi556_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct hi556 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct regulator_bulk_data supplies[HI556_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) const struct hi556_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct hi556_otp_info *otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct rkmodule_awb_cfg awb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define to_hi556(sd) container_of(sd, struct hi556, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Pclk 176Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * linelength 2816(0xb00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * framelength 1988(0x7c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * grabwindow_width 2592
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * grabwindow_height 1944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * MIPI speed(Mbps) : 840Mbps x 2Lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct regval hi556_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x0a00, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x0e00, 0x0102},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x0e02, 0x0102},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x0e0c, 0x0100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x2000, 0x7400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x2002, 0x001c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x2004, 0x0242},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x2006, 0x0942},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x2008, 0x7007},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x200a, 0x0fd9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x200c, 0x0259},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x200e, 0x7008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x2010, 0x160e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x2012, 0x0047},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x2014, 0x2118},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x2016, 0x0041},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x2018, 0x00d8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x201a, 0x0145},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x201c, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x201e, 0x0181},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x2020, 0x13cc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x2022, 0x2057},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x2024, 0x7001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x2026, 0x0fca},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x2028, 0x00cb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x202a, 0x009f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x202c, 0x7002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x202e, 0x13cc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x2030, 0x019b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x2032, 0x014d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x2034, 0x2987},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x2036, 0x2766},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x2038, 0x0020},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x203a, 0x2060},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x203c, 0x0e5d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x203e, 0x181d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x2040, 0x2066},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x2042, 0x20c4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x2044, 0x5000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x2046, 0x0005},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x2048, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x204a, 0x01db},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x204c, 0x025a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x204e, 0x00c0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x2050, 0x0005},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x2052, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x2054, 0x0ad9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x2056, 0x0259},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x2058, 0x0618},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x205a, 0x0258},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x205c, 0x2266},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x205e, 0x20c8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x2060, 0x2060},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x2062, 0x707b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x2064, 0x0fdd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x2066, 0x81b8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x2068, 0x5040},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x206a, 0x0020},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x206c, 0x5060},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x206e, 0x3143},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x2070, 0x5081},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x2072, 0x025c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x2074, 0x7800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x2076, 0x7400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x2078, 0x001c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x207a, 0x0242},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x207c, 0x0942},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x207e, 0x0bd9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x2080, 0x0259},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x2082, 0x7008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x2084, 0x160e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x2086, 0x0047},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x2088, 0x2118},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x208a, 0x0041},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x208c, 0x00d8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x208e, 0x0145},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x2090, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x2092, 0x0181},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x2094, 0x13cc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x2096, 0x2057},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x2098, 0x7001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x209a, 0x0fca},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x209c, 0x00cb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x209e, 0x009f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x20a0, 0x7002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x20a2, 0x13cc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x20a4, 0x019b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x20a6, 0x014d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x20a8, 0x2987},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x20aa, 0x2766},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x20ac, 0x0020},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x20ae, 0x2060},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x20b0, 0x0e5d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x20b2, 0x181d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x20b4, 0x2066},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x20b6, 0x20c4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x20b8, 0x50a0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x20ba, 0x0005},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x20bc, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x20be, 0x01db},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x20c0, 0x025a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x20c2, 0x00c0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x20c4, 0x0005},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x20c6, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x20c8, 0x0ad9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x20ca, 0x0259},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x20cc, 0x0618},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x20ce, 0x0258},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x20d0, 0x2266},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x20d2, 0x20c8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x20d4, 0x2060},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x20d6, 0x707b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x20d8, 0x0fdd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x20da, 0x86b8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x20dc, 0x50e0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x20de, 0x0020},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x20e0, 0x5100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x20e2, 0x3143},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x20e4, 0x5121},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x20e6, 0x7800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x20e8, 0x3140},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x20ea, 0x01c4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x20ec, 0x01c1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x20ee, 0x01c0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x20f0, 0x01c4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x20f2, 0x2700},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x20f4, 0x3d40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x20f6, 0x7800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x20f8, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x27fe, 0xe000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x3000, 0x60f8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x3002, 0x187f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3004, 0x7060},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3006, 0x0114},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x3008, 0x60b0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x300a, 0x1473},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x300c, 0x0013},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x300e, 0x140f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x3010, 0x0040},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x3012, 0x100f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x3014, 0x60f8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x3016, 0x187f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x3018, 0x7060},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x301a, 0x0114},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x301c, 0x60b0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x301e, 0x1473},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3020, 0x0013},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3022, 0x140f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x3024, 0x0040},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x3026, 0x000f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x0b00, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x0b02, 0x0045},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x0b04, 0xb405},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x0b06, 0xc403},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x0b08, 0x0081},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x0b0a, 0x8252},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x0b0c, 0xf814},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x0b0e, 0xc618},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x0b10, 0xa828},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x0b12, 0x004c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x0b14, 0x4068},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x0b16, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x0f30, 0x6e25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x0f32, 0x7067},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x0954, 0x0009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x0956, 0x1100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x0958, 0xcc80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x095a, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x0c00, 0x1110},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x0c02, 0x0011},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x0c04, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x0c06, 0x0200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x0c10, 0x0040},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x0c12, 0x0040},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x0c14, 0x0040},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x0c16, 0x0040},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x0a10, 0x4000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3068, 0xf800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x306a, 0xf876},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x006c, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x005e, 0x0200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x000e, 0x0100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x0e0a, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x004a, 0x0100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x004c, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x004e, 0x0100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x000c, 0x0022},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x0008, 0x0b00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x005a, 0x0202},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x0012, 0x000e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x0018, 0x0a31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x0022, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x0028, 0x0017},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x0024, 0x0028},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x002a, 0x002d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x0026, 0x0030},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x002c, 0x07c7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x002e, 0x1111},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x0030, 0x1111},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x0032, 0x1111},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x0006, 0x0823},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x0a22, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x0a12, 0x0a20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x0a14, 0x0798},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x003e, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x0074, 0x0821},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x0070, 0x0411},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x0002, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x0a02, 0x0100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x0a24, 0x0100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x0076, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x0060, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x0062, 0x0530},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x0064, 0x0500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x0066, 0x0530},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x0068, 0x0500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x0122, 0x0300},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x015a, 0xff08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x0804, 0x0200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x005c, 0x0102},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x0a1a, 0x0800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x003c, 0x0101}, //fix framerate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Pclk 210Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * linelength 2816
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * framelength 2083
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * grabwindow_width 2592
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * grabwindow_height 1944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * MIPI speed(Mbps): 880Mbps x 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const struct regval hi556_2592x1944_regs_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x0a00, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x0b0a, 0x8252},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x0f30, 0x6e25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x0f32, 0x7067},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x004a, 0x0100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x004c, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x004e, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x000c, 0x0022},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x0008, 0x0b00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x005a, 0x0202},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x0012, 0x000e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x0018, 0x0a31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x0022, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x0028, 0x0017},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x0024, 0x0028},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x002a, 0x002d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x0026, 0x0030},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x002c, 0x07c7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x002e, 0x1111},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x0030, 0x1111},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x0032, 0x1111},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x0006, 0x0823},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x0a22, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x0a12, 0x0a20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x0a14, 0x0798},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x003e, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x0804, 0x0200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x0a04, 0x014a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x090c, 0x0fdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x090e, 0x002d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x0902, 0x4319},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x0914, 0xc10a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x0916, 0x071f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x0918, 0x0408},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x091a, 0x0c0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x091c, 0x0f09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x091e, 0x0a00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) //{0x0a00, 0x0100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const struct hi556_mode supported_modes_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .width = 2592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .height = 1944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .exp_def = 0x0810,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .hts_def = 0x0B00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .vts_def = 0x0823,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .reg_list = hi556_2592x1944_regs_2lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct hi556_mode *supported_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MIPI_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static const char * const hi556_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) "Solid color bar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "100% color bars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "Fade to gray color bars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) "PN9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "Horizental/Vertical gradient",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "Check board",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) "Slant",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "Resolution",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static int hi556_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_dbg(&client->dev, "%s(%d) enter!\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (i2c_master_send(client, buf, len + 2) != len + 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) "write reg(0x%x val:0x%x)failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int hi556_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int i, delay_ms, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (regs[i].addr == DELAY_MS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) delay_ms = regs[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev_info(&client->dev, "delay(%d) ms !\n", delay_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) usleep_range(1000 * delay_ms, 1000 * delay_ms + 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = hi556_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) HI556_REG_VALUE_16BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dev_err(&client->dev, "%s failed !\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int hi556_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Check Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #ifdef CHECK_REG_VALUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int hi556_reg_verify(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = hi556_read_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) HI556_REG_VALUE_16BIT, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (value != regs[i].val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dev_info(&client->dev, "%s: 0x%04x is 0x%x instead of 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) __func__, regs[i].addr, value, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int hi556_get_reso_dist(const struct hi556_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const struct hi556_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) hi556_find_best_fit(struct hi556 *hi556,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) for (i = 0; i < hi556->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dist = hi556_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int hi556_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct hi556 *hi556 = to_hi556(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) const struct hi556_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) mutex_lock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mode = hi556_find_best_fit(hi556, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) fmt->format.code = HI556_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) mutex_unlock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) hi556->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) __v4l2_ctrl_modify_range(hi556->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) __v4l2_ctrl_modify_range(hi556->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) HI556_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) mutex_unlock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static int hi556_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct hi556 *hi556 = to_hi556(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) const struct hi556_mode *mode = hi556->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mutex_lock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) mutex_unlock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) fmt->format.code = HI556_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mutex_unlock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int hi556_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) code->code = HI556_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int hi556_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct hi556 *hi556 = to_hi556(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (fse->index >= hi556->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (fse->code != HI556_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int hi556_enable_test_pattern(struct hi556 *hi556, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (pattern) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) hi556_write_reg(hi556->client, HI556_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) HI556_REG_VALUE_08BIT, HI556_TEST_PATTERN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) hi556_write_reg(hi556->client, HI556_REG_TEST_PATTERN_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) HI556_REG_VALUE_08BIT, 0x01 << (pattern - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) hi556_write_reg(hi556->client, HI556_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) HI556_REG_VALUE_08BIT, HI556_TEST_PATTERN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static int hi556_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct hi556 *hi556 = to_hi556(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) const struct hi556_mode *mode = hi556->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static int hi556_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u32 val = 1 << (HI556_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static void hi556_get_module_inf(struct hi556 *hi556,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) strscpy(inf->base.sensor, HI556_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) strscpy(inf->base.module, hi556->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) strscpy(inf->base.lens, hi556->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static void hi556_set_awb_cfg(struct hi556 *hi556,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct rkmodule_awb_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) mutex_lock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) memcpy(&hi556->awb_cfg, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) mutex_unlock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static long hi556_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct hi556 *hi556 = to_hi556(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) hi556_get_module_inf(hi556, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) hi556_set_awb_cfg(hi556, (struct rkmodule_awb_cfg *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ret = hi556_write_reg(hi556->client, HI556_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) HI556_REG_VALUE_08BIT, HI556_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = hi556_write_reg(hi556->client, HI556_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) HI556_REG_VALUE_08BIT, HI556_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static long hi556_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct rkmodule_awb_cfg *awb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ret = hi556_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) awb_cfg = kzalloc(sizeof(*awb_cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!awb_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (copy_from_user(awb_cfg, up, sizeof(*awb_cfg))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) kfree(awb_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ret = hi556_ioctl(sd, cmd, awb_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) kfree(awb_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (copy_from_user(&stream, up, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ret = hi556_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static int __hi556_start_stream(struct hi556 *hi556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = hi556_write_array(hi556->client, hi556->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #ifdef CHECK_REG_VALUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* verify default values to make sure everything has */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* been written correctly as expected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dev_info(&hi556->client->dev, "%s:Check register value!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ret = hi556_reg_verify(hi556->client, hi556_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ret = hi556_reg_verify(hi556->client, hi556->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) mutex_unlock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ret = v4l2_ctrl_handler_setup(&hi556->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) mutex_lock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) dev_info(&hi556->client->dev, "APPly otp failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ret = hi556_write_reg(hi556->client, HI556_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) HI556_REG_VALUE_08BIT, HI556_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static int __hi556_stop_stream(struct hi556 *hi556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return hi556_write_reg(hi556->client, HI556_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) HI556_REG_VALUE_08BIT, HI556_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static int hi556_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct hi556 *hi556 = to_hi556(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct i2c_client *client = hi556->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) hi556->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) hi556->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) DIV_ROUND_CLOSEST(hi556->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) hi556->cur_mode->max_fps.numerator));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) mutex_lock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (on == hi556->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) dev_info(&client->dev, "stream on!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ret = __hi556_start_stream(hi556);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dev_info(&client->dev, "stream off!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) __hi556_stop_stream(hi556);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) hi556->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) mutex_unlock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static int hi556_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct hi556 *hi556 = to_hi556(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct i2c_client *client = hi556->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dev_info(&client->dev, "%s(%d) on(%d)\n", __func__, __LINE__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) mutex_lock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (hi556->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ret = hi556_write_array(hi556->client, hi556_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) hi556->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) hi556->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) mutex_unlock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static inline u32 hi556_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return DIV_ROUND_UP(cycles, HI556_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static int __hi556_power_on(struct hi556 *hi556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct device *dev = &hi556->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (!IS_ERR(hi556->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) gpiod_set_value_cansleep(hi556->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (!IS_ERR_OR_NULL(hi556->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ret = pinctrl_select_state(hi556->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) hi556->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ret = clk_set_rate(hi556->xvclk, HI556_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (clk_get_rate(hi556->xvclk) != HI556_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ret = clk_prepare_enable(hi556->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ret = regulator_bulk_enable(HI556_NUM_SUPPLIES, hi556->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (!IS_ERR(hi556->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) gpiod_set_value_cansleep(hi556->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (!IS_ERR(hi556->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) gpiod_set_value_cansleep(hi556->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) delay_us = hi556_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) clk_disable_unprepare(hi556->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static void __hi556_power_off(struct hi556 *hi556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct device *dev = &hi556->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (!IS_ERR(hi556->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) gpiod_set_value_cansleep(hi556->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) clk_disable_unprepare(hi556->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (!IS_ERR(hi556->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) gpiod_set_value_cansleep(hi556->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (!IS_ERR_OR_NULL(hi556->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ret = pinctrl_select_state(hi556->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) hi556->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!IS_ERR(hi556->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) gpiod_set_value_cansleep(hi556->power_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) regulator_bulk_disable(HI556_NUM_SUPPLIES, hi556->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static int hi556_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct hi556 *hi556 = to_hi556(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return __hi556_power_on(hi556);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static int hi556_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct hi556 *hi556 = to_hi556(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) __hi556_power_off(hi556);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static int hi556_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct hi556 *hi556 = to_hi556(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) const struct hi556_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) mutex_lock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) try_fmt->code = HI556_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) mutex_unlock(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static int hi556_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct hi556 *hi556 = to_hi556(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (fie->index >= hi556->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (fie->code != HI556_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static const struct dev_pm_ops hi556_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) SET_RUNTIME_PM_OPS(hi556_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) hi556_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static const struct v4l2_subdev_internal_ops hi556_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .open = hi556_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static const struct v4l2_subdev_core_ops hi556_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .s_power = hi556_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .ioctl = hi556_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .compat_ioctl32 = hi556_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static const struct v4l2_subdev_video_ops hi556_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .s_stream = hi556_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .g_frame_interval = hi556_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static const struct v4l2_subdev_pad_ops hi556_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .enum_mbus_code = hi556_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .enum_frame_size = hi556_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .enum_frame_interval = hi556_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .get_fmt = hi556_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .set_fmt = hi556_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .get_mbus_config = hi556_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static const struct v4l2_subdev_ops hi556_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .core = &hi556_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .video = &hi556_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .pad = &hi556_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static int hi556_set_exposure_reg(struct hi556 *hi556, u32 exposure)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) u32 cal_shutter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) cal_shutter = exposure >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) cal_shutter = cal_shutter << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) ret = hi556_write_reg(hi556->client, HI556_REG_GROUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) HI556_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ret |= hi556_write_reg(hi556->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) HI556_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) HI556_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) HI556_FETCH_HIGH_BYTE_EXP(cal_shutter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ret |= hi556_write_reg(hi556->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) HI556_REG_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) HI556_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) HI556_FETCH_MIDDLE_BYTE_EXP(cal_shutter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) ret |= hi556_write_reg(hi556->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) HI556_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) HI556_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) HI556_FETCH_LOW_BYTE_EXP(cal_shutter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ret |= hi556_write_reg(hi556->client, HI556_REG_GROUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) HI556_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static int hi556_set_gain_reg(struct hi556 *hi556, u32 a_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ret = hi556_write_reg(hi556->client, HI556_REG_GROUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) HI556_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ret |= hi556_write_reg(hi556->client, HI556_REG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) HI556_REG_VALUE_08BIT, a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ret |= hi556_write_reg(hi556->client, HI556_REG_GROUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) HI556_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static int hi556_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) struct hi556 *hi556 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct hi556, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct i2c_client *client = hi556->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) max = hi556->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) __v4l2_ctrl_modify_range(hi556->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) hi556->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) hi556->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) hi556->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) dev_dbg(&client->dev, "set exposure value 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) ret = hi556_set_exposure_reg(hi556, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dev_dbg(&client->dev, "set analog gain value 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ret = hi556_set_gain_reg(hi556, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) dev_dbg(&client->dev, "set vb value 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) ret = hi556_write_reg(hi556->client, HI556_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) HI556_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ctrl->val + hi556->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ret = hi556_enable_test_pattern(hi556, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ret = hi556_read_reg(hi556->client, HI556_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) HI556_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ret |= hi556_write_reg(hi556->client, HI556_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) HI556_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) HI556_FETCH_MIRROR(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) ret = hi556_read_reg(hi556->client, HI556_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) HI556_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) ret |= hi556_write_reg(hi556->client, HI556_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) HI556_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) HI556_FETCH_FLIP(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static const struct v4l2_ctrl_ops hi556_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .s_ctrl = hi556_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static int hi556_initialize_controls(struct hi556 *hi556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) const struct hi556_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) handler = &hi556->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) mode = hi556->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) handler->lock = &hi556->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) 0, hi556->pixel_rate, 1, hi556->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) hi556->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (hi556->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) hi556->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) hi556->vblank = v4l2_ctrl_new_std(handler, &hi556_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) HI556_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) hi556->exposure = v4l2_ctrl_new_std(handler, &hi556_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) V4L2_CID_EXPOSURE, HI556_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) exposure_max, HI556_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) hi556->anal_gain = v4l2_ctrl_new_std(handler, &hi556_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) hi556->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) &hi556_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) ARRAY_SIZE(hi556_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) 0, 0, hi556_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) v4l2_ctrl_new_std(handler, &hi556_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) v4l2_ctrl_new_std(handler, &hi556_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) dev_err(&hi556->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) hi556->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) static int hi556_check_sensor_id(struct hi556 *hi556,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) struct device *dev = &hi556->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ret = hi556_read_reg(client, HI556_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) HI556_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) dev_info(dev, "Detected Hi%04x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static int hi556_configure_regulators(struct hi556 *hi556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) for (i = 0; i < HI556_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) hi556->supplies[i].supply = hi556_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return devm_regulator_bulk_get(&hi556->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) HI556_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) hi556->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static int hi556_parse_of(struct hi556 *hi556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct device *dev = &hi556->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) fwnode = of_fwnode_handle(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (rval <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) dev_warn(dev, " Get mipi lane num failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) hi556->lane_num = rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (hi556->lane_num == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) hi556->cur_mode = &supported_modes_2lane[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) supported_modes = supported_modes_2lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) hi556->cfg_num = ARRAY_SIZE(supported_modes_2lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) hi556->pixel_rate = MIPI_FREQ * 2U * hi556->lane_num / 8U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) hi556->lane_num, hi556->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) dev_err(dev, "unsupported lane_num(%d)\n", hi556->lane_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static int hi556_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) struct hi556 *hi556;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) char facing[2] = "b";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) hi556 = devm_kzalloc(dev, sizeof(*hi556), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (!hi556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) &hi556->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) dev_warn(dev, "could not get module index!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) hi556->module_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) &hi556->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) &hi556->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) &hi556->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) hi556->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) hi556->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (IS_ERR(hi556->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) hi556->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (IS_ERR(hi556->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) hi556->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (IS_ERR(hi556->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) dev_warn(dev, "Failed to get reset-gpios, maybe no use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) hi556->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (IS_ERR(hi556->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) ret = hi556_configure_regulators(hi556);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) ret = hi556_parse_of(hi556);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) hi556->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (!IS_ERR(hi556->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) hi556->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) pinctrl_lookup_state(hi556->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (IS_ERR(hi556->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) hi556->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) pinctrl_lookup_state(hi556->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (IS_ERR(hi556->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) mutex_init(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) sd = &hi556->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) v4l2_i2c_subdev_init(sd, client, &hi556_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) ret = hi556_initialize_controls(hi556);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) ret = __hi556_power_on(hi556);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) ret = hi556_check_sensor_id(hi556, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) dev_info(&client->dev, "%s(%d) Check id failed\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) "check following information:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) "Power/PowerDown/Reset/Mclk/I2cBus !!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) sd->internal_ops = &hi556_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) hi556->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) ret = media_entity_pads_init(&sd->entity, 1, &hi556->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (strcmp(hi556->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) hi556->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) HI556_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) __hi556_power_off(hi556);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) v4l2_ctrl_handler_free(&hi556->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) mutex_destroy(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static int hi556_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) struct hi556 *hi556 = to_hi556(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) v4l2_ctrl_handler_free(&hi556->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) mutex_destroy(&hi556->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) __hi556_power_off(hi556);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) static const struct of_device_id hi556_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) { .compatible = "hynix,hi556" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) MODULE_DEVICE_TABLE(of, hi556_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static const struct i2c_device_id hi556_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) { "hynix,hi556", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) static struct i2c_driver hi556_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .name = HI556_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .pm = &hi556_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .of_match_table = of_match_ptr(hi556_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .probe = &hi556_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .remove = &hi556_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .id_table = hi556_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) return i2c_add_driver(&hi556_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) i2c_del_driver(&hi556_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) MODULE_DESCRIPTION("Hynix hi556 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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