^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * gc5035 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 init driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * TODO: add OTP function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X04 fix vb and gain set issues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * V0.0X01.0X05 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GC5035_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GC5035_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GC5035_LINK_FREQ_MHZ 438000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MIPI_FREQ 438000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GC5035_PIXEL_RATE (MIPI_FREQ * 2LL * 2LL / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GC5035_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CHIP_ID 0x5035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GC5035_REG_CHIP_ID_H 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GC5035_REG_CHIP_ID_L 0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GC5035_REG_SET_PAGE 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GC5035_SET_PAGE_ONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GC5035_REG_CTRL_MODE 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GC5035_MODE_SW_STANDBY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GC5035_MODE_STREAMING 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GC5035_REG_EXPOSURE_H 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GC5035_REG_EXPOSURE_L 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GC5035_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 8) & 0x0F) /* 4 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GC5035_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 8 Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GC5035_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GC5035_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GC5035_VTS_MAX 0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GC5035_REG_AGAIN 0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GC5035_REG_DGAIN_INT 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GC5035_REG_DGAIN_FRAC 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GC5035_GAIN_MIN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GC5035_GAIN_MAX 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GC5035_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GC5035_GAIN_DEFAULT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GC5035_REG_VTS_H 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GC5035_REG_VTS_L 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define REG_NULL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GC5035_NAME "gc5035"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const char * const gc5035_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GC5035_NUM_SUPPLIES ARRAY_SIZE(gc5035_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMAGE_NORMAL_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DD_PARAM_QTY_5035 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define INFO_ROM_START_5035 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define INFO_WIDTH_5035 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define WB_ROM_START_5035 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define WB_WIDTH_5035 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GOLDEN_ROM_START_5035 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GOLDEN_WIDTH_5035 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define WINDOW_WIDTH 0x0a30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WINDOW_HEIGHT 0x079c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* SENSOR MIRROR FLIP INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GC5035_MIRROR_FLIP_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #if GC5035_MIRROR_FLIP_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GC5035_MIRROR 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GC5035_RSTDUMMY1 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GC5035_RSTDUMMY2 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GC5035_MIRROR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GC5035_RSTDUMMY1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GC5035_RSTDUMMY2 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct gc5035_otp_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 flag; //bit[7]: info bit[6]:wb bit[3]:dd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 lens_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u16 vcm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u16 vcm_driver_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 month;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 day;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 rg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 bg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 golden_rg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 golden_bg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u16 dd_param_x[DD_PARAM_QTY_5035];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u16 dd_param_y[DD_PARAM_QTY_5035];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u16 dd_param_type[DD_PARAM_QTY_5035];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u16 dd_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct gc5035_id_name {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) char name[RKMODULE_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct gc5035_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct gc5035 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct regulator_bulk_data supplies[GC5035_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) const struct gc5035_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned int lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 Dgain_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct gc5035_otp_info *otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct rkmodule_inf module_inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct rkmodule_awb_cfg awb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define to_gc5035(sd) container_of(sd, struct gc5035, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct regval gc5035_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* SYSTEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0xfc, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0xf4, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0xf5, 0xe9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0xf6, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0xf8, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0xf9, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0xfa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0xfc, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x36, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0xd3, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x36, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x33, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0xfe, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x01, 0xe7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0xf7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0xfc, 0x8f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0xfc, 0x8f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0xfc, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0xee, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x87, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x8c, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Analog & CISCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x05, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x06, 0xda},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x9d, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x09, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x0a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x0b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x0c, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x0d, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x0e, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x0f, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x10, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x11, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x17, GC5035_MIRROR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x19, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0xfe, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x30, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x31, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0xd9, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x1b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x21, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x28, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x29, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x44, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x4b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x4e, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x50, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x52, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x53, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x55, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x5b, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0xc5, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x8c, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0xfe, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x33, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x32, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x91, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x92, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x93, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x95, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x96, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0xd5, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x97, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x16, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x1a, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x1f, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x20, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x46, 0xe3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x4a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x54, GC5035_RSTDUMMY1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x62, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x72, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x73, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x7a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x7d, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x90, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0xce, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0xd0, 0xb2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0xd2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0xe6, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0xfe, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x12, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x13, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x14, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x15, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x22, GC5035_RSTDUMMY2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x91, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x92, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x93, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x94, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0xfc, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0xfe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0xfc, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0xfc, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0xfe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0xfc, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0xb0, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0xb1, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0xb2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0xb3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0xb4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0xb6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x53, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x89, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x60, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x87, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* BLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x42, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x49, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x4a, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x4b, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x55, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Anti_blooming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x41, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x4c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x4d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x4e, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x44, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x48, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Crop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x91, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x92, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x93, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x94, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x95, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x96, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x97, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x98, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x99, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* MIPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0xfe, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x02, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x03, 0xb7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x15, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x18, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x21, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x22, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x23, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x24, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x25, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x26, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x29, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x2a, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x2b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x8c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x3e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * mipi_datarate per lane 876Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const struct regval gc5035_2592x1944_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* lane snap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const struct gc5035_mode supported_modes_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .width = 2592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .height = 1944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .exp_def = 0x07C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .hts_def = 0x0B68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .vts_def = 0x07D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .reg_list = gc5035_2592x1944_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct gc5035_mode *supported_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) GC5035_LINK_FREQ_MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int gc5035_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) "gc5035 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int gc5035_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret = gc5035_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int gc5035_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "gc5035 read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int gc5035_get_reso_dist(const struct gc5035_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const struct gc5035_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) gc5035_find_best_fit(struct gc5035 *gc5035,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) for (i = 0; i < gc5035->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dist = gc5035_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int gc5035_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct gc5035 *gc5035 = to_gc5035(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) const struct gc5035_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mutex_lock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) mode = gc5035_find_best_fit(gc5035, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) fmt->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mutex_unlock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) gc5035->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) __v4l2_ctrl_modify_range(gc5035->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) __v4l2_ctrl_modify_range(gc5035->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) GC5035_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mutex_unlock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int gc5035_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct gc5035 *gc5035 = to_gc5035(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) const struct gc5035_mode *mode = gc5035->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) mutex_lock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) mutex_unlock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) fmt->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mutex_unlock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int gc5035_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) code->code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int gc5035_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct gc5035 *gc5035 = to_gc5035(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (fse->index >= gc5035->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (fse->code != MEDIA_BUS_FMT_SRGGB10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int gc5035_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct gc5035 *gc5035 = to_gc5035(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) const struct gc5035_mode *mode = gc5035->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mutex_lock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mutex_unlock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static void gc5035_get_module_inf(struct gc5035 *gc5035,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) strlcpy(inf->base.sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) GC5035_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) strlcpy(inf->base.module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) gc5035->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) strlcpy(inf->base.lens,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) gc5035->len_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static void gc5035_set_module_inf(struct gc5035 *gc5035,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct rkmodule_awb_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) mutex_lock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) memcpy(&gc5035->awb_cfg, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) mutex_unlock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static long gc5035_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct gc5035 *gc5035 = to_gc5035(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) gc5035_get_module_inf(gc5035, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) gc5035_set_module_inf(gc5035, (struct rkmodule_awb_cfg *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) GC5035_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) GC5035_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret |= gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) GC5035_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) GC5035_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) GC5035_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) GC5035_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret |= gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) GC5035_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) GC5035_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static long gc5035_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ret = gc5035_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ret = gc5035_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ret = gc5035_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static int __gc5035_start_stream(struct gc5035 *gc5035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ret = gc5035_write_array(gc5035->client, gc5035->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mutex_unlock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ret = v4l2_ctrl_handler_setup(&gc5035->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mutex_lock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ret = gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) GC5035_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) GC5035_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ret |= gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) GC5035_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) GC5035_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int __gc5035_stop_stream(struct gc5035 *gc5035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) GC5035_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) GC5035_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ret |= gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) GC5035_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) GC5035_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static int gc5035_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct gc5035 *gc5035 = to_gc5035(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct i2c_client *client = gc5035->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) mutex_lock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (on == gc5035->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = __gc5035_start_stream(gc5035);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) __gc5035_stop_stream(gc5035);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) gc5035->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) mutex_unlock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static int gc5035_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct gc5035 *gc5035 = to_gc5035(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct i2c_client *client = gc5035->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) mutex_lock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (gc5035->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ret = gc5035_write_array(gc5035->client, gc5035_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) gc5035->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) gc5035->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) mutex_unlock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static inline u32 gc5035_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return DIV_ROUND_UP(cycles, GC5035_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static int __gc5035_power_on(struct gc5035 *gc5035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct device *dev = &gc5035->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (!IS_ERR_OR_NULL(gc5035->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ret = pinctrl_select_state(gc5035->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) gc5035->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = clk_set_rate(gc5035->xvclk, GC5035_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (clk_get_rate(gc5035->xvclk) != GC5035_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = clk_prepare_enable(gc5035->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (!IS_ERR(gc5035->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) gpiod_set_value_cansleep(gc5035->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = regulator_bulk_enable(GC5035_NUM_SUPPLIES, gc5035->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (!IS_ERR(gc5035->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) gpiod_set_value_cansleep(gc5035->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (!IS_ERR(gc5035->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) gpiod_set_value_cansleep(gc5035->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) delay_us = gc5035_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) clk_disable_unprepare(gc5035->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static void __gc5035_power_off(struct gc5035 *gc5035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (!IS_ERR(gc5035->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) gpiod_set_value_cansleep(gc5035->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) clk_disable_unprepare(gc5035->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (!IS_ERR(gc5035->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) gpiod_set_value_cansleep(gc5035->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (!IS_ERR_OR_NULL(gc5035->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ret = pinctrl_select_state(gc5035->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) gc5035->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_dbg(&gc5035->client->dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) regulator_bulk_disable(GC5035_NUM_SUPPLIES, gc5035->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static int gc5035_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct gc5035 *gc5035 = to_gc5035(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return __gc5035_power_on(gc5035);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static int gc5035_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct gc5035 *gc5035 = to_gc5035(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) __gc5035_power_off(gc5035);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static int gc5035_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct gc5035 *gc5035 = to_gc5035(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) const struct gc5035_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) mutex_lock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) try_fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) mutex_unlock(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static int sensor_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct gc5035 *sensor = to_gc5035(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) //struct device *dev = &sensor->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) //dev_info(dev, "%s(%d) enter!\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (2 == sensor->lane_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) config->flags = V4L2_MBUS_CSI2_2_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) dev_err(&sensor->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) "unsupported lane_num(%d)\n", sensor->lane_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static int gc5035_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct gc5035 *gc5035 = to_gc5035(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (fie->index >= gc5035->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (fie->code != MEDIA_BUS_FMT_SRGGB10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static const struct dev_pm_ops gc5035_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) SET_RUNTIME_PM_OPS(gc5035_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) gc5035_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static const struct v4l2_subdev_internal_ops gc5035_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .open = gc5035_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static const struct v4l2_subdev_core_ops gc5035_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .s_power = gc5035_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .ioctl = gc5035_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .compat_ioctl32 = gc5035_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static const struct v4l2_subdev_video_ops gc5035_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .s_stream = gc5035_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .g_frame_interval = gc5035_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static const struct v4l2_subdev_pad_ops gc5035_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .enum_mbus_code = gc5035_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .enum_frame_size = gc5035_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .enum_frame_interval = gc5035_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .get_fmt = gc5035_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .set_fmt = gc5035_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .get_mbus_config = sensor_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static const struct v4l2_subdev_ops gc5035_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .core = &gc5035_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .video = &gc5035_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .pad = &gc5035_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static int gc5035_set_test_pattern(struct gc5035 *gc5035, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dev_info(&gc5035->client->dev, "Test Pattern!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ret = gc5035_write_reg(gc5035->client, 0xfe, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ret |= gc5035_write_reg(gc5035->client, 0x8c, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret |= gc5035_write_reg(gc5035->client, 0xfe, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static const char * const gc5035_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static int gc5035_set_exposure_reg(struct gc5035 *gc5035, u32 exposure)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) u32 caltime = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) caltime = exposure / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) caltime = caltime * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) gc5035->Dgain_ratio = 64 * exposure / caltime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ret = gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) GC5035_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) GC5035_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ret |= gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) GC5035_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) (caltime >> 8) & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) ret |= gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) GC5035_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) caltime & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static u32 GC5035_AGC_Param[17][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {64, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {76, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {90, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {106, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {126, 8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {150, 9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {179, 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {211, 11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {250, 12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {301, 13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {358, 14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {427, 15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {499, 16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {589, 17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {704, 18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {830, 19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {998, 20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static int gc5035_set_gain_reg(struct gc5035 *gc5035, u32 a_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct device *dev = &gc5035->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) int ret = 0, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) u32 temp_gain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) //dev_info(dev, "%s(%d) a_gain(0x%08x)!\n", __func__, __LINE__, a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (a_gain < 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) a_gain = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) else if (a_gain > 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) a_gain = 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) for (i = 16; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (a_gain >= GC5035_AGC_Param[i][0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ret = gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) GC5035_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) GC5035_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ret |= gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) GC5035_REG_AGAIN, GC5035_AGC_Param[i][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) temp_gain = a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) temp_gain = temp_gain * gc5035->Dgain_ratio / GC5035_AGC_Param[i][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) dev_info(dev, "AGC_Param[%d][0](%d) temp_gain is(0x%08x)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) i, GC5035_AGC_Param[i][0], temp_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret |= gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) GC5035_REG_DGAIN_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) temp_gain >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ret |= gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) GC5035_REG_DGAIN_FRAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) (temp_gain << 2) & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static int gc5035_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct gc5035 *gc5035 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct gc5035, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct i2c_client *client = gc5035->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) max = gc5035->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) __v4l2_ctrl_modify_range(gc5035->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) gc5035->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) gc5035->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) gc5035->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ret = gc5035_set_exposure_reg(gc5035, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ret = gc5035_set_gain_reg(gc5035, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ret = gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) GC5035_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) GC5035_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ret |= gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) GC5035_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) ((ctrl->val + gc5035->cur_mode->height) >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ret |= gc5035_write_reg(gc5035->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) GC5035_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) (ctrl->val + gc5035->cur_mode->height) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ret = gc5035_set_test_pattern(gc5035, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static const struct v4l2_ctrl_ops gc5035_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .s_ctrl = gc5035_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static int gc5035_initialize_controls(struct gc5035 *gc5035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) const struct gc5035_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) handler = &gc5035->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) mode = gc5035->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) handler->lock = &gc5035->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) 0, GC5035_PIXEL_RATE, 1, GC5035_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) gc5035->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (gc5035->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) gc5035->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) gc5035->vblank = v4l2_ctrl_new_std(handler, &gc5035_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) GC5035_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) gc5035->exposure = v4l2_ctrl_new_std(handler, &gc5035_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) V4L2_CID_EXPOSURE, GC5035_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) exposure_max, GC5035_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) gc5035->anal_gain = v4l2_ctrl_new_std(handler, &gc5035_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) V4L2_CID_ANALOGUE_GAIN, GC5035_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) GC5035_GAIN_MAX, GC5035_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) GC5035_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) gc5035->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) &gc5035_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ARRAY_SIZE(gc5035_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) 0, 0, gc5035_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) dev_err(&gc5035->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) gc5035->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static int gc5035_check_sensor_id(struct gc5035 *gc5035,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) struct device *dev = &gc5035->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) u16 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) u8 reg_H = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) u8 reg_L = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) ret = gc5035_read_reg(client, GC5035_REG_CHIP_ID_H, ®_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ret |= gc5035_read_reg(client, GC5035_REG_CHIP_ID_L, ®_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) dev_info(dev, "detected gc%04x sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static int gc5035_configure_regulators(struct gc5035 *gc5035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) for (i = 0; i < GC5035_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) gc5035->supplies[i].supply = gc5035_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return devm_regulator_bulk_get(&gc5035->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) GC5035_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) gc5035->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static void free_gpio(struct gc5035 *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct device *dev = &sensor->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) unsigned int temp_gpio = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) dev_info(dev, "%s(%d) enter!\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (!IS_ERR(sensor->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) temp_gpio = desc_to_gpio(sensor->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) dev_info(dev, "free gpio(%d)!\n", temp_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) gpio_free(temp_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (!IS_ERR(sensor->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) temp_gpio = desc_to_gpio(sensor->pwdn_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) dev_info(dev, "free gpio(%d)!\n", temp_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) gpio_free(temp_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static int gc5035_parse_of(struct gc5035 *gc5035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct device *dev = &gc5035->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) fwnode = of_fwnode_handle(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (rval <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) dev_warn(dev, " Get mipi lane num failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) gc5035->lane_num = rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (2 == gc5035->lane_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) gc5035->cur_mode = &supported_modes_2lane[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) supported_modes = supported_modes_2lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) gc5035->cfg_num = ARRAY_SIZE(supported_modes_2lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) gc5035->pixel_rate = MIPI_FREQ * 2U * gc5035->lane_num / 10U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) gc5035->lane_num, gc5035->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) dev_err(dev, "unsupported lane_num(%d)\n", gc5035->lane_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static int gc5035_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) struct gc5035 *gc5035;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) gc5035 = devm_kzalloc(dev, sizeof(*gc5035), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (!gc5035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) &gc5035->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) &gc5035->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) &gc5035->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) &gc5035->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) gc5035->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) gc5035->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (IS_ERR(gc5035->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) gc5035->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (IS_ERR(gc5035->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) gc5035->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (IS_ERR(gc5035->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) ret = gc5035_configure_regulators(gc5035);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) ret = gc5035_parse_of(gc5035);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) gc5035->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (!IS_ERR(gc5035->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) gc5035->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) pinctrl_lookup_state(gc5035->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (IS_ERR(gc5035->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) gc5035->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) pinctrl_lookup_state(gc5035->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (IS_ERR(gc5035->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) mutex_init(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) sd = &gc5035->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) v4l2_i2c_subdev_init(sd, client, &gc5035_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ret = gc5035_initialize_controls(gc5035);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) ret = __gc5035_power_on(gc5035);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) ret = gc5035_check_sensor_id(gc5035, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) sd->internal_ops = &gc5035_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) gc5035->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ret = media_entity_pads_init(&sd->entity, 1, &gc5035->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (strcmp(gc5035->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) gc5035->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) GC5035_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) __gc5035_power_off(gc5035);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) free_gpio(gc5035);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) v4l2_ctrl_handler_free(&gc5035->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) mutex_destroy(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static int gc5035_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) struct gc5035 *gc5035 = to_gc5035(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) v4l2_ctrl_handler_free(&gc5035->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) mutex_destroy(&gc5035->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) __gc5035_power_off(gc5035);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static const struct of_device_id gc5035_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) { .compatible = "galaxycore,gc5035" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) MODULE_DEVICE_TABLE(of, gc5035_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static const struct i2c_device_id gc5035_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) { "galaxycore,gc5035", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static struct i2c_driver gc5035_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .name = GC5035_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .pm = &gc5035_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .of_match_table = of_match_ptr(gc5035_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .probe = &gc5035_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .remove = &gc5035_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .id_table = gc5035_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return i2c_add_driver(&gc5035_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) i2c_del_driver(&gc5035_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) MODULE_DESCRIPTION("GalaxyCore gc5035 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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