^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * gc5025 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GC5025_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GC5025_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GC5025_LINK_FREQ_MHZ 432000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GC5025_PIXEL_RATE (GC5025_LINK_FREQ_MHZ * 2 * 2 / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GC5025_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CHIP_ID 0x5025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GC5025_REG_CHIP_ID_H 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GC5025_REG_CHIP_ID_L 0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GC5025_REG_SET_PAGE 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GC5025_SET_PAGE_ONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GC5025_REG_CTRL_MODE 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GC5025_MODE_SW_STANDBY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GC5025_MODE_STREAMING 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GC5025_REG_EXPOSURE_H 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GC5025_REG_EXPOSURE_L 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GC5025_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GC5025_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GC5025_VTS_MAX 0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GC5025_REG_AGAIN 0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GC5025_REG_DGAIN_INT 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GC5025_REG_DGAIN_FRAC 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GC5025_GAIN_MIN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GC5025_GAIN_MAX 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GC5025_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GC5025_GAIN_DEFAULT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GC5025_REG_VTS_H 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GC5025_REG_VTS_L 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define REG_NULL 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GC5025_NAME "gc5025"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const char * const gc5025_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GC5025_NUM_SUPPLIES ARRAY_SIZE(gc5025_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMAGE_NORMAL_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DD_PARAM_QTY_5025 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define INFO_ROM_START_5025 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define INFO_WIDTH_5025 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define WB_ROM_START_5025 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define WB_WIDTH_5025 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GOLDEN_ROM_START_5025 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GOLDEN_WIDTH_5025 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define WINDOW_WIDTH 0x0a30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define WINDOW_HEIGHT 0x079c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct gc5025_otp_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 flag; //bit[7]: info bit[6]:wb bit[3]:dd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 lens_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 vcm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u16 vcm_driver_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 month;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 day;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 rg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 bg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 golden_rg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 golden_bg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 dd_param_x[DD_PARAM_QTY_5025];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 dd_param_y[DD_PARAM_QTY_5025];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u16 dd_param_type[DD_PARAM_QTY_5025];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u16 dd_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct gc5025_id_name {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) char name[RKMODULE_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct gc5025_id_name gc5025_module_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {0x0d, "CameraKing"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {0x00, "Unknown"}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct gc5025_id_name gc5025_lens_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {0xa9, "CK5502"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {0x00, "Unknown"}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct gc5025_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct gc5025 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct regulator_bulk_data supplies[GC5025_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const struct gc5025_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 Dgain_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) bool DR_State;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct gc5025_otp_info *otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct rkmodule_inf module_inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct rkmodule_awb_cfg awb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define to_gc5025(sd) container_of(sd, struct gc5025, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct regval gc5025_2592x1944_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * mipi_datarate per lane 656Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct regval gc5025_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0xf7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0xf8, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0xf9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0xfa, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0xfc, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0xfe, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x01, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0xfc, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x88, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x03, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x04, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x05, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x06, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x08, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x0a, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x0c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x0d, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x0e, 0x9c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x0f, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x10, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x17, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x18, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x19, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x1a, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x1e, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x1f, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x20, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x21, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x26, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x25, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x27, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x28, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x29, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x2b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x30, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x31, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x32, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x33, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x34, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x81, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0xcb, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0xcd, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0xcf, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0xd0, 0xb3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0xd1, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0xd9, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0xdc, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0xdd, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0xe0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0xe1, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0xe3, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0xe4, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0xe5, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0xe6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0xe7, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0xfe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0xfe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x80, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x89, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0xfe, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x88, 0xf7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x8a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x8e, 0xc7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x40, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x41, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x42, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x4e, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x4f, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x67, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0xae, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0xaf, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x60, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x61, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0xb0, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0xb1, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0xb2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0xb6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x91, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x92, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x94, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0xfe, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x02, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x03, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x06, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x16, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x18, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x21, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x22, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x23, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x24, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x25, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x26, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x29, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x2a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x2b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct regval gc5025_doublereset_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x1c, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x2f, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x38, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x39, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0xd3, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x43, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x1d, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct regval gc5025_disable_doublereset_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x1c, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x2f, 0x4d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x38, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x39, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x3c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x3d, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0xd3, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x43, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x1d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const struct gc5025_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .width = 2592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .height = 1944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .exp_def = 0x07C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .hts_def = 0x12C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .vts_def = 0x07D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .reg_list = gc5025_2592x1944_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) GC5025_LINK_FREQ_MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int gc5025_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "gc5025 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int gc5025_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = gc5025_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int gc5025_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) "gc5025 read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int gc5025_get_reso_dist(const struct gc5025_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const struct gc5025_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) gc5025_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dist = gc5025_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int gc5025_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct gc5025 *gc5025 = to_gc5025(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) const struct gc5025_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mutex_lock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mode = gc5025_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) fmt->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mutex_unlock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) gc5025->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) __v4l2_ctrl_modify_range(gc5025->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) __v4l2_ctrl_modify_range(gc5025->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) GC5025_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) mutex_unlock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int gc5025_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct gc5025 *gc5025 = to_gc5025(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) const struct gc5025_mode *mode = gc5025->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) mutex_lock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) mutex_unlock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) fmt->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) mutex_unlock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int gc5025_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) code->code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int gc5025_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (fse->code != MEDIA_BUS_FMT_SRGGB10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int gc5025_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct gc5025 *gc5025 = to_gc5025(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) const struct gc5025_mode *mode = gc5025->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mutex_lock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mutex_unlock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int gc5025_otp_read_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u8 addr_high = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = gc5025_write_reg(client, 0xfe, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret |= gc5025_read_reg(client, 0xd4, &addr_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) switch (page) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) addr_high &= 0xfb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) addr_high |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) addr_high &= 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) addr_high |= (address & 0x300) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ret |= gc5025_write_reg(client, 0xD4, addr_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret |= gc5025_write_reg(client, 0xD5, address & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret |= gc5025_write_reg(client, 0xF3, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret |= gc5025_read_reg(client, 0xD7, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int gc5025_otp_enable(struct gc5025 *gc5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct i2c_client *client = gc5025->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u8 otp_clk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u8 otp_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = gc5025_write_reg(client, 0xfe, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ret |= gc5025_write_reg(client, 0xf7, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ret |= gc5025_write_reg(client, 0xf8, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret |= gc5025_write_reg(client, 0xf9, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ret |= gc5025_write_reg(client, 0xfa, 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret |= gc5025_write_reg(client, 0xfc, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret |= gc5025_write_reg(client, 0xfe, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ret |= gc5025_write_reg(client, 0x01, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ret |= gc5025_write_reg(client, 0xfc, 0x2e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret |= gc5025_write_reg(client, 0xfe, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret |= gc5025_write_reg(client, 0x88, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret |= gc5025_write_reg(client, 0xe7, 0xcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ret |= gc5025_write_reg(client, 0xfc, 0x2e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret |= gc5025_write_reg(client, 0xfa, 0xb0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret |= gc5025_read_reg(client, 0xfa, &otp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ret |= gc5025_read_reg(client, 0xd4, &otp_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) otp_clk |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) otp_en |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret |= gc5025_write_reg(client, 0xfa, otp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret |= gc5025_write_reg(client, 0xd4, otp_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int gc5025_otp_disable(struct gc5025 *gc5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct i2c_client *client = gc5025->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u8 otp_clk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u8 otp_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = gc5025_read_reg(client, 0xfa, &otp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret |= gc5025_read_reg(client, 0xd4, &otp_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) otp_clk &= 0xef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) otp_en &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret |= gc5025_write_reg(client, 0xfa, otp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret |= gc5025_write_reg(client, 0xd4, otp_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static int gc5025_otp_read(struct gc5025 *gc5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int otp_flag, i, j, index, temp, tmpH, tmpL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct gc5025_otp_info *otp_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct device *dev = &gc5025->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct i2c_client *client = gc5025->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int checksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int page = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int total_number = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u8 m_DD_Otp_Value[182];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u16 dd_rom_start, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u8 info_start_add, wb_start_add, golden_start_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u8 check_dd_flag, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u8 dd0 = 0, dd1 = 0, dd2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u16 x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) otp_p = devm_kzalloc(dev, sizeof(*otp_p), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (!otp_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* OTP info and awb*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) otp_flag = gc5025_otp_read_reg(client, 1, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) for (index = 0; index < 2; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) switch ((otp_flag >> (4 + 2 * index)) & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dev_err(dev, "%s GC5025_OTP_INFO group %d is Empty!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) __func__, index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dev_dbg(dev, "%s GC5025_OTP_INFO group %d is Valid!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) __func__, index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) checksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) info_start_add =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) INFO_ROM_START_5025 + 8 * index * INFO_WIDTH_5025;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) otp_p->module_id = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 1, info_start_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) checksum += otp_p->module_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) otp_p->lens_id = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 1, info_start_add + 8 * 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) checksum += otp_p->lens_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) otp_p->vcm_driver_id = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 1, info_start_add + 8 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) checksum += otp_p->vcm_driver_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) otp_p->vcm_id = gc5025_otp_read_reg(client, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) info_start_add + 8 * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) checksum += otp_p->vcm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) otp_p->year = gc5025_otp_read_reg(client, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) info_start_add + 8 * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) checksum += otp_p->year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) otp_p->month = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 1, info_start_add + 8 * 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) checksum += otp_p->month;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) otp_p->day = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 1, info_start_add + 8 * 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) checksum += otp_p->day;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) checksum = checksum % 255 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) temp = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 1, 0x40 + 8 * index * INFO_WIDTH_5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (checksum == temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) otp_p->flag = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_dbg(dev, "fac info: module(0x%x) lens(0x%x) time(%d_%d_%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) otp_p->module_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) otp_p->lens_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) otp_p->year,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) otp_p->month,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) otp_p->day);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_err(dev, "otp module info check sum error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dev_err(dev, "%s GC5025_OTP_INFO group %d is Invalid !!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) __func__, index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) switch ((otp_flag >> (2 * index)) & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_err(dev, "%s GC5025_OTP_WB group %d is Empty !\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) __func__, index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dev_dbg(dev, "%s GC5025_OTP_WB group %d is Valid !!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) __func__, index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) checksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) wb_start_add =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) WB_ROM_START_5025 + 8 * index * WB_WIDTH_5025;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) tmpH = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 1, wb_start_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) checksum += tmpH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) tmpL = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 1, wb_start_add + 8 * 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) checksum += tmpL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) otp_p->rg_ratio = (tmpH << 8) | tmpL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) tmpH = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 1, wb_start_add + 8 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) checksum += tmpH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) tmpL = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 1, wb_start_add + 8 * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) checksum += tmpL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) otp_p->bg_ratio = (tmpH << 8) | tmpL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) checksum = checksum % 255 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) temp = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 1, 0xa8 + 8 * index * WB_WIDTH_5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (checksum == temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) otp_p->flag = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dev_dbg(dev, "otp:(rg_ratio 0x%x, bg_ratio 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) otp_p->rg_ratio, otp_p->bg_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dev_err(dev, "%s GC5025_OTP_WB group %d is Invalid !!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) __func__, index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* OTP awb golden*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) otp_flag = gc5025_otp_read_reg(client, 1, 0xd8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) for (index = 0; index < 2; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) switch ((otp_flag >> (2 * index)) & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_err(dev, "%s GC5025_OTP_GOLDEN group %d is Empty !\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) __func__, index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) dev_dbg(dev, "%s GC5025_OTP_GOLDEN group %d is Valid !!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) __func__, index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) checksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) golden_start_add =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) GOLDEN_ROM_START_5025 + 8 * index * GOLDEN_WIDTH_5025;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) tmpH = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 1, golden_start_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) checksum += tmpH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) tmpL = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 1, golden_start_add + 8 * 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) checksum += tmpL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) otp_p->golden_rg = (tmpH << 8) | tmpL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) tmpH = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 1, golden_start_add + 8 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) checksum += tmpH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) tmpL = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 1, golden_start_add + 8 * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) checksum += tmpL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) otp_p->golden_bg = (tmpH << 8) | tmpL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) checksum = checksum % 255 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) temp = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 0x100 + 8 * index * GOLDEN_WIDTH_5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (checksum == temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev_dbg(dev, "otp:(golden_rg 0x%x, golden_bg 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) otp_p->golden_rg, otp_p->golden_bg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dev_err(dev, "%s GC5025_OTP_GOLDEN group %d is Invalid !!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) __func__, index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* OTP DD calibration data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) otp_flag = gc5025_otp_read_reg(client, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) switch (otp_flag & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_err(dev, "%s GC5025 OTP:flag_dd is EMPTY!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dev_dbg(dev, "%s GC5025 OTP:flag_dd is Valid!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) checksum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) total_number = gc5025_otp_read_reg(client, 0, 0x08) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) gc5025_otp_read_reg(client, 0, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) for (i = 0; i < 126; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) m_DD_Otp_Value[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) 0, 0x08 + 8 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) checksum += m_DD_Otp_Value[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) for (i = 0; i < 56; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) m_DD_Otp_Value[126 + i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) 1, 0x148 + 8 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) checksum += m_DD_Otp_Value[126 + i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) checksum = checksum % 255 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) temp = gc5025_otp_read_reg(client, 1, 0x308);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (checksum == temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) for (i = 0; i < total_number; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (i < 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) page = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dd_rom_start = 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) page = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dd_rom_start = 0x148;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) offset = 124;//31*4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) check_dd_flag = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dd_rom_start + 8 * (4 * i - offset + 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (check_dd_flag & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) //Read OTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) type = check_dd_flag & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dd0 = gc5025_otp_read_reg(client, page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dd_rom_start + 8 * (4 * i - offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dd1 = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dd_rom_start + 8 * (4 * i - offset + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dd2 = gc5025_otp_read_reg(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dd_rom_start + 8 * (4 * i - offset + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) x = ((dd1 & 0x0f) << 8) + dd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) y = (dd2 << 4) + ((dd1 & 0xf0) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (type == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) for (j = 0; j < 4; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) otp_p->dd_param_x[cnt] = x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) otp_p->dd_param_y[cnt] = y + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) otp_p->dd_param_type[cnt++] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) } else if (type == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) for (j = 0; j < 2; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) otp_p->dd_param_x[cnt] = x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) otp_p->dd_param_y[cnt] = y + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) otp_p->dd_param_type[cnt++] = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) otp_p->dd_param_x[cnt] = x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) otp_p->dd_param_y[cnt] = y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) otp_p->dd_param_type[cnt++] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) dev_err(dev, "%s GC5025_OTP_DD:check_id[%d] = %x,checkid error!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) __func__, i, check_dd_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) otp_p->dd_cnt = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) otp_p->flag |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev_err(dev, "%s GC5025 OTP:flag_dd is Invalid!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (otp_p->flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) gc5025->otp = otp_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) gc5025->otp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) devm_kfree(dev, otp_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static void gc5025_get_otp(struct gc5025_otp_info *otp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* fac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (otp->flag & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) inf->fac.flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) inf->fac.year = otp->year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) inf->fac.month = otp->month;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) inf->fac.day = otp->day;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) for (i = 0; i < ARRAY_SIZE(gc5025_module_info) - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (gc5025_module_info[i].id == otp->module_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) strlcpy(inf->fac.module, gc5025_module_info[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) sizeof(inf->fac.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) for (i = 0; i < ARRAY_SIZE(gc5025_lens_info) - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (gc5025_lens_info[i].id == otp->lens_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) strlcpy(inf->fac.lens, gc5025_lens_info[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) sizeof(inf->fac.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* awb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (otp->flag & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) inf->awb.flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) inf->awb.r_value = otp->rg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) inf->awb.b_value = otp->bg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) inf->awb.gr_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) inf->awb.gb_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) inf->awb.golden_r_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) inf->awb.golden_b_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) inf->awb.golden_gr_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) inf->awb.golden_gb_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static void gc5025_get_module_inf(struct gc5025 *gc5025,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct gc5025_otp_info *otp = gc5025->otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) strlcpy(inf->base.sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) GC5025_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) strlcpy(inf->base.module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) gc5025->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) strlcpy(inf->base.lens,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) gc5025->len_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (otp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) gc5025_get_otp(otp, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static void gc5025_set_module_inf(struct gc5025 *gc5025,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct rkmodule_awb_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) mutex_lock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) memcpy(&gc5025->awb_cfg, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) mutex_unlock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static long gc5025_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct gc5025 *gc5025 = to_gc5025(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) gc5025_get_module_inf(gc5025, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) gc5025_set_module_inf(gc5025, (struct rkmodule_awb_cfg *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ret = gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) GC5025_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) GC5025_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ret |= gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) GC5025_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) GC5025_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ret = gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) GC5025_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) GC5025_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ret |= gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) GC5025_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) GC5025_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static long gc5025_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ret = gc5025_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret = gc5025_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ret = gc5025_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int gc5025_apply_otp(struct gc5025 *gc5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int R_gain, G_gain, B_gain, base_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct i2c_client *client = gc5025->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct gc5025_otp_info *otp_p = gc5025->otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct rkmodule_awb_cfg *awb_cfg = &gc5025->awb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) u32 golden_bg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) u32 golden_rg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) u32 golden_g_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) u16 i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u16 temp_x = 0, temp_y = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) u8 temp_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) u8 temp_val0, temp_val1, temp_val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) u16 column, ii, iii, jj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (!gc5025->awb_cfg.enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) golden_g_value = (awb_cfg->golden_gb_value +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) awb_cfg->golden_gr_value) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) golden_bg_ratio =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) awb_cfg->golden_b_value * 0x400 / golden_g_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) golden_rg_ratio =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) awb_cfg->golden_r_value * 0x400 / golden_g_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /* apply OTP WB Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if ((otp_p->flag & 0x40) && golden_bg_ratio && golden_rg_ratio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* calculate G gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) R_gain = golden_rg_ratio * 1000 / otp_p->rg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) B_gain = golden_bg_ratio * 1000 / otp_p->bg_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) G_gain = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) base_gain = (R_gain < B_gain) ? R_gain : B_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) base_gain = (base_gain < G_gain) ? base_gain : G_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) R_gain = 0x400 * R_gain / (base_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) B_gain = 0x400 * B_gain / (base_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) G_gain = 0x400 * G_gain / (base_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* update sensor WB gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) gc5025_write_reg(client, 0xfe, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) gc5025_write_reg(client, 0xc6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) (G_gain & 0x7f8) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) gc5025_write_reg(client, 0xc7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) (R_gain & 0x7f8) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) gc5025_write_reg(client, 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) (B_gain & 0x7f8) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) gc5025_write_reg(client, 0xc9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) (G_gain & 0x7f8) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) gc5025_write_reg(client, 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ((G_gain & 0X07) << 4) | (R_gain & 0x07));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) gc5025_write_reg(client, 0xc5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ((B_gain & 0X07) << 4) | (G_gain & 0x07));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) dev_dbg(&client->dev, "apply awb gain: 0x%x, 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) R_gain, G_gain, B_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /* apply OTP DD Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (otp_p->flag & 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #if defined IMAGE_NORMAL_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #elif defined IMAGE_H_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) for (i = 0; i < otp_p->dd_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (otp_p->dd_param_type[i] == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) otp_p->dd_param_x[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) WINDOW_WIDTH - otp_p->dd_param_x[i] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) } else if (otp_p->dd_param_type[i] == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) otp_p->dd_param_x[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) WINDOW_WIDTH - otp_p->dd_param_x[i] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) otp_p->dd_param_x[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) WINDOW_WIDTH - otp_p->dd_param_x[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #elif defined IMAGE_V_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) for (i = 0; i < otp_p->dd_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) otp_p->dd_param_y[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) WINDOW_HEIGHT - otp_p->dd_param_y[i] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #elif defined IMAGE_HV_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) for (i = 0; i < otp_p->dd_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (otp_p->dd_param_type[i] == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) otp_p->dd_param_x[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) WINDOW_WIDTH - otp_p->dd_param_x[i] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) otp_p->dd_param_y[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) WINDOW_HEIGHT - otp_p->dd_param_y[i] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) } else if (otp_p->dd_param_type[i] == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) otp_p->dd_param_x[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) WINDOW_WIDTH - otp_p->dd_param_x[i] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) otp_p->dd_param_y[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) WINDOW_HEIGHT - otp_p->dd_param_y[i] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) otp_p->dd_param_x[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) WINDOW_WIDTH - otp_p->dd_param_x[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) otp_p->dd_param_y[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) WINDOW_HEIGHT - otp_p->dd_param_y[i] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) //y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) for (i = 0; i < otp_p->dd_cnt - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) for (j = 0; j < otp_p->dd_cnt - 1 - i; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (otp_p->dd_param_y[j] >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) otp_p->dd_param_y[j + 1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) temp_x = otp_p->dd_param_x[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) otp_p->dd_param_x[j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) otp_p->dd_param_x[j + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) otp_p->dd_param_x[j + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) temp_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) temp_y =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) otp_p->dd_param_y[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) otp_p->dd_param_y[j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) otp_p->dd_param_y[j + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) otp_p->dd_param_y[j + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) temp_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) temp_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) otp_p->dd_param_type[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) otp_p->dd_param_type[j] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) otp_p->dd_param_type[j + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) otp_p->dd_param_type[j + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) temp_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) //x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) column = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) for (i = 0 ; i < otp_p->dd_cnt - 1; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (otp_p->dd_param_y[i] == otp_p->dd_param_y[i + 1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) column++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (otp_p->dd_cnt - 2 != i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (otp_p->dd_cnt - 2 == i &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) otp_p->dd_param_y[i] == otp_p->dd_param_y[i + 1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) i = otp_p->dd_cnt - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) iii = i - column;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) for (ii = i - column; ii < i ; ++ii) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) for (jj = i - column; jj <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) i - (ii - iii); ++jj) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (otp_p->dd_param_x[jj] >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) otp_p->dd_param_x[jj + 1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) temp_x = otp_p->dd_param_x[jj];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) otp_p->dd_param_x[jj] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) otp_p->dd_param_x[jj + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) otp_p->dd_param_x[jj + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) temp_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) temp_y =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) otp_p->dd_param_y[jj];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) otp_p->dd_param_y[jj] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) otp_p->dd_param_y[jj + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) otp_p->dd_param_y[jj + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) temp_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) temp_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) otp_p->dd_param_type[jj];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) otp_p->dd_param_type[jj] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) otp_p->dd_param_type[jj + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) otp_p->dd_param_type[jj + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) temp_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) column = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) //write SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) gc5025_write_reg(client, 0xfe, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) gc5025_write_reg(client, 0x80, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) gc5025_write_reg(client, 0xfe, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) gc5025_write_reg(client, 0xa8, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) gc5025_write_reg(client, 0x9d, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) gc5025_write_reg(client, 0xbe, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) gc5025_write_reg(client, 0xa9, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) for (i = 0; i < otp_p->dd_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) temp_val0 = otp_p->dd_param_x[i] & 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) temp_val1 = ((otp_p->dd_param_y[i] << 4) & 0x00f0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ((otp_p->dd_param_x[i] >> 8) & 0x000f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) temp_val2 = (otp_p->dd_param_y[i] >> 4) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) gc5025_write_reg(client, 0xaa, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) gc5025_write_reg(client, 0xac, temp_val0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) gc5025_write_reg(client, 0xac, temp_val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) gc5025_write_reg(client, 0xac, temp_val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) gc5025_write_reg(client, 0xac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) otp_p->dd_param_type[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) gc5025_write_reg(client, 0xbe, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) gc5025_write_reg(client, 0xfe, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static int __gc5025_start_stream(struct gc5025 *gc5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ret = gc5025_write_array(gc5025->client, gc5025->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (gc5025->DR_State) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) ret = gc5025_write_array(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) gc5025_doublereset_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ret = gc5025_write_array(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) gc5025_disable_doublereset_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) mutex_unlock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ret = v4l2_ctrl_handler_setup(&gc5025->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) mutex_lock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (gc5025->otp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ret = gc5025_otp_enable(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ret |= gc5025_apply_otp(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ret |= gc5025_otp_disable(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ret = gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) GC5025_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) GC5025_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) ret |= gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) GC5025_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) GC5025_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static int __gc5025_stop_stream(struct gc5025 *gc5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ret = gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) GC5025_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) GC5025_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) ret |= gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) GC5025_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) GC5025_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static int gc5025_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct gc5025 *gc5025 = to_gc5025(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct i2c_client *client = gc5025->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) mutex_lock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (on == gc5025->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) ret = __gc5025_start_stream(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) __gc5025_stop_stream(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) gc5025->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) mutex_unlock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static int gc5025_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct gc5025 *gc5025 = to_gc5025(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) struct i2c_client *client = gc5025->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) mutex_lock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (gc5025->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) ret = gc5025_write_array(gc5025->client, gc5025_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) gc5025->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) gc5025->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) mutex_unlock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static inline u32 gc5025_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) return DIV_ROUND_UP(cycles, GC5025_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static int __gc5025_power_on(struct gc5025 *gc5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) struct device *dev = &gc5025->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (!IS_ERR(gc5025->power_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) gpiod_set_value_cansleep(gc5025->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) usleep_range(5000, 5100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (!IS_ERR_OR_NULL(gc5025->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ret = pinctrl_select_state(gc5025->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) gc5025->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) ret = clk_set_rate(gc5025->xvclk, GC5025_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (clk_get_rate(gc5025->xvclk) != GC5025_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ret = clk_prepare_enable(gc5025->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (!IS_ERR(gc5025->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) gpiod_set_value_cansleep(gc5025->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) ret = regulator_bulk_enable(GC5025_NUM_SUPPLIES, gc5025->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (!IS_ERR(gc5025->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) gpiod_set_value_cansleep(gc5025->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (!IS_ERR(gc5025->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) gpiod_set_value_cansleep(gc5025->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) delay_us = gc5025_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) clk_disable_unprepare(gc5025->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static void __gc5025_power_off(struct gc5025 *gc5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (!IS_ERR(gc5025->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) gpiod_set_value_cansleep(gc5025->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) clk_disable_unprepare(gc5025->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (!IS_ERR(gc5025->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) gpiod_set_value_cansleep(gc5025->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (!IS_ERR_OR_NULL(gc5025->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) ret = pinctrl_select_state(gc5025->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) gc5025->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) dev_dbg(&gc5025->client->dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) regulator_bulk_disable(GC5025_NUM_SUPPLIES, gc5025->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static int gc5025_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) struct gc5025 *gc5025 = to_gc5025(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return __gc5025_power_on(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static int gc5025_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) struct gc5025 *gc5025 = to_gc5025(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) __gc5025_power_off(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static int gc5025_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) struct gc5025 *gc5025 = to_gc5025(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) const struct gc5025_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) mutex_lock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) try_fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) mutex_unlock(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static int gc5025_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (fie->code != MEDIA_BUS_FMT_SRGGB10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static int gc5025_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) val = 1 << (GC5025_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) static int gc5025_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) sel->r.width = 2592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) sel->r.top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) sel->r.height = 1944;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static const struct dev_pm_ops gc5025_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) SET_RUNTIME_PM_OPS(gc5025_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) gc5025_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static const struct v4l2_subdev_internal_ops gc5025_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .open = gc5025_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static const struct v4l2_subdev_core_ops gc5025_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .s_power = gc5025_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .ioctl = gc5025_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .compat_ioctl32 = gc5025_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) static const struct v4l2_subdev_video_ops gc5025_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .s_stream = gc5025_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .g_frame_interval = gc5025_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static const struct v4l2_subdev_pad_ops gc5025_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .enum_mbus_code = gc5025_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .enum_frame_size = gc5025_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .enum_frame_interval = gc5025_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .get_fmt = gc5025_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .set_fmt = gc5025_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .get_selection = gc5025_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .get_mbus_config = gc5025_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static const struct v4l2_subdev_ops gc5025_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .core = &gc5025_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .video = &gc5025_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .pad = &gc5025_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) static int gc5025_set_exposure_reg(struct gc5025 *gc5025, u32 exposure)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) u32 caltime = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) caltime = exposure / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) caltime = caltime * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) gc5025->Dgain_ratio = 256 * exposure / caltime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) ret = gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) GC5025_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) GC5025_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (!gc5025->DR_State) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) if (caltime <= 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) ret |= gc5025_write_reg(gc5025->client, 0xd9, 0xdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) ret |= gc5025_write_reg(gc5025->client, 0xd9, 0xaa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) ret |= gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) GC5025_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) (caltime >> 8) & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) ret |= gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) GC5025_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) caltime & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define GC5025_ANALOG_GAIN_1 64 /*1.00x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define GC5025_ANALOG_GAIN_2 92 // 1.445x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) static int gc5025_set_gain_reg(struct gc5025 *gc5025, u32 a_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) u32 temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (a_gain < 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) a_gain = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) ret = gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) GC5025_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) GC5025_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (a_gain >= GC5025_ANALOG_GAIN_1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) a_gain < GC5025_ANALOG_GAIN_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) ret |= gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) GC5025_REG_AGAIN, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) temp = a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) ret |= gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) GC5025_REG_AGAIN, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) temp = 64 * a_gain / GC5025_ANALOG_GAIN_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) temp = temp * gc5025->Dgain_ratio / 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) ret |= gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) GC5025_REG_DGAIN_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) temp >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) ret |= gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) GC5025_REG_DGAIN_FRAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) (temp << 2) & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static int gc5025_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) struct gc5025 *gc5025 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) struct gc5025, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) struct i2c_client *client = gc5025->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) max = gc5025->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) __v4l2_ctrl_modify_range(gc5025->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) gc5025->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) gc5025->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) gc5025->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) ret = gc5025_set_exposure_reg(gc5025, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) ret = gc5025_set_gain_reg(gc5025, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) ret = gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) GC5025_REG_SET_PAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) GC5025_SET_PAGE_ONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) ret |= gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) GC5025_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ((ctrl->val - 24) >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) ret |= gc5025_write_reg(gc5025->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) GC5025_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) (ctrl->val - 24) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static const struct v4l2_ctrl_ops gc5025_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .s_ctrl = gc5025_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static int gc5025_initialize_controls(struct gc5025 *gc5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) const struct gc5025_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) handler = &gc5025->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) mode = gc5025->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) handler->lock = &gc5025->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) 0, GC5025_PIXEL_RATE, 1, GC5025_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) gc5025->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (gc5025->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) gc5025->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) gc5025->vblank = v4l2_ctrl_new_std(handler, &gc5025_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) GC5025_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) gc5025->exposure = v4l2_ctrl_new_std(handler, &gc5025_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) V4L2_CID_EXPOSURE, GC5025_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) exposure_max, GC5025_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) gc5025->anal_gain = v4l2_ctrl_new_std(handler, &gc5025_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) V4L2_CID_ANALOGUE_GAIN, GC5025_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) GC5025_GAIN_MAX, GC5025_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) GC5025_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) dev_err(&gc5025->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) gc5025->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) static int gc5025_check_sensor_id(struct gc5025 *gc5025,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) struct device *dev = &gc5025->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) u16 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) u8 reg_H = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) u8 reg_L = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) u8 flag_doublereset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) u8 flag_GC5025A = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) ret = gc5025_read_reg(client, GC5025_REG_CHIP_ID_H, ®_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) ret |= gc5025_read_reg(client, GC5025_REG_CHIP_ID_L, ®_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) ret |= gc5025_read_reg(client, 0x26, &flag_doublereset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) ret |= gc5025_read_reg(client, 0x27, &flag_GC5025A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) if ((flag_GC5025A & 0x01) == 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) dev_warn(dev, "GC5025A sensor!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) gc5025->DR_State = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) if ((flag_doublereset & 0x03) == 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) gc5025->DR_State = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) dev_warn(dev, "GC5025 double reset off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) gc5025->DR_State = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) dev_warn(dev, "GC5025 double reset on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) static int gc5025_configure_regulators(struct gc5025 *gc5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) for (i = 0; i < GC5025_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) gc5025->supplies[i].supply = gc5025_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) return devm_regulator_bulk_get(&gc5025->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) GC5025_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) gc5025->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) static int gc5025_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) struct gc5025 *gc5025;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) gc5025 = devm_kzalloc(dev, sizeof(*gc5025), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) if (!gc5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) &gc5025->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) &gc5025->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) &gc5025->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) &gc5025->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) gc5025->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) gc5025->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) gc5025->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (IS_ERR(gc5025->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) gc5025->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) if (IS_ERR(gc5025->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) dev_warn(dev, "Failed to get power-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) gc5025->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (IS_ERR(gc5025->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) gc5025->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if (IS_ERR(gc5025->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) ret = gc5025_configure_regulators(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) gc5025->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (!IS_ERR(gc5025->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) gc5025->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) pinctrl_lookup_state(gc5025->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (IS_ERR(gc5025->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) gc5025->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) pinctrl_lookup_state(gc5025->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (IS_ERR(gc5025->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) mutex_init(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) sd = &gc5025->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) v4l2_i2c_subdev_init(sd, client, &gc5025_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) ret = gc5025_initialize_controls(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) ret = __gc5025_power_on(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) ret = gc5025_check_sensor_id(gc5025, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) gc5025_otp_enable(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) gc5025_otp_read(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) gc5025_otp_disable(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) sd->internal_ops = &gc5025_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) gc5025->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ret = media_entity_pads_init(&sd->entity, 1, &gc5025->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) if (strcmp(gc5025->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) gc5025->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) GC5025_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) __gc5025_power_off(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) v4l2_ctrl_handler_free(&gc5025->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) mutex_destroy(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) static int gc5025_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) struct gc5025 *gc5025 = to_gc5025(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) v4l2_ctrl_handler_free(&gc5025->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) mutex_destroy(&gc5025->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) __gc5025_power_off(gc5025);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) static const struct of_device_id gc5025_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) { .compatible = "galaxycore,gc5025" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) MODULE_DEVICE_TABLE(of, gc5025_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) static const struct i2c_device_id gc5025_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) { "galaxycore,gc5025", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) static struct i2c_driver gc5025_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .name = GC5025_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .pm = &gc5025_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .of_match_table = of_match_ptr(gc5025_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .probe = &gc5025_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .remove = &gc5025_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .id_table = gc5025_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) return i2c_add_driver(&gc5025_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) i2c_del_driver(&gc5025_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) MODULE_DESCRIPTION("GalaxyCore gc5025 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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