^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * gc5024 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 init driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * TODO: add OTP function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X04 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) //#define IMAGE_NORMAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMAGE_H_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) //#define IMAGE_V_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) //#define IMAGE_HV_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #ifdef IMAGE_NORMAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MIRROR 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PH_SWITCH 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STARTX 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STARTY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #ifdef IMAGE_H_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MIRROR 0xd5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PH_SWITCH 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STARTX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STARTY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #ifdef IMAGE_V_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MIRROR 0xd6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PH_SWITCH 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define STARTX 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STARTY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifdef IMAGE_HV_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MIRROR 0xd7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PH_SWITCH 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define STARTX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STARTY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GC5024_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GC5024_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MIPI_FREQ 420000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* pixel rate = link frequency * 1 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GC5024_PIXEL_RATE (MIPI_FREQ * 2LL * 2LL / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GC5024_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CHIP_ID 0x5024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GC5024_REG_CHIP_ID_H 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GC5024_REG_CHIP_ID_L 0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GC5024_PAGE_SELECT 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GC5024_MODE_SELECT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GC5024_MODE_SW_STANDBY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GC5024_MODE_STREAMING 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GC5024_REG_EXPOSURE_H 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GC5024_REG_EXPOSURE_L 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GC5024_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GC5024_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GC5024_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GC5024_ANALOG_GAIN_1 64 /*1.00x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GC5024_ANALOG_GAIN_2 88 /*1.375x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GC5024_ANALOG_GAIN_3 122 /*1.90x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GC5024_ANALOG_GAIN_4 168 /*2.625x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GC5024_ANALOG_GAIN_5 239 /*3.738x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GC5024_ANALOG_GAIN_6 330 /*5.163x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GC5024_ANALOG_GAIN_7 470 /*7.350x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GC5024_ANALOG_GAIN_REG 0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GC5024_PREGAIN_H_REG 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GC5024_PREGAIN_L_REG 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GC5024_GAIN_MIN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GC5024_GAIN_MAX 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GC5024_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GC5024_GAIN_DEFAULT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GC5024_REG_VTS_H 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GC5024_REG_VTS_L 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GC5024_NAME "gc5024"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GC5024_MEDIA_BUS_FMT MEDIA_BUS_FMT_SBGGR10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const char * const gc5024_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GC5024_NUM_SUPPLIES ARRAY_SIZE(gc5024_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct gc5024_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct gc5024 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct regulator_bulk_data supplies[GC5024_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const struct gc5024_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned int lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define to_gc5024(sd) container_of(sd, struct gc5024, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct regval gc5024_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*SYS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0xf7, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0xf8, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0xf9, 0xae},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0xfa, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0xfc, 0xae},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x88, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0xe7, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*Analog*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x03, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x04, 0xca},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x05, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x06, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x07, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x08, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x0a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x0c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x0d, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x0e, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x0f, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x10, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x11, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x12, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x13, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x17, MIRROR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x18, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x19, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x1a, PH_SWITCH},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x1b, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x1c, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x21, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x24, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x29, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x2d, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x2f, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x32, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0xcd, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0xd0, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0xd1, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0xd2, 0xcb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0xd3, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0xd8, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0xdc, 0xba},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0xe2, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0xe4, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0xe6, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*ISP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x80, 0x50},//50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x8d, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x90, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x92, STARTY},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x94, STARTX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x95, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x96, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x97, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x98, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*Gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x99, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x9a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x9b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x9c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x9d, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x9e, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x9f, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0xb0, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0xb1, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0xb2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0xb6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*Blk*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x40, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x4e, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x4f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x60, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x61, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0xfe, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0xa4, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0xa5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*Dark Sun*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x40, 0x00},//96 20160527
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x42, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x45, 0xca},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x47, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x48, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*DD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x80, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x81, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x82, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x84, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x85, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x86, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x87, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x88, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x89, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*Degrid*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x8a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*MIPI*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0xfe, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x01, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x02, 0x34}, //0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x03, 0x13}, //0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x04, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x05, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x06, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x11, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x12, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x13, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x15, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x16, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x18, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x21, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x22, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x23, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x24, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x25, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x26, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x29, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x2a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x2b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x42, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x43, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0xfe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * mipi_datarate per lane 1008Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct regval gc5024_2592x1944_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct gc5024_mode supported_modes_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .width = 2592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .height = 1944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .denominator = 200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .exp_def = 0x07C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .hts_def = 0x12C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .vts_def = 0x07D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .reg_list = gc5024_2592x1944_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct gc5024_mode *supported_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MIPI_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* sensor register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int gc5024_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "gc5024 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* sensor register read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int gc5024_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "gc5024 read reg:0x%x failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int gc5024_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = gc5024_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int gc5024_get_reso_dist(const struct gc5024_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const struct gc5024_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) gc5024_find_best_fit(struct gc5024 *gc5024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) for (i = 0; i < gc5024->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dist = gc5024_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int gc5024_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct gc5024 *gc5024 = to_gc5024(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) const struct gc5024_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mutex_lock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mode = gc5024_find_best_fit(gc5024, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mutex_unlock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) gc5024->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) __v4l2_ctrl_modify_range(gc5024->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) __v4l2_ctrl_modify_range(gc5024->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) GC5024_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mutex_unlock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int gc5024_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct gc5024 *gc5024 = to_gc5024(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) const struct gc5024_mode *mode = gc5024->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mutex_lock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) mutex_unlock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mutex_unlock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int gc5024_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int gc5024_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct gc5024 *gc5024 = to_gc5024(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (fse->index >= gc5024->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int gc5024_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct gc5024 *gc5024 = to_gc5024(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) const struct gc5024_mode *mode = gc5024->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mutex_lock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) mutex_unlock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static void gc5024_get_module_inf(struct gc5024 *gc5024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) strlcpy(inf->base.sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) GC5024_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) strlcpy(inf->base.module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) gc5024->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) strlcpy(inf->base.lens,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) gc5024->len_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static long gc5024_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct gc5024 *gc5024 = to_gc5024(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) gc5024_get_module_inf(gc5024, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ret = gc5024_write_reg(gc5024->client, GC5024_PAGE_SELECT, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret |= gc5024_write_reg(gc5024->client, GC5024_MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) GC5024_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ret = gc5024_write_reg(gc5024->client, GC5024_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ret = gc5024_write_reg(gc5024->client, GC5024_PAGE_SELECT, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret |= gc5024_write_reg(gc5024->client, GC5024_MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) GC5024_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret |= gc5024_write_reg(gc5024->client, GC5024_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static long gc5024_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = gc5024_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = gc5024_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ret = gc5024_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int __gc5024_start_stream(struct gc5024 *gc5024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ret = gc5024_write_array(gc5024->client, gc5024->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mutex_unlock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = v4l2_ctrl_handler_setup(&gc5024->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) mutex_lock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ret = gc5024_write_reg(gc5024->client, GC5024_PAGE_SELECT, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ret |= gc5024_write_reg(gc5024->client, GC5024_MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) GC5024_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = gc5024_write_reg(gc5024->client, GC5024_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int __gc5024_stop_stream(struct gc5024 *gc5024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = gc5024_write_reg(gc5024->client, GC5024_PAGE_SELECT, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ret |= gc5024_write_reg(gc5024->client, GC5024_MODE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) GC5024_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret |= gc5024_write_reg(gc5024->client, GC5024_PAGE_SELECT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static int gc5024_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct gc5024 *gc5024 = to_gc5024(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct i2c_client *client = gc5024->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) mutex_lock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (on == gc5024->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret = __gc5024_start_stream(gc5024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) __gc5024_stop_stream(gc5024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) gc5024->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) mutex_unlock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static int gc5024_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct gc5024 *gc5024 = to_gc5024(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct i2c_client *client = gc5024->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) mutex_lock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (gc5024->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ret = gc5024_write_array(gc5024->client, gc5024_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) gc5024->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) gc5024->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) mutex_unlock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static inline u32 gc5024_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return DIV_ROUND_UP(cycles, GC5024_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int __gc5024_power_on(struct gc5024 *gc5024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct device *dev = &gc5024->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (!IS_ERR_OR_NULL(gc5024->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ret = pinctrl_select_state(gc5024->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) gc5024->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret = clk_set_rate(gc5024->xvclk, GC5024_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (clk_get_rate(gc5024->xvclk) != GC5024_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ret = clk_prepare_enable(gc5024->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!IS_ERR(gc5024->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) gpiod_set_value_cansleep(gc5024->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (!IS_ERR(gc5024->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) gpiod_set_value_cansleep(gc5024->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = regulator_bulk_enable(GC5024_NUM_SUPPLIES, gc5024->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (!IS_ERR(gc5024->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) gpiod_set_value_cansleep(gc5024->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) delay_us = gc5024_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) clk_disable_unprepare(gc5024->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static void __gc5024_power_off(struct gc5024 *gc5024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct device *dev = &gc5024->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (!IS_ERR(gc5024->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) gpiod_set_value_cansleep(gc5024->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) clk_disable_unprepare(gc5024->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!IS_ERR(gc5024->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) gpiod_set_value_cansleep(gc5024->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (!IS_ERR_OR_NULL(gc5024->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = pinctrl_select_state(gc5024->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) gc5024->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) regulator_bulk_disable(GC5024_NUM_SUPPLIES, gc5024->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static int gc5024_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct gc5024 *gc5024 = to_gc5024(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return __gc5024_power_on(gc5024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int gc5024_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct gc5024 *gc5024 = to_gc5024(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) __gc5024_power_off(gc5024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static int gc5024_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct gc5024 *gc5024 = to_gc5024(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) const struct gc5024_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) mutex_lock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) mutex_unlock(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static int sensor_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct gc5024 *sensor = to_gc5024(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct device *dev = &sensor->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dev_info(dev, "%s(%d) enter!\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (2 == sensor->lane_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) config->type = V4L2_MBUS_CSI2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) config->flags = V4L2_MBUS_CSI2_2_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dev_err(&sensor->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) "unsupported lane_num(%d)\n", sensor->lane_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static int gc5024_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct gc5024 *gc5024 = to_gc5024(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (fie->index >= gc5024->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static const struct dev_pm_ops gc5024_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) SET_RUNTIME_PM_OPS(gc5024_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) gc5024_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static const struct v4l2_subdev_internal_ops gc5024_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .open = gc5024_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const struct v4l2_subdev_core_ops gc5024_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .s_power = gc5024_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .ioctl = gc5024_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .compat_ioctl32 = gc5024_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static const struct v4l2_subdev_video_ops gc5024_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .g_mbus_config = sensor_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .s_stream = gc5024_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .g_frame_interval = gc5024_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static const struct v4l2_subdev_pad_ops gc5024_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .enum_mbus_code = gc5024_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .enum_frame_size = gc5024_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .enum_frame_interval = gc5024_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .get_fmt = gc5024_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .set_fmt = gc5024_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static const struct v4l2_subdev_ops gc5024_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .core = &gc5024_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .video = &gc5024_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .pad = &gc5024_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static int gc5024_set_gain_reg(struct gc5024 *gc5024, u32 a_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) u32 temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ret = gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) GC5024_PAGE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (a_gain >= GC5024_ANALOG_GAIN_1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) a_gain < GC5024_ANALOG_GAIN_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) GC5024_ANALOG_GAIN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) temp = a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) GC5024_PREGAIN_H_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) temp >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) GC5024_PREGAIN_L_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) (temp << 2) & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) } else if (a_gain >= GC5024_ANALOG_GAIN_2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) a_gain < GC5024_ANALOG_GAIN_3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) GC5024_ANALOG_GAIN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) temp = 64 * a_gain / GC5024_ANALOG_GAIN_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) GC5024_PREGAIN_H_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) temp >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) GC5024_PREGAIN_L_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) (temp << 2) & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) } else if (a_gain >= GC5024_ANALOG_GAIN_3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) a_gain < GC5024_ANALOG_GAIN_4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) GC5024_ANALOG_GAIN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) temp = 64 * a_gain / GC5024_ANALOG_GAIN_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) GC5024_PREGAIN_H_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) temp >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) GC5024_PREGAIN_L_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) (temp << 2) & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) } else if (a_gain >= GC5024_ANALOG_GAIN_4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) a_gain < GC5024_ANALOG_GAIN_5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) GC5024_ANALOG_GAIN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) temp = 64 * a_gain / GC5024_ANALOG_GAIN_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) GC5024_PREGAIN_H_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) temp >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) GC5024_PREGAIN_L_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) (temp << 2) & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) } else if (a_gain >= GC5024_ANALOG_GAIN_5 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) a_gain < GC5024_ANALOG_GAIN_6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) GC5024_ANALOG_GAIN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) temp = 64 * a_gain / GC5024_ANALOG_GAIN_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) GC5024_PREGAIN_H_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) temp >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) GC5024_PREGAIN_L_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) (temp << 2) & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) } else if (a_gain >= GC5024_ANALOG_GAIN_6 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) a_gain < GC5024_ANALOG_GAIN_7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) GC5024_ANALOG_GAIN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) temp = 64 * a_gain / GC5024_ANALOG_GAIN_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) GC5024_PREGAIN_H_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) temp >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) GC5024_PREGAIN_L_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) (temp << 2) & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) GC5024_ANALOG_GAIN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) temp = 64 * a_gain / GC5024_ANALOG_GAIN_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) GC5024_PREGAIN_H_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) temp >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) GC5024_PREGAIN_L_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) (temp << 2) & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static int gc5024_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct gc5024 *gc5024 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct gc5024, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct i2c_client *client = gc5024->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) max = gc5024->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) __v4l2_ctrl_modify_range(gc5024->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) gc5024->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) gc5024->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) gc5024->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) GC5024_PAGE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) GC5024_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) (ctrl->val >> 8) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) GC5024_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ctrl->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ret = gc5024_set_gain_reg(gc5024, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ret = gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) GC5024_PAGE_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) GC5024_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ((ctrl->val) >> 8) & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ret |= gc5024_write_reg(gc5024->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) GC5024_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) (ctrl->val) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static const struct v4l2_ctrl_ops gc5024_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .s_ctrl = gc5024_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static int gc5024_initialize_controls(struct gc5024 *gc5024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) const struct gc5024_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct device *dev = &gc5024->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) dev_info(dev, "Enter %s(%d) !\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) handler = &gc5024->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) mode = gc5024->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) handler->lock = &gc5024->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) 0, GC5024_PIXEL_RATE, 1, GC5024_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) gc5024->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (gc5024->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) gc5024->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) gc5024->vblank = v4l2_ctrl_new_std(handler, &gc5024_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) GC5024_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) gc5024->exposure = v4l2_ctrl_new_std(handler, &gc5024_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) V4L2_CID_EXPOSURE, GC5024_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) exposure_max, GC5024_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) gc5024->anal_gain = v4l2_ctrl_new_std(handler, &gc5024_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) V4L2_CID_ANALOGUE_GAIN, GC5024_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) GC5024_GAIN_MAX, GC5024_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) GC5024_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) dev_err(&gc5024->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) gc5024->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static int gc5024_check_sensor_id(struct gc5024 *gc5024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct device *dev = &gc5024->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) u8 pid, ver = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) unsigned short id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ret = gc5024_read_reg(client, GC5024_REG_CHIP_ID_H, &pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) dev_err(dev, "Read chip ID H register error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ret = gc5024_read_reg(client, GC5024_REG_CHIP_ID_L, &ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) dev_err(dev, "Read chip ID L register error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) id = SENSOR_ID(pid, ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) dev_info(dev, "detected gc%04x sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static int gc5024_configure_regulators(struct gc5024 *gc5024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) for (i = 0; i < GC5024_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) gc5024->supplies[i].supply = gc5024_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return devm_regulator_bulk_get(&gc5024->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) GC5024_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) gc5024->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static int gc5024_parse_of(struct gc5024 *gc5024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct device *dev = &gc5024->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) fwnode = of_fwnode_handle(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (rval <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) dev_warn(dev, " Get mipi lane num failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) gc5024->lane_num = rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (2 == gc5024->lane_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) gc5024->cur_mode = &supported_modes_2lane[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) supported_modes = supported_modes_2lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) gc5024->cfg_num = ARRAY_SIZE(supported_modes_2lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) gc5024->pixel_rate = MIPI_FREQ * 2U * gc5024->lane_num / 10U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) gc5024->lane_num, gc5024->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) dev_err(dev, "unsupported lane_num(%d)\n", gc5024->lane_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static int gc5024_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct gc5024 *gc5024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) gc5024 = devm_kzalloc(dev, sizeof(*gc5024), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (!gc5024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) &gc5024->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) &gc5024->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) &gc5024->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) &gc5024->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) gc5024->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) gc5024->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (IS_ERR(gc5024->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) gc5024->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (IS_ERR(gc5024->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) gc5024->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (IS_ERR(gc5024->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ret = gc5024_parse_of(gc5024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) gc5024->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (!IS_ERR(gc5024->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) gc5024->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) pinctrl_lookup_state(gc5024->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (IS_ERR(gc5024->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) gc5024->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) pinctrl_lookup_state(gc5024->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (IS_ERR(gc5024->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) ret = gc5024_configure_regulators(gc5024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) mutex_init(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) sd = &gc5024->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) v4l2_i2c_subdev_init(sd, client, &gc5024_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ret = gc5024_initialize_controls(gc5024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ret = __gc5024_power_on(gc5024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) ret = gc5024_check_sensor_id(gc5024, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) sd->internal_ops = &gc5024_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) gc5024->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) ret = media_entity_pads_init(&sd->entity, 1, &gc5024->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (strcmp(gc5024->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) gc5024->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) GC5024_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) __gc5024_power_off(gc5024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) v4l2_ctrl_handler_free(&gc5024->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) mutex_destroy(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static int gc5024_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct gc5024 *gc5024 = to_gc5024(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) v4l2_ctrl_handler_free(&gc5024->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) mutex_destroy(&gc5024->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) __gc5024_power_off(gc5024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) static const struct of_device_id gc5024_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) { .compatible = "galaxycore,gc5024" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) MODULE_DEVICE_TABLE(of, gc5024_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) static const struct i2c_device_id gc5024_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) { "galaxycore,gc5024", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static struct i2c_driver gc5024_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .name = GC5024_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .pm = &gc5024_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .of_match_table = of_match_ptr(gc5024_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .probe = &gc5024_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .remove = &gc5024_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .id_table = gc5024_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) return i2c_add_driver(&gc5024_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) i2c_del_driver(&gc5024_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) MODULE_DESCRIPTION("GC5024 CMOS Image Sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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