^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * gc4c33 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 fix gain range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X05 fix gain reg, add otp and dpc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * V0.0X01.0X06 add set dpc cfg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * V0.0X01.0X07 support enum sensor fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * V0.0X01.0X08 support mirror and flip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * V0.0X01.0X09 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GC4C33_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GC4C33_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GC4C33_LINK_FREQ 315000000 //2560*1440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) //#define GC4C33_LINK_FREQ 157500000 //1920*1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) //#define GC4C33_LINK_FREQ 261000000 //1280*720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GC4C33_PIXEL_RATE (GC4C33_LINK_FREQ * 2 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) GC4C33_LANES / GC4C33_BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GC4C33_XVCLK_FREQ 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CHIP_ID 0x46c3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GC4C33_REG_CHIP_ID_H 0x03f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GC4C33_REG_CHIP_ID_L 0x03f1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GC4C33_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GC4C33_MODE_SW_STANDBY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GC4C33_MODE_STREAMING 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GC4C33_REG_EXPOSURE_H 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GC4C33_REG_EXPOSURE_L 0x0203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GC4C33_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GC4C33_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GC4C33_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GC4C33_GAIN_MIN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GC4C33_GAIN_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GC4C33_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GC4C33_GAIN_DEFAULT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GC4C33_REG_TEST_PATTERN 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GC4C33_TEST_PATTERN_ENABLE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GC4C33_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GC4C33_REG_VTS_H 0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GC4C33_REG_VTS_L 0x0341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GC4C33_REG_DPCC_ENABLE 0x00aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GC4C33_REG_DPCC_SINGLE 0x00a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GC4C33_REG_DPCC_DOUBLE 0x00a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GC4C33_FLIP_MIRROR_REG 0x0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GC4C33_MIRROR_BIT_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GC4C33_FLIP_BIT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GC4C33_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GC4C33_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GC4C33_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GC4C33_NAME "gc4c33"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GC4C33_ENABLE_DPCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GC4C33_ENABLE_OTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) //#define GC4C33_ENABLE_HIGHLIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const char * const gc4c33_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GC4C33_NUM_SUPPLIES ARRAY_SIZE(gc4c33_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct gc4c33_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct gc4c33 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct gpio_desc *pwren_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct regulator_bulk_data supplies[GC4C33_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct v4l2_ctrl *h_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct v4l2_ctrl *v_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const struct gc4c33_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define to_gc4c33(sd) container_of(sd, struct gc4c33, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct regval gc4c33_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const u32 reg_val_table[43][9] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x00, 0x39, 0x00, 0x39, 0x00, 0x00, 0x01, 0x00, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x00, 0x39, 0x00, 0x39, 0x08, 0x00, 0x01, 0x0B, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x00, 0x39, 0x00, 0x39, 0x01, 0x00, 0x01, 0x1B, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x00, 0x39, 0x00, 0x39, 0x09, 0x00, 0x01, 0x2A, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x00, 0x39, 0x00, 0x39, 0x10, 0x00, 0x01, 0x3E, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x00, 0x39, 0x00, 0x39, 0x18, 0x00, 0x02, 0x13, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x00, 0x39, 0x00, 0x39, 0x11, 0x00, 0x02, 0x33, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x00, 0x39, 0x00, 0x39, 0x19, 0x00, 0x03, 0x11, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x00, 0x39, 0x00, 0x39, 0x30, 0x00, 0x03, 0x3B, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x00, 0x39, 0x00, 0x39, 0x38, 0x00, 0x04, 0x26, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x00, 0x39, 0x00, 0x39, 0x31, 0x00, 0x05, 0x24, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x00, 0x39, 0x00, 0x39, 0x39, 0x00, 0x06, 0x21, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x00, 0x39, 0x00, 0x39, 0x32, 0x00, 0x07, 0x28, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x00, 0x39, 0x00, 0x39, 0x3a, 0x00, 0x08, 0x3C, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x00, 0x39, 0x00, 0x39, 0x33, 0x00, 0x0A, 0x3F, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x00, 0x39, 0x00, 0x39, 0x3b, 0x00, 0x0C, 0x38, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x00, 0x39, 0x00, 0x39, 0x34, 0x00, 0x0F, 0x17, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x00, 0x39, 0x00, 0x39, 0x3c, 0x00, 0x11, 0x3F, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x00, 0x39, 0x00, 0x39, 0xb4, 0x00, 0x15, 0x34, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x00, 0x39, 0x00, 0x39, 0xbc, 0x00, 0x19, 0x22, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x00, 0x39, 0x00, 0x39, 0x34, 0x01, 0x1E, 0x09, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x00, 0x39, 0x00, 0x39, 0x3c, 0x11, 0x1A, 0x31, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x00, 0x32, 0x00, 0x32, 0x3c, 0x11, 0x20, 0x12, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x00, 0x3a, 0x00, 0x3a, 0x3c, 0x11, 0x25, 0x28, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x00, 0x33, 0x00, 0x33, 0x3c, 0x11, 0x2D, 0x28, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x00, 0x3b, 0x00, 0x3b, 0x3c, 0x11, 0x35, 0x0A, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x00, 0x34, 0x00, 0x34, 0x3c, 0x11, 0x3F, 0x22, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x00, 0x3c, 0x00, 0x3c, 0x3c, 0x11, 0x4A, 0x02, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x00, 0xb4, 0x00, 0xb4, 0x3c, 0x11, 0x5A, 0x36, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x00, 0xbc, 0x00, 0xbc, 0x3c, 0x11, 0x69, 0x37, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x01, 0x34, 0x10, 0x34, 0x3c, 0x11, 0x7E, 0x13, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x01, 0x3c, 0x10, 0x3c, 0x3c, 0x11, 0x93, 0x0B, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x01, 0xb4, 0x10, 0xb4, 0x3c, 0x11, 0xB4, 0x19, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x01, 0xbc, 0x10, 0xbc, 0x3c, 0x11, 0xD2, 0x0E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x02, 0x34, 0x20, 0x34, 0x3c, 0x11, 0xFC, 0x0B, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x02, 0x3c, 0x20, 0x3c, 0x3c, 0x11, 0xff, 0xff, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x01, 0xf4, 0x10, 0xf4, 0x3c, 0x11, 0xff, 0xff, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x01, 0xfc, 0x10, 0xfc, 0x3c, 0x11, 0xff, 0xff, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x02, 0x74, 0x20, 0x74, 0x3c, 0x11, 0xff, 0xff, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x02, 0x7c, 0x20, 0x7c, 0x3c, 0x11, 0xff, 0xff, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x02, 0x75, 0x20, 0x75, 0x3c, 0x11, 0xff, 0xff, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x02, 0x7d, 0x20, 0x7d, 0x3c, 0x11, 0xff, 0xff, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x02, 0xf5, 0x20, 0xf5, 0x3c, 0x11, 0xff, 0xff, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const u32 gain_level_table[44] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 147,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 179,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 209,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 251,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 294,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 356,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 417,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 488,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 572,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 703,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 824,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 983,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 1151,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 1396,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 1634,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 1929,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 1702,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 2066,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 2377,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 2957,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 3402,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 4738,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 5814,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 6775,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 8083,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 9419,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 11545,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 13454,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 16139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 18808,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 22695,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 26447,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 31725,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 36971,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 44784,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 52188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 62977,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const u32 reg_Val_Table_720P[32][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x00, 0x00, 0x01, 0x00, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x08, 0x00, 0x01, 0x0A, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x01, 0x00, 0x01, 0x19, 0x1E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x09, 0x00, 0x01, 0x26, 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x10, 0x00, 0x01, 0x3F, 0x1A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x18, 0x00, 0x02, 0x13, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x11, 0x00, 0x02, 0x31, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x19, 0x00, 0x03, 0x0B, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x30, 0x00, 0x04, 0x04, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x38, 0x00, 0x04, 0x2C, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x31, 0x00, 0x05, 0x29, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x39, 0x00, 0x06, 0x1F, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x32, 0x00, 0x07, 0x38, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3a, 0x00, 0x09, 0x05, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x33, 0x00, 0x0B, 0x12, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3b, 0x00, 0x0D, 0x00, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x34, 0x00, 0x10, 0x03, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3c, 0x00, 0x12, 0x1E, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0xb4, 0x00, 0x16, 0x00, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0xbc, 0x00, 0x19, 0x15, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x34, 0x01, 0x1F, 0x06, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x3c, 0x01, 0x23, 0x33, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0xb4, 0x01, 0x2C, 0x22, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0xbc, 0x01, 0x33, 0x12, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x34, 0x02, 0x3F, 0x10, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3c, 0x02, 0x48, 0x34, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0xf4, 0x01, 0x5F, 0x06, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0xfc, 0x01, 0x6D, 0x1E, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x74, 0x02, 0x87, 0x00, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x7c, 0x02, 0x9B, 0x19, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x75, 0x02, 0xC7, 0x07, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x7d, 0x02, 0xE5, 0x0B, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const u32 gain_Level_Table_720P[32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 147,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 177,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 361,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 415,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 504,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 581,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 722,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 832,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 1027,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 1182,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 1408,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 1621,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 1990,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 2291,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 2850,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 3282,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 4048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 4660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 6086,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 7006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 8640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 9945,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 12743,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 14667,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * mipi_datarate per lane 630Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct regval gc4c33_linear10bit_2560x1440_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x03fe, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x03fe, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x03fe, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x03fe, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x031c, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x0317, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x0320, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x0106, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x0324, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x0327, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x0325, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x0326, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x031a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x0314, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x0315, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x0334, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x0337, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x0335, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x0336, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x0324, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x0334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x031c, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x0180, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x031c, 0xd6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x0287, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x02ee, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x0202, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x0203, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x0213, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x0214, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x0290, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x029d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x0340, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x0341, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x0342, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x0343, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x00f2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x00f1, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x00f0, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x00c1, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x00c2, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x00c3, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x00c4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x00da, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x00db, 0xa0},//1440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x00d8, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x00d9, 0x00},//2560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x00c5, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x00c6, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x00bf, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x00ce, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x00cd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x00cf, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x023c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x02d1, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x027d, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x0238, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x02ce, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x02f9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x0227, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x0232, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x0245, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x027d, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x02fa, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x02e7, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x02e8, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x021d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x0220, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x0228, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x022c, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x024b, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x024e, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x024d, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x0255, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x025b, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x0262, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x02d4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x0540, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x0239, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x0231, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x024f, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x028c, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x02d3, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x02da, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x02db, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x02e6, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x0512, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x0513, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x0515, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x0518, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x0519, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x051d, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x0216, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x0221, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x0223, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x0225, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x0229, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x022b, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x022e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x0230, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x023a, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x027b, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x027c, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x0298, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x02a4, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x02ab, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x02ac, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x02ad, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x02af, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x02cd, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x02d2, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x02e4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x0530, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x0531, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x0243, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x0219, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x02e5, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x0338, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x0339, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x033a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x023b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x0212, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x0523, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x0347, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x0348, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x0349, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x034a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x034b, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x0097, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x0098, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x0099, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x009a, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x034c, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x034d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x034e, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x034f, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x0354, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x0352, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x0295, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x0296, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x02f0, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x02f1, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x02f2, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x02f4, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x02f5, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x02f6, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x02f7, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x02f8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x0291, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x0292, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x0297, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x02d5, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x02d6, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x02d7, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x0268, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x0269, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x0272, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x0273, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x0274, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x0275, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x0276, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x0277, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x0278, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x0279, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x0555, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x0556, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x0557, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x0558, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x0559, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x055a, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x055b, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x055c, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x055d, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x055e, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x0550, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x0551, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x0552, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x0553, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x0554, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x0220, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x021f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x0233, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x0234, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x02be, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x00a0, 0x5d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x00c7, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x00c8, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x00df, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x00de, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x00c0, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x031c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x031f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x031f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x031c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x031f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x031f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x031c, 0xd6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x0053, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x008e, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x0205, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x02b0, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x02b1, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x02b3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x02b4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x02fc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x02fd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x0263, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x0267, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x0451, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x0455, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x0452, 0xE6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x0456, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x0450, 0xAB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x0454, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x0453, 0xAB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x0457, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x0226, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x0042, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x0458, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x0459, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x045a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x045b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x044c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x044d, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x044e, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x044f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x0060, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x00e1, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x00e2, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x00e4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x00e5, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x00e6, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x00e7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x00e8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x00e9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x00ea, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x00ef, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x00a9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x00b3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x00b4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x00b5, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x00b6, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x00b7, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x00d1, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x00d2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x00d4, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x00d5, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x0089, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x008c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x0080, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x0180, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x0181, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x0182, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x0185, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x0114, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x0115, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x0103, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x0104, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x00aa, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x00a7, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x00a8, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x00a1, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x00a2, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * mipi_datarate per lane 522Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const struct regval gc4c33_linear10bit_1280x720_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x031c, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x0317, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x0320, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x0106, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x0324, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x0327, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x0325, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x0326, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x031a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x0314, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x0315, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x0334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x0337, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x0335, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x0336, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x0324, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x0334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x031c, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x0180, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {0x031c, 0xd6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {0x0287, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {0x02ee, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {0x0202, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {0x0203, 0xa6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {0x0213, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {0x0214, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {0x0290, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {0x029d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0x0340, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {0x0341, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {0x0342, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {0x0343, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {0x023c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {0x02d1, 0xe2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {0x027d, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {0x0238, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {0x02ce, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {0x02f9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {0x0227, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {0x0232, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x0245, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x027d, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x02fa, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x02e7, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x02e8, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {0x021d, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {0x0220, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {0x0228, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {0x022c, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {0x02c0, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {0x024b, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {0x024e, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {0x024d, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {0x0255, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {0x025b, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {0x0262, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {0x02d4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {0x0540, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {0x0239, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {0x0231, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {0x024f, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {0x028c, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {0x02d3, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {0x02da, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {0x02db, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {0x02e6, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {0x0512, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {0x0513, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {0x0515, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {0x0518, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {0x0519, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {0x051d, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {0x0216, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {0x0221, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {0x0223, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {0x0225, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {0x0229, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {0x022b, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {0x022e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {0x0230, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {0x023a, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {0x027b, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {0x027c, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {0x0298, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {0x02a4, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {0x02ab, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {0x02ac, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {0x02ad, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {0x02af, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {0x02cd, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {0x02d2, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {0x02e4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {0x0530, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {0x0531, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {0x0243, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {0x0219, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {0x02e5, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {0x0338, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {0x0339, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {0x033a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {0x023b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {0x0212, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {0x0523, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {0x0347, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {0x0348, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {0x0349, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {0x034a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {0x034b, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {0x034c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {0x034d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {0x034e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {0x034f, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {0x0354, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {0x0295, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {0x0296, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {0x02f0, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0x02f1, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0x02f2, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0x02f4, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0x02f5, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {0x02f6, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {0x02f7, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {0x02f8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {0x0291, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {0x0292, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {0x0297, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {0x02d5, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {0x02d6, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {0x02d7, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {0x021f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {0x0233, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {0x0234, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0x0224, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {0x031c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {0x031f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {0x031f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {0x031c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {0x031f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {0x031f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {0x031c, 0xd6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {0x0053, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {0x008e, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {0x0205, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {0x02b0, 0xf2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {0x02b1, 0xf2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {0x02b3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {0x02b4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {0x0451, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {0x0455, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {0x0452, 0xE6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {0x0456, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {0x0450, 0xAB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {0x0454, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {0x0453, 0xAB},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {0x0457, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {0x0226, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {0x0042, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {0x0458, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {0x0459, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {0x045a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {0x045b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {0x044c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {0x044d, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {0x044e, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {0x044f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {0x0060, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {0x00a0, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {0x00c7, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {0x00c8, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {0x00e1, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {0x00e2, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {0x00e4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {0x00e5, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {0x00e6, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {0x00e7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {0x00e8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {0x00e9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {0x00ea, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {0x00ef, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {0x0089, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {0x008c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {0x0080, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {0x0180, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {0x0181, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {0x0182, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {0x0185, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {0x0114, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {0x0115, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {0x0103, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {0x0104, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {0x00aa, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {0x00a7, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {0x00a8, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {0x00a1, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {0x00a2, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * mipi_datarate per lane 630Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static const struct regval gc4c33_linear10bit_1920x1080_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {0x031c, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {0x0317, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {0x0320, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {0x0106, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {0x0324, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {0x0327, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {0x0325, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {0x0326, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {0x031a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {0x0314, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {0x0315, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {0x0334, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {0x0337, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {0x0335, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {0x0336, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {0x0324, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {0x0334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {0x031c, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {0x0180, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {0x031c, 0xd6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {0x0287, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {0x02ee, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {0x0202, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {0x0203, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {0x0213, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {0x0214, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {0x0290, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {0x029d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {0x0340, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {0x0341, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {0x0342, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {0x0343, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {0x00f2, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {0x00f1, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {0x00f0, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {0x00c5, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {0x00c6, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {0x00bf, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {0x00ce, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {0x00cd, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {0x00cf, 0xe9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {0x023c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {0x02d1, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {0x027d, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {0x0238, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {0x02ce, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {0x02f9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {0x0227, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {0x0232, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {0x0245, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {0x027d, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {0x02fa, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {0x02e7, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {0x02e8, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {0x021d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {0x0220, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {0x0228, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {0x022c, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {0x024b, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {0x024e, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {0x024d, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {0x0255, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {0x025b, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {0x0262, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {0x02d4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {0x0540, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {0x0239, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {0x0231, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {0x024f, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {0x028c, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {0x02d3, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {0x02da, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {0x02db, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {0x02e6, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {0x0512, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {0x0513, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {0x0515, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {0x0518, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {0x0519, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {0x051d, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {0x0211, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {0x0216, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {0x0221, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {0x0223, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {0x0225, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {0x0229, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {0x022b, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {0x022e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {0x0230, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {0x023a, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {0x027b, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {0x027c, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {0x0298, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {0x02a4, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {0x02ab, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {0x02ac, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {0x02ad, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {0x02af, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {0x02cd, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {0x02d2, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {0x02e4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {0x0530, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {0x0531, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {0x0243, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {0x0219, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {0x02e5, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {0x0338, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {0x0339, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {0x033a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {0x023b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {0x0212, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {0x0523, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {0x0347, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {0x0348, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {0x0349, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {0x034a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {0x034b, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {0x034c, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {0x034d, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {0x034e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {0x034f, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {0x0354, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {0x0295, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {0x0296, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {0x02f0, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {0x02f1, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {0x02f2, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {0x02f4, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {0x02f5, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {0x02f6, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {0x02f7, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {0x02f8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {0x0291, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {0x0292, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {0x0297, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {0x02d5, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {0x02d6, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {0x02d7, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {0x0268, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {0x0269, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {0x0272, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {0x0273, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {0x0274, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {0x0275, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {0x0276, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {0x0277, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {0x0278, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {0x0279, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {0x0555, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {0x0556, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {0x0557, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {0x0558, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {0x0559, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {0x055a, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {0x055b, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {0x055c, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {0x055d, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {0x055e, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {0x0550, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {0x0551, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {0x0552, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {0x0553, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {0x0554, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {0x0220, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {0x021f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {0x0233, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {0x0234, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {0x02be, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {0x00a0, 0x5d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {0x00c7, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {0x00c8, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {0x00df, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {0x00de, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {0x00aa, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {0x00c0, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {0x00c1, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {0x00c2, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {0x00c3, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {0x00c4, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {0x031c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {0x031f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {0x031f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {0x031c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {0x031c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {0x031f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {0x031f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {0x031c, 0xd6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {0x0053, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {0x008e, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {0x0205, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {0x02b0, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {0x02b1, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {0x02b3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {0x02b4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {0x02fc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {0x02fd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {0x0263, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {0x0267, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {0x0451, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {0x0455, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {0x0452, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {0x0456, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {0x0450, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {0x0454, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {0x0453, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {0x0457, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {0x0226, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {0x0042, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {0x0458, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {0x0459, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {0x045a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {0x045b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {0x044c, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {0x044d, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {0x044e, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {0x044f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {0x0060, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {0x00e1, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {0x00e2, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {0x00e4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {0x00e5, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {0x00e6, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {0x00e7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {0x00e8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {0x00e9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {0x00ea, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {0x00ef, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {0x00a1, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {0x00a2, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {0x00a7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {0x00a8, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {0x00a9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {0x00b3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {0x00b4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {0x00b5, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {0x00b6, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {0x00b7, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {0x00d1, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {0x00d2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {0x00d4, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {0x00d5, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {0x0089, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {0x008c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {0x0080, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {0x0180, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {0x0181, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {0x0182, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {0x0185, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {0x0114, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {0x0115, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {0x0103, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {0x0104, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {0x00aa, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {0x00a7, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {0x00a8, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {0x00a1, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {0x00a2, 0xFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static const struct gc4c33_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .width = 2560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .height = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .exp_def = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .hts_def = 0x0AA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .vts_def = 0x05DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .reg_list = gc4c33_linear10bit_2560x1440_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .exp_def = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .hts_def = 0x0E2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .vts_def = 0x0465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .reg_list = gc4c33_linear10bit_1920x1080_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .height = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .exp_def = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .hts_def = 0x0855,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .vts_def = 0x02EE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .reg_list = gc4c33_linear10bit_1280x720_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) GC4C33_LINK_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static const char * const gc4c33_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static int gc4c33_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static int gc4c33_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ret = gc4c33_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) GC4C33_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static int gc4c33_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static int gc4c33_get_reso_dist(const struct gc4c33_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static const struct gc4c33_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) gc4c33_find_best_fit(struct gc4c33 *gc4c33, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) for (i = 0; i < gc4c33->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) dist = gc4c33_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static int gc4c33_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct gc4c33 *gc4c33 = to_gc4c33(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) const struct gc4c33_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) mutex_lock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) mode = gc4c33_find_best_fit(gc4c33, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) mutex_unlock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) gc4c33->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) __v4l2_ctrl_modify_range(gc4c33->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) __v4l2_ctrl_modify_range(gc4c33->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) GC4C33_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) mutex_unlock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static int gc4c33_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct gc4c33 *gc4c33 = to_gc4c33(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) const struct gc4c33_mode *mode = gc4c33->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) mutex_lock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) mutex_unlock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) mutex_unlock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static int gc4c33_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) struct gc4c33 *gc4c33 = to_gc4c33(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) code->code = gc4c33->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static int gc4c33_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct gc4c33 *gc4c33 = to_gc4c33(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (fse->index >= gc4c33->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static int gc4c33_enable_test_pattern(struct gc4c33 *gc4c33, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) val = (pattern - 1) | GC4C33_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) val = GC4C33_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return gc4c33_write_reg(gc4c33->client, GC4C33_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) GC4C33_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static int gc4c33_set_gain_reg(struct gc4c33 *gc4c33, u32 gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) int total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) u32 tol_dig_gain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (gain < 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) gain = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) total = sizeof(gain_level_table) / sizeof(u32) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) for (i = 0; i < total; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (gain_level_table[i] <= gain &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) gain < gain_level_table[i + 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) tol_dig_gain = gain * 64 / gain_level_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (i >= total)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) i = total - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) gc4c33_write_reg(gc4c33->client, 0x31d, GC4C33_REG_VALUE_08BIT, 0x2a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) gc4c33_write_reg(gc4c33->client, 0x2fd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) GC4C33_REG_VALUE_08BIT, reg_val_table[i][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) gc4c33_write_reg(gc4c33->client, 0x2fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) GC4C33_REG_VALUE_08BIT, reg_val_table[i][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) gc4c33_write_reg(gc4c33->client, 0x263,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) GC4C33_REG_VALUE_08BIT, reg_val_table[i][2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) gc4c33_write_reg(gc4c33->client, 0x267,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) GC4C33_REG_VALUE_08BIT, reg_val_table[i][3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) gc4c33_write_reg(gc4c33->client, 0x31d, GC4C33_REG_VALUE_08BIT, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) gc4c33_write_reg(gc4c33->client, 0x2b3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) GC4C33_REG_VALUE_08BIT, reg_val_table[i][4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) gc4c33_write_reg(gc4c33->client, 0x2b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) GC4C33_REG_VALUE_08BIT, reg_val_table[i][5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) gc4c33_write_reg(gc4c33->client, 0x2b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) GC4C33_REG_VALUE_08BIT, reg_val_table[i][6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) gc4c33_write_reg(gc4c33->client, 0x2b9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) GC4C33_REG_VALUE_08BIT, reg_val_table[i][7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) gc4c33_write_reg(gc4c33->client, 0x515,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) GC4C33_REG_VALUE_08BIT, reg_val_table[i][8]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) gc4c33_write_reg(gc4c33->client, 0x20e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) GC4C33_REG_VALUE_08BIT, (tol_dig_gain >> 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) gc4c33_write_reg(gc4c33->client, 0x20f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) GC4C33_REG_VALUE_08BIT, ((tol_dig_gain & 0x3f) << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static int gc4c33_set_gain_reg_720P(struct gc4c33 *gc4c33, u32 gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) int total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) u32 tol_dig_gain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) total = sizeof(gain_Level_Table_720P) / sizeof(u32) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) for (i = 0; i < total; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (gain_Level_Table_720P[i] <= gain &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) gain < gain_Level_Table_720P[i + 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (gain == gain_Level_Table_720P[total])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) i = total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) tol_dig_gain = gain * 64 / gain_Level_Table_720P[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) gc4c33_write_reg(gc4c33->client, 0x2b3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) GC4C33_REG_VALUE_08BIT, reg_Val_Table_720P[i][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) gc4c33_write_reg(gc4c33->client, 0x2b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) GC4C33_REG_VALUE_08BIT, reg_Val_Table_720P[i][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) gc4c33_write_reg(gc4c33->client, 0x2b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) GC4C33_REG_VALUE_08BIT, reg_Val_Table_720P[i][2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) gc4c33_write_reg(gc4c33->client, 0x2b9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) GC4C33_REG_VALUE_08BIT, reg_Val_Table_720P[i][3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) gc4c33_write_reg(gc4c33->client, 0x515,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) GC4C33_REG_VALUE_08BIT, reg_Val_Table_720P[i][4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) gc4c33_write_reg(gc4c33->client, 0x20e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) GC4C33_REG_VALUE_08BIT, (tol_dig_gain >> 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) gc4c33_write_reg(gc4c33->client, 0x20f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) GC4C33_REG_VALUE_08BIT, ((tol_dig_gain & 0x3f) << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) static int gc4c33_set_dpcc_cfg(struct gc4c33 *gc4c33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) struct rkmodule_dpcc_cfg *dpcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #ifdef GC4C33_ENABLE_DPCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (dpcc->enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) ret = gc4c33_write_reg(gc4c33->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) GC4C33_REG_DPCC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) GC4C33_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) 0x38 | (dpcc->enable & 0x03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) ret |= gc4c33_write_reg(gc4c33->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) GC4C33_REG_DPCC_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) GC4C33_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) 255 - dpcc->cur_single_dpcc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) 255 / dpcc->total_dpcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ret |= gc4c33_write_reg(gc4c33->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) GC4C33_REG_DPCC_DOUBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) GC4C33_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) 255 - dpcc->cur_multiple_dpcc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) 255 / dpcc->total_dpcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) ret = gc4c33_write_reg(gc4c33->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) GC4C33_REG_DPCC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) GC4C33_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ret |= gc4c33_write_reg(gc4c33->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) GC4C33_REG_DPCC_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) GC4C33_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) ret |= gc4c33_write_reg(gc4c33->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) GC4C33_REG_DPCC_DOUBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) GC4C33_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) ret = gc4c33_write_reg(gc4c33->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) GC4C33_REG_DPCC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) GC4C33_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) ret |= gc4c33_write_reg(gc4c33->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) GC4C33_REG_DPCC_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) GC4C33_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) ret |= gc4c33_write_reg(gc4c33->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) GC4C33_REG_DPCC_DOUBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) GC4C33_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static int gc4c33_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) struct gc4c33 *gc4c33 = to_gc4c33(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) const struct gc4c33_mode *mode = gc4c33->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) mutex_lock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) mutex_unlock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static int gc4c33_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) struct gc4c33 *gc4c33 = to_gc4c33(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) const struct gc4c33_mode *mode = gc4c33->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) u32 val = 1 << (GC4C33_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static void gc4c33_get_module_inf(struct gc4c33 *gc4c33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) strlcpy(inf->base.sensor, GC4C33_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) strlcpy(inf->base.module, gc4c33->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) strlcpy(inf->base.lens, gc4c33->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static int gc4c33_get_channel_info(struct gc4c33 *gc4c33, struct rkmodule_channel_info *ch_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ch_info->vc = gc4c33->cur_mode->vc[ch_info->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) ch_info->width = gc4c33->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) ch_info->height = gc4c33->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) ch_info->bus_fmt = gc4c33->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static long gc4c33_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) struct gc4c33 *gc4c33 = to_gc4c33(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) struct rkmodule_nr_switch_threshold *nr_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) gc4c33_get_module_inf(gc4c33, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) hdr->hdr_mode = gc4c33->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) w = gc4c33->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) h = gc4c33->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) for (i = 0; i < gc4c33->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) gc4c33->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (i == gc4c33->cfg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) dev_err(&gc4c33->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) w = gc4c33->cur_mode->hts_def -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) gc4c33->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) h = gc4c33->cur_mode->vts_def -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) gc4c33->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) __v4l2_ctrl_modify_range(gc4c33->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) __v4l2_ctrl_modify_range(gc4c33->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) GC4C33_VTS_MAX -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) gc4c33->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) case RKMODULE_SET_DPCC_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) ret = gc4c33_set_dpcc_cfg(gc4c33, (struct rkmodule_dpcc_cfg *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) case RKMODULE_GET_NR_SWITCH_THRESHOLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) nr_switch = (struct rkmodule_nr_switch_threshold *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) nr_switch->direct = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) nr_switch->up_thres = 3014;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) nr_switch->down_thres = 3014;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) nr_switch->div_coeff = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) ret = gc4c33_write_reg(gc4c33->client, GC4C33_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) GC4C33_REG_VALUE_08BIT, GC4C33_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) ret = gc4c33_write_reg(gc4c33->client, GC4C33_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) GC4C33_REG_VALUE_08BIT, GC4C33_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) ch_info = (struct rkmodule_channel_info *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) ret = gc4c33_get_channel_info(gc4c33, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) static long gc4c33_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct rkmodule_dpcc_cfg *dpcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct rkmodule_nr_switch_threshold *nr_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) ret = gc4c33_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ret = gc4c33_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) ret = gc4c33_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) ret = gc4c33_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) case RKMODULE_SET_DPCC_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) dpcc = kzalloc(sizeof(*dpcc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) if (!dpcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) ret = copy_from_user(dpcc, up, sizeof(*dpcc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ret = gc4c33_ioctl(sd, cmd, dpcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) kfree(dpcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) ret = gc4c33_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) case RKMODULE_GET_NR_SWITCH_THRESHOLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) nr_switch = kzalloc(sizeof(*nr_switch), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) if (!nr_switch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) ret = gc4c33_ioctl(sd, cmd, nr_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) ret = copy_to_user(up, nr_switch, sizeof(*nr_switch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) kfree(nr_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) ret = gc4c33_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) if (!ch_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) ret = gc4c33_ioctl(sd, cmd, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) ret = copy_to_user(up, ch_info, sizeof(*ch_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) kfree(ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) #ifdef GC4C33_ENABLE_OTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static int gc4c33_sensor_dpc_otp_dd(struct gc4c33 *gc4c33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) u32 num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) ret = gc4c33_write_reg(gc4c33->client, 0x0a70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) GC4C33_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ret |= gc4c33_write_reg(gc4c33->client, 0x0317,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) GC4C33_REG_VALUE_08BIT, 0x2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) ret |= gc4c33_write_reg(gc4c33->client, 0x0a67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) GC4C33_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) ret |= gc4c33_write_reg(gc4c33->client, 0x0a4f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) GC4C33_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) ret |= gc4c33_write_reg(gc4c33->client, 0x0a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) GC4C33_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) ret |= gc4c33_write_reg(gc4c33->client, 0x0a66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) GC4C33_REG_VALUE_08BIT, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) ret |= gc4c33_write_reg(gc4c33->client, 0x0a69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) GC4C33_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) ret |= gc4c33_write_reg(gc4c33->client, 0x0a6a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) GC4C33_REG_VALUE_08BIT, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ret |= gc4c33_write_reg(gc4c33->client, 0x0313,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) GC4C33_REG_VALUE_08BIT, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) ret |= gc4c33_read_reg(gc4c33->client, 0x0a6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) GC4C33_REG_VALUE_08BIT, &num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) ret |= gc4c33_write_reg(gc4c33->client, 0x0a69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) GC4C33_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) ret |= gc4c33_write_reg(gc4c33->client, 0x0a6a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) GC4C33_REG_VALUE_08BIT, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) ret |= gc4c33_write_reg(gc4c33->client, 0x0313,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) GC4C33_REG_VALUE_08BIT, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) if (num != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) ret |= gc4c33_write_reg(gc4c33->client, 0x0317,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) GC4C33_REG_VALUE_08BIT, 0x2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) ret |= gc4c33_write_reg(gc4c33->client, 0x0a67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) GC4C33_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) ret |= gc4c33_write_reg(gc4c33->client, 0x0a66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) GC4C33_REG_VALUE_08BIT, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ret |= gc4c33_write_reg(gc4c33->client, 0x0a70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) GC4C33_REG_VALUE_08BIT, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) ret |= gc4c33_write_reg(gc4c33->client, 0x0a71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) GC4C33_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) ret |= gc4c33_write_reg(gc4c33->client, 0x0a72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) GC4C33_REG_VALUE_08BIT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) ret |= gc4c33_write_reg(gc4c33->client, 0x0a73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) GC4C33_REG_VALUE_08BIT, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) ret |= gc4c33_write_reg(gc4c33->client, 0x0a74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) GC4C33_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) ret |= gc4c33_write_reg(gc4c33->client, 0x0a75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) GC4C33_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) ret |= gc4c33_write_reg(gc4c33->client, 0x05be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) GC4C33_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) ret |= gc4c33_write_reg(gc4c33->client, 0x05a9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) GC4C33_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) usleep_range(30 * 1000, 30 * 1000 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) ret |= gc4c33_write_reg(gc4c33->client, 0x0313,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) GC4C33_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) usleep_range(120 * 1000, 120 * 1000 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) ret |= gc4c33_write_reg(gc4c33->client, 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) GC4C33_REG_VALUE_08BIT, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) ret |= gc4c33_write_reg(gc4c33->client, 0x05be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) GC4C33_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) ret |= gc4c33_write_reg(gc4c33->client, 0x0a70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) GC4C33_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) ret |= gc4c33_write_reg(gc4c33->client, 0x0a69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) GC4C33_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ret |= gc4c33_write_reg(gc4c33->client, 0x0a6a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) GC4C33_REG_VALUE_08BIT, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ret |= gc4c33_write_reg(gc4c33->client, 0x0313,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) GC4C33_REG_VALUE_08BIT, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) ret |= gc4c33_write_reg(gc4c33->client, 0x0317,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) GC4C33_REG_VALUE_08BIT, 0x2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) ret |= gc4c33_write_reg(gc4c33->client, 0x0a67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) GC4C33_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) ret |= gc4c33_write_reg(gc4c33->client, 0x0a4f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) GC4C33_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) ret |= gc4c33_write_reg(gc4c33->client, 0x0a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) GC4C33_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) ret |= gc4c33_write_reg(gc4c33->client, 0x0a66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) GC4C33_REG_VALUE_08BIT, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) ret |= gc4c33_write_reg(gc4c33->client, 0x0a69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) GC4C33_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) ret |= gc4c33_write_reg(gc4c33->client, 0x0a6a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) GC4C33_REG_VALUE_08BIT, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) ret |= gc4c33_write_reg(gc4c33->client, 0x0313,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) GC4C33_REG_VALUE_08BIT, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #ifdef GC4C33_ENABLE_HIGHLIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) ret |= gc4c33_write_reg(gc4c33->client, 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) GC4C33_REG_VALUE_08BIT, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) ret |= gc4c33_write_reg(gc4c33->client, 0x0090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) GC4C33_REG_VALUE_08BIT, 0x49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) ret |= gc4c33_write_reg(gc4c33->client, 0x05be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) GC4C33_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static int __gc4c33_start_stream(struct gc4c33 *gc4c33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) ret = gc4c33_write_array(gc4c33->client, gc4c33->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) #ifdef GC4C33_ENABLE_OTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) ret = gc4c33_sensor_dpc_otp_dd(gc4c33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) mutex_unlock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) ret = v4l2_ctrl_handler_setup(&gc4c33->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) mutex_lock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) return gc4c33_write_reg(gc4c33->client, GC4C33_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) GC4C33_REG_VALUE_08BIT, GC4C33_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) static int __gc4c33_stop_stream(struct gc4c33 *gc4c33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) return gc4c33_write_reg(gc4c33->client, GC4C33_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) GC4C33_REG_VALUE_08BIT, GC4C33_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) static int gc4c33_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) struct gc4c33 *gc4c33 = to_gc4c33(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) struct i2c_client *client = gc4c33->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) mutex_lock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (on == gc4c33->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) ret = __gc4c33_start_stream(gc4c33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) __gc4c33_stop_stream(gc4c33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) gc4c33->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) mutex_unlock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) static int gc4c33_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) struct gc4c33 *gc4c33 = to_gc4c33(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) struct i2c_client *client = gc4c33->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) mutex_lock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) if (gc4c33->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) ret = gc4c33_write_array(gc4c33->client, gc4c33_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) gc4c33->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) gc4c33->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) mutex_unlock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) static inline u32 gc4c33_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) return DIV_ROUND_UP(cycles, GC4C33_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) static int __gc4c33_power_on(struct gc4c33 *gc4c33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) struct device *dev = &gc4c33->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) if (!IS_ERR_OR_NULL(gc4c33->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) ret = pinctrl_select_state(gc4c33->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) gc4c33->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) ret = clk_set_rate(gc4c33->xvclk, GC4C33_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) if (clk_get_rate(gc4c33->xvclk) != GC4C33_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) ret = clk_prepare_enable(gc4c33->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (!IS_ERR(gc4c33->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) gpiod_set_value_cansleep(gc4c33->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (!IS_ERR(gc4c33->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) gpiod_set_value_cansleep(gc4c33->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) ret = regulator_bulk_enable(GC4C33_NUM_SUPPLIES, gc4c33->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) if (!IS_ERR(gc4c33->pwren_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) gpiod_set_value_cansleep(gc4c33->pwren_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) if (!IS_ERR(gc4c33->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) gpiod_set_value_cansleep(gc4c33->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) if (!IS_ERR(gc4c33->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) gpiod_set_value_cansleep(gc4c33->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) delay_us = gc4c33_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) clk_disable_unprepare(gc4c33->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) static void __gc4c33_power_off(struct gc4c33 *gc4c33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) struct device *dev = &gc4c33->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) if (!IS_ERR(gc4c33->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) gpiod_set_value_cansleep(gc4c33->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) clk_disable_unprepare(gc4c33->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (!IS_ERR(gc4c33->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) gpiod_set_value_cansleep(gc4c33->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (!IS_ERR_OR_NULL(gc4c33->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) ret = pinctrl_select_state(gc4c33->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) gc4c33->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) regulator_bulk_disable(GC4C33_NUM_SUPPLIES, gc4c33->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) if (!IS_ERR(gc4c33->pwren_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) gpiod_set_value_cansleep(gc4c33->pwren_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) static int gc4c33_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) struct gc4c33 *gc4c33 = to_gc4c33(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) return __gc4c33_power_on(gc4c33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) static int gc4c33_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) struct gc4c33 *gc4c33 = to_gc4c33(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) __gc4c33_power_off(gc4c33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) static int gc4c33_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) struct gc4c33 *gc4c33 = to_gc4c33(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) const struct gc4c33_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) mutex_lock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) mutex_unlock(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) static int gc4c33_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) struct gc4c33 *gc4c33 = to_gc4c33(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if (fie->index >= gc4c33->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) static const struct dev_pm_ops gc4c33_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) SET_RUNTIME_PM_OPS(gc4c33_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) gc4c33_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static const struct v4l2_subdev_internal_ops gc4c33_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .open = gc4c33_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) static const struct v4l2_subdev_core_ops gc4c33_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .s_power = gc4c33_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .ioctl = gc4c33_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .compat_ioctl32 = gc4c33_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) static const struct v4l2_subdev_video_ops gc4c33_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .s_stream = gc4c33_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .g_frame_interval = gc4c33_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) static const struct v4l2_subdev_pad_ops gc4c33_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .enum_mbus_code = gc4c33_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .enum_frame_size = gc4c33_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .enum_frame_interval = gc4c33_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .get_fmt = gc4c33_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .set_fmt = gc4c33_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .get_mbus_config = gc4c33_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) static const struct v4l2_subdev_ops gc4c33_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .core = &gc4c33_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .video = &gc4c33_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .pad = &gc4c33_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) static int gc4c33_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) struct gc4c33 *gc4c33 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) struct gc4c33, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) struct i2c_client *client = gc4c33->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) /*Propagate change of current control to all related controls*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) /*Update max exposure while meeting expected vblanking*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) max = gc4c33->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) __v4l2_ctrl_modify_range(gc4c33->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) gc4c33->exposure->minimum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) gc4c33->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) gc4c33->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) ret = gc4c33_write_reg(gc4c33->client, GC4C33_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) GC4C33_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) ctrl->val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) ret |= gc4c33_write_reg(gc4c33->client, GC4C33_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) GC4C33_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) ctrl->val & 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) if (gc4c33->cur_mode->height == 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) ret = gc4c33_set_gain_reg_720P(gc4c33, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) ret = gc4c33_set_gain_reg(gc4c33, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) ret = gc4c33_write_reg(gc4c33->client, GC4C33_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) GC4C33_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) (ctrl->val + gc4c33->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) ret |= gc4c33_write_reg(gc4c33->client, GC4C33_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) GC4C33_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) (ctrl->val + gc4c33->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) ret = gc4c33_read_reg(gc4c33->client, GC4C33_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) GC4C33_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) val |= GC4C33_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) val &= ~GC4C33_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) ret |= gc4c33_write_reg(gc4c33->client, GC4C33_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) GC4C33_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) gc4c33->flip = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) ret = gc4c33_read_reg(gc4c33->client, GC4C33_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) GC4C33_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) val |= GC4C33_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) val &= ~GC4C33_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) ret |= gc4c33_write_reg(gc4c33->client, GC4C33_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) GC4C33_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) gc4c33->flip = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) ret = gc4c33_enable_test_pattern(gc4c33, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) static const struct v4l2_ctrl_ops gc4c33_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .s_ctrl = gc4c33_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) static int gc4c33_initialize_controls(struct gc4c33 *gc4c33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) const struct gc4c33_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) handler = &gc4c33->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) mode = gc4c33->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) handler->lock = &gc4c33->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) 0, GC4C33_PIXEL_RATE, 1, GC4C33_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) gc4c33->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) if (gc4c33->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) gc4c33->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) gc4c33->vblank = v4l2_ctrl_new_std(handler, &gc4c33_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) GC4C33_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) gc4c33->exposure = v4l2_ctrl_new_std(handler, &gc4c33_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) V4L2_CID_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) GC4C33_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) exposure_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) GC4C33_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) gc4c33->anal_gain = v4l2_ctrl_new_std(handler, &gc4c33_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) V4L2_CID_ANALOGUE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) GC4C33_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) GC4C33_GAIN_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) GC4C33_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) GC4C33_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) gc4c33->test_pattern =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) &gc4c33_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) ARRAY_SIZE(gc4c33_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) 0, 0, gc4c33_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) gc4c33->h_flip = v4l2_ctrl_new_std(handler, &gc4c33_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) gc4c33->v_flip = v4l2_ctrl_new_std(handler, &gc4c33_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) gc4c33->flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) dev_err(&gc4c33->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) gc4c33->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) static int gc4c33_check_sensor_id(struct gc4c33 *gc4c33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) struct device *dev = &gc4c33->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) u16 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) u32 reg_H = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) u32 reg_L = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) ret = gc4c33_read_reg(client, GC4C33_REG_CHIP_ID_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) GC4C33_REG_VALUE_08BIT, ®_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) ret |= gc4c33_read_reg(client, GC4C33_REG_CHIP_ID_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) GC4C33_REG_VALUE_08BIT, ®_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) if (!(reg_H == (CHIP_ID >> 8) || reg_L == (CHIP_ID & 0xff))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) dev_info(dev, "detected gc%04x sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) static int gc4c33_configure_regulators(struct gc4c33 *gc4c33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) for (i = 0; i < GC4C33_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) gc4c33->supplies[i].supply = gc4c33_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) return devm_regulator_bulk_get(&gc4c33->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) GC4C33_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) gc4c33->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) static int gc4c33_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) struct gc4c33 *gc4c33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) gc4c33 = devm_kzalloc(dev, sizeof(*gc4c33), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) if (!gc4c33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) &gc4c33->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) &gc4c33->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) &gc4c33->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) &gc4c33->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) gc4c33->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) gc4c33->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) for (i = 0; i < gc4c33->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) gc4c33->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) if (i == gc4c33->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) gc4c33->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) gc4c33->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) if (IS_ERR(gc4c33->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) gc4c33->pwren_gpio = devm_gpiod_get(dev, "pwren", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) if (IS_ERR(gc4c33->pwren_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) dev_warn(dev, "Failed to get pwren-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) gc4c33->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) if (IS_ERR(gc4c33->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) gc4c33->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) if (IS_ERR(gc4c33->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) gc4c33->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) if (!IS_ERR(gc4c33->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) gc4c33->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) pinctrl_lookup_state(gc4c33->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) if (IS_ERR(gc4c33->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) gc4c33->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) pinctrl_lookup_state(gc4c33->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) if (IS_ERR(gc4c33->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) ret = gc4c33_configure_regulators(gc4c33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) mutex_init(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) sd = &gc4c33->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) v4l2_i2c_subdev_init(sd, client, &gc4c33_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) ret = gc4c33_initialize_controls(gc4c33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) ret = __gc4c33_power_on(gc4c33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) ret = gc4c33_check_sensor_id(gc4c33, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) sd->internal_ops = &gc4c33_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) gc4c33->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) ret = media_entity_pads_init(&sd->entity, 1, &gc4c33->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) if (strcmp(gc4c33->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) gc4c33->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) GC4C33_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) __gc4c33_power_off(gc4c33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) v4l2_ctrl_handler_free(&gc4c33->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) mutex_destroy(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) static int gc4c33_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) struct gc4c33 *gc4c33 = to_gc4c33(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) v4l2_ctrl_handler_free(&gc4c33->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) mutex_destroy(&gc4c33->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) __gc4c33_power_off(gc4c33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) static const struct of_device_id gc4c33_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) { .compatible = "galaxycore,gc4c33" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) MODULE_DEVICE_TABLE(of, gc4c33_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) static const struct i2c_device_id gc4c33_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) { "galaxycore,gc4c33", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) static struct i2c_driver gc4c33_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .name = GC4C33_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .pm = &gc4c33_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .of_match_table = of_match_ptr(gc4c33_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .probe = &gc4c33_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .remove = &gc4c33_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .id_table = gc4c33_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) return i2c_add_driver(&gc4c33_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) i2c_del_driver(&gc4c33_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) MODULE_DESCRIPTION("galaxycore gc4c33 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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