^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GC4653 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 fix gain range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X05 support enum sensor fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * V0.0X01.0X06 support mirror and flip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * V0.0X01.0X07 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GC4653_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GC4653_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GC4653_LINK_FREQ_LINEAR 324000000 //2560*1440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GC4653_PIXEL_RATE_LINEAR (GC4653_LINK_FREQ_LINEAR * 2 / 10 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GC4653_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CHIP_ID 0x4653
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GC4653_REG_CHIP_ID_H 0x03f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GC4653_REG_CHIP_ID_L 0x03f1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GC4653_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GC4653_MODE_SW_STANDBY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GC4653_MODE_STREAMING 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GC4653_REG_EXPOSURE_H 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GC4653_REG_EXPOSURE_L 0x0203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GC4653_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GC4653_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GC4653_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GC4653_GAIN_MIN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GC4653_GAIN_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GC4653_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GC4653_GAIN_DEFAULT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GC4653_REG_TEST_PATTERN 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GC4653_TEST_PATTERN_ENABLE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GC4653_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GC4653_REG_VTS_H 0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GC4653_REG_VTS_L 0x0341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GC4653_FLIP_MIRROR_REG 0x0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GC4653_MIRROR_BIT_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GC4653_FLIP_BIT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GC4653_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GC4653_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GC4653_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GC4653_NAME "gc4653"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const char * const gc4653_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GC4653_NUM_SUPPLIES ARRAY_SIZE(gc4653_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct gc4653_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct gc4653 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct gpio_desc *pwren_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct regulator_bulk_data supplies[GC4653_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_ctrl *h_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_ctrl *v_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const struct gc4653_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 cur_pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 cur_link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define to_gc4653(sd) container_of(sd, struct gc4653, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const struct regval gc4653_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const u32 reg_val_table_liner[21][7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) //2b3 2b4 2b8 2b9 515 519 2d9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x00, 0x00, 0x01, 0x00, 0x30, 0x1e, 0x5C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x20, 0x00, 0x01, 0x0B, 0x30, 0x1e, 0x5C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x01, 0x00, 0x01, 0x19, 0x30, 0x1d, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x21, 0x00, 0x01, 0x2A, 0x30, 0x1e, 0x5C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x02, 0x00, 0x02, 0x00, 0x30, 0x1e, 0x5C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x22, 0x00, 0x02, 0x17, 0x30, 0x1d, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x03, 0x00, 0x02, 0x33, 0x20, 0x16, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x23, 0x00, 0x03, 0x14, 0x20, 0x17, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x04, 0x00, 0x04, 0x00, 0x20, 0x17, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x24, 0x00, 0x04, 0x2F, 0x20, 0x19, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x05, 0x00, 0x05, 0x26, 0x20, 0x19, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x25, 0x00, 0x06, 0x28, 0x20, 0x1b, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x0c, 0x00, 0x08, 0x00, 0x20, 0x1d, 0x5B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x2C, 0x00, 0x09, 0x1E, 0x20, 0x1f, 0x5D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x0D, 0x00, 0x0B, 0x0C, 0x20, 0x21, 0x5F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x2D, 0x00, 0x0D, 0x11, 0x20, 0x24, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x1C, 0x00, 0x10, 0x00, 0x20, 0x26, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3C, 0x00, 0x12, 0x3D, 0x18, 0x2a, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x5C, 0x00, 0x16, 0x19, 0x18, 0x2c, 0x6A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x7C, 0x00, 0x1A, 0x22, 0x18, 0x2e, 0x6C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x9C, 0x00, 0x20, 0x00, 0x18, 0x32, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const u32 gain_level_table[22] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 151,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 179,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 212,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 303,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 358,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 424,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 606,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 716,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 849,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 1213,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 1433,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 1698,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * mipi_datarate per lane 648Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct regval gc4653_linear10bit_2560x1440_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x03fe, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x0317, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x0320, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x0324, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x0325, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x0326, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x0327, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x0334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x0336, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x0337, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x0315, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x031c, 0xc6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x0287, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x0084, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x0087, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x029d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x0290, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x0340, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x0341, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x0345, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x034b, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x0352, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x0354, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x02d1, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x0223, 0xf2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x0238, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x02ce, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x0232, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x02d3, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x0243, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x02ee, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x026f, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x0257, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x0211, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x0219, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x023f, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x0518, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x0519, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x0515, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x02d9, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x02da, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x02db, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x02e6, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x021b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x0252, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x024e, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x02c4, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x021d, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x024a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x02ca, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x0262, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x029a, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x021c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x0298, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x029c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x027e, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x02c2, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x0540, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x0546, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x0548, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x0544, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x0242, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x02c0, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x02c3, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x02e4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x022e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x027b, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x0269, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x02d2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x027c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x023a, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x0245, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x0530, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x0531, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x0228, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x02ab, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x0250, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x0221, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x02ac, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x02a5, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x0260, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x0216, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x0299, 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x02bb, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x02a3, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x02a4, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x021e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x024f, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x028c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x0532, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x0533, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x0277, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x0276, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x0239, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x0202, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x0203, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x0205, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x02b0, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x0002, 0xa9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x0004, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x021a, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x0266, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x0020, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x0021, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x0022, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x0023, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x0342, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x0343, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x03fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x0106, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x0108, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x0114, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x0115, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x0180, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x0181, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x0182, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x0185, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x03fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x000f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const struct regval gc4653_otp_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x0080, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x0097, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x0098, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x0099, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x009a, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x0317, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x0a67, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x0a70, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x0a82, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x0a83, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x0a80, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x05be, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x05a9, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x0313, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x05be, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x0317, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x0a67, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const struct gc4653_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .width = 2560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .height = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .exp_def = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .hts_def = 0x12C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .vts_def = 0x05DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .bus_fmt = MEDIA_BUS_FMT_SGRBG10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .reg_list = gc4653_linear10bit_2560x1440_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) GC4653_LINK_FREQ_LINEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const char * const gc4653_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int gc4653_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int gc4653_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = gc4653_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) GC4653_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int gc4653_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int gc4653_get_reso_dist(const struct gc4653_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const struct gc4653_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) gc4653_find_best_fit(struct gc4653 *gc4653, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) for (i = 0; i < gc4653->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dist = gc4653_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int gc4653_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct gc4653 *gc4653 = to_gc4653(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) const struct gc4653_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) mutex_lock(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) mode = gc4653_find_best_fit(gc4653, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) mutex_unlock(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) gc4653->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) __v4l2_ctrl_modify_range(gc4653->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) __v4l2_ctrl_modify_range(gc4653->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) GC4653_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) gc4653->cur_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) gc4653->cur_pixel_rate = GC4653_PIXEL_RATE_LINEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) __v4l2_ctrl_s_ctrl_int64(gc4653->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) gc4653->cur_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) __v4l2_ctrl_s_ctrl(gc4653->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) gc4653->cur_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) gc4653->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mutex_unlock(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int gc4653_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct gc4653 *gc4653 = to_gc4653(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) const struct gc4653_mode *mode = gc4653->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mutex_lock(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mutex_unlock(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mutex_unlock(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int gc4653_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct gc4653 *gc4653 = to_gc4653(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) code->code = gc4653->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int gc4653_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct gc4653 *gc4653 = to_gc4653(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (fse->index >= gc4653->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int gc4653_enable_test_pattern(struct gc4653 *gc4653, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) val = GC4653_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) val = GC4653_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return gc4653_write_reg(gc4653->client, GC4653_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) GC4653_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int gc4653_set_gain_reg(struct gc4653 *gc4653, u32 gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u32 tol_dig_gain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (gain < 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) gain = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) total = sizeof(gain_level_table) / sizeof(u32) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) for (i = 0; i < total; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (gain_level_table[i] <= gain &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) gain < gain_level_table[i + 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) tol_dig_gain = gain * 64 / gain_level_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (i >= total)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) i = total - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) gc4653_write_reg(gc4653->client, 0x2b3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) GC4653_REG_VALUE_08BIT, reg_val_table_liner[i][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) gc4653_write_reg(gc4653->client, 0x2b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) GC4653_REG_VALUE_08BIT, reg_val_table_liner[i][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) gc4653_write_reg(gc4653->client, 0x2b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GC4653_REG_VALUE_08BIT, reg_val_table_liner[i][2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) gc4653_write_reg(gc4653->client, 0x2b9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) GC4653_REG_VALUE_08BIT, reg_val_table_liner[i][3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) gc4653_write_reg(gc4653->client, 0x515,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) GC4653_REG_VALUE_08BIT, reg_val_table_liner[i][4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) gc4653_write_reg(gc4653->client, 0x519,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) GC4653_REG_VALUE_08BIT, reg_val_table_liner[i][5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) gc4653_write_reg(gc4653->client, 0x2d9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) GC4653_REG_VALUE_08BIT, reg_val_table_liner[i][6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) gc4653_write_reg(gc4653->client, 0x20e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) GC4653_REG_VALUE_08BIT, (tol_dig_gain >> 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) gc4653_write_reg(gc4653->client, 0x20f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) GC4653_REG_VALUE_08BIT, ((tol_dig_gain & 0x3f) << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static int gc4653_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct gc4653 *gc4653 = to_gc4653(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) const struct gc4653_mode *mode = gc4653->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) mutex_lock(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) mutex_unlock(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static int gc4653_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct gc4653 *gc4653 = to_gc4653(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) const struct gc4653_mode *mode = gc4653->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) val = 1 << (GC4653_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static void gc4653_get_module_inf(struct gc4653 *gc4653,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) strscpy(inf->base.sensor, GC4653_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) strscpy(inf->base.module, gc4653->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) strscpy(inf->base.lens, gc4653->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int gc4653_get_channel_info(struct gc4653 *gc4653, struct rkmodule_channel_info *ch_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ch_info->vc = gc4653->cur_mode->vc[ch_info->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ch_info->width = gc4653->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ch_info->height = gc4653->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ch_info->bus_fmt = gc4653->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static long gc4653_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct gc4653 *gc4653 = to_gc4653(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) gc4653_get_module_inf(gc4653, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) hdr->hdr_mode = gc4653->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) w = gc4653->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) h = gc4653->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) for (i = 0; i < gc4653->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) gc4653->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (i == gc4653->cfg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dev_err(&gc4653->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) w = gc4653->cur_mode->hts_def -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) gc4653->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) h = gc4653->cur_mode->vts_def -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) gc4653->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) __v4l2_ctrl_modify_range(gc4653->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) __v4l2_ctrl_modify_range(gc4653->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) GC4653_VTS_MAX -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) gc4653->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) gc4653->cur_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) gc4653->cur_pixel_rate = GC4653_PIXEL_RATE_LINEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) __v4l2_ctrl_s_ctrl_int64(gc4653->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) gc4653->cur_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) __v4l2_ctrl_s_ctrl(gc4653->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) gc4653->cur_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) gc4653->cur_vts = gc4653->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = gc4653_write_reg(gc4653->client, GC4653_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) GC4653_REG_VALUE_08BIT, GC4653_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ret = gc4653_write_reg(gc4653->client, GC4653_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) GC4653_REG_VALUE_08BIT, GC4653_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ch_info = (struct rkmodule_channel_info *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ret = gc4653_get_channel_info(gc4653, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static long gc4653_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = gc4653_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ret = gc4653_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ret = gc4653_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ret = gc4653_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ret = gc4653_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ret = gc4653_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (!ch_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ret = gc4653_ioctl(sd, cmd, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ret = copy_to_user(up, ch_info, sizeof(*ch_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) kfree(ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int __gc4653_start_stream(struct gc4653 *gc4653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ret = gc4653_write_array(gc4653->client, gc4653->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ret = __v4l2_ctrl_handler_setup(&gc4653->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (gc4653->has_init_exp && gc4653->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ret = gc4653_ioctl(&gc4653->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) &gc4653->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) dev_err(&gc4653->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret |= gc4653_write_reg(gc4653->client, GC4653_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) GC4653_REG_VALUE_08BIT, GC4653_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (gc4653->cur_mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ret |= gc4653_write_array(gc4653->client, gc4653_otp_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static int __gc4653_stop_stream(struct gc4653 *gc4653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) gc4653->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return gc4653_write_reg(gc4653->client, GC4653_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) GC4653_REG_VALUE_08BIT, GC4653_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static int gc4653_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct gc4653 *gc4653 = to_gc4653(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct i2c_client *client = gc4653->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) mutex_lock(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (on == gc4653->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ret = __gc4653_start_stream(gc4653);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) __gc4653_stop_stream(gc4653);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) gc4653->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) mutex_unlock(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static int gc4653_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct gc4653 *gc4653 = to_gc4653(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct i2c_client *client = gc4653->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) mutex_lock(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (gc4653->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ret = gc4653_write_array(gc4653->client, gc4653_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) gc4653->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) gc4653->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) mutex_unlock(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static inline u32 gc4653_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return DIV_ROUND_UP(cycles, GC4653_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static int __gc4653_power_on(struct gc4653 *gc4653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct device *dev = &gc4653->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (!IS_ERR_OR_NULL(gc4653->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = pinctrl_select_state(gc4653->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) gc4653->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ret = clk_set_rate(gc4653->xvclk, GC4653_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (clk_get_rate(gc4653->xvclk) != GC4653_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret = clk_prepare_enable(gc4653->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (!IS_ERR(gc4653->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) gpiod_set_value_cansleep(gc4653->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (!IS_ERR(gc4653->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) gpiod_set_value_cansleep(gc4653->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ret = regulator_bulk_enable(GC4653_NUM_SUPPLIES, gc4653->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (!IS_ERR(gc4653->pwren_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) gpiod_set_value_cansleep(gc4653->pwren_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (!IS_ERR(gc4653->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) gpiod_set_value_cansleep(gc4653->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (!IS_ERR(gc4653->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) gpiod_set_value_cansleep(gc4653->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) delay_us = gc4653_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) clk_disable_unprepare(gc4653->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static void __gc4653_power_off(struct gc4653 *gc4653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct device *dev = &gc4653->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (!IS_ERR(gc4653->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) gpiod_set_value_cansleep(gc4653->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) clk_disable_unprepare(gc4653->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (!IS_ERR(gc4653->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) gpiod_set_value_cansleep(gc4653->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (!IS_ERR_OR_NULL(gc4653->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ret = pinctrl_select_state(gc4653->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) gc4653->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) regulator_bulk_disable(GC4653_NUM_SUPPLIES, gc4653->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (!IS_ERR(gc4653->pwren_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) gpiod_set_value_cansleep(gc4653->pwren_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static int gc4653_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct gc4653 *gc4653 = to_gc4653(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return __gc4653_power_on(gc4653);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static int gc4653_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct gc4653 *gc4653 = to_gc4653(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) __gc4653_power_off(gc4653);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static int gc4653_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct gc4653 *gc4653 = to_gc4653(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) const struct gc4653_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) mutex_lock(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) mutex_unlock(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static int gc4653_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct gc4653 *gc4653 = to_gc4653(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (fie->index >= gc4653->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static const struct dev_pm_ops gc4653_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) SET_RUNTIME_PM_OPS(gc4653_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) gc4653_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static const struct v4l2_subdev_internal_ops gc4653_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .open = gc4653_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static const struct v4l2_subdev_core_ops gc4653_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .s_power = gc4653_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .ioctl = gc4653_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .compat_ioctl32 = gc4653_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static const struct v4l2_subdev_video_ops gc4653_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .s_stream = gc4653_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .g_frame_interval = gc4653_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static const struct v4l2_subdev_pad_ops gc4653_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .enum_mbus_code = gc4653_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .enum_frame_size = gc4653_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .enum_frame_interval = gc4653_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .get_fmt = gc4653_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .set_fmt = gc4653_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .get_mbus_config = gc4653_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static const struct v4l2_subdev_ops gc4653_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .core = &gc4653_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .video = &gc4653_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .pad = &gc4653_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static int gc4653_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct gc4653 *gc4653 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct gc4653, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct i2c_client *client = gc4653->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /*Propagate change of current control to all related controls*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /*Update max exposure while meeting expected vblanking*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) max = gc4653->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) __v4l2_ctrl_modify_range(gc4653->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) gc4653->exposure->minimum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) gc4653->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) gc4653->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ret = gc4653_write_reg(gc4653->client, GC4653_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) GC4653_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) ctrl->val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) ret |= gc4653_write_reg(gc4653->client, GC4653_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) GC4653_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ctrl->val & 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ret = gc4653_set_gain_reg(gc4653, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) gc4653->cur_vts = ctrl->val + gc4653->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ret = gc4653_write_reg(gc4653->client, GC4653_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) GC4653_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) gc4653->cur_vts >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ret |= gc4653_write_reg(gc4653->client, GC4653_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) GC4653_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) gc4653->cur_vts & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ret = gc4653_enable_test_pattern(gc4653, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ret = gc4653_read_reg(gc4653->client, GC4653_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) GC4653_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) val |= GC4653_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) val &= ~GC4653_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ret |= gc4653_write_reg(gc4653->client, GC4653_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) GC4653_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ret = gc4653_read_reg(gc4653->client, GC4653_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) GC4653_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) val |= GC4653_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) val &= ~GC4653_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) ret |= gc4653_write_reg(gc4653->client, GC4653_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) GC4653_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static const struct v4l2_ctrl_ops gc4653_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .s_ctrl = gc4653_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static int gc4653_initialize_controls(struct gc4653 *gc4653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) const struct gc4653_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) handler = &gc4653->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) mode = gc4653->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) handler->lock = &gc4653->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) gc4653->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) gc4653->cur_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) gc4653->cur_pixel_rate = GC4653_PIXEL_RATE_LINEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) __v4l2_ctrl_s_ctrl(gc4653->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) gc4653->cur_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) gc4653->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) 0, GC4653_PIXEL_RATE_LINEAR, 1, GC4653_PIXEL_RATE_LINEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) gc4653->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (gc4653->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) gc4653->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) gc4653->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) gc4653->vblank = v4l2_ctrl_new_std(handler, &gc4653_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) GC4653_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) gc4653->exposure = v4l2_ctrl_new_std(handler, &gc4653_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) V4L2_CID_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) GC4653_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) exposure_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) GC4653_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) gc4653->anal_gain = v4l2_ctrl_new_std(handler, &gc4653_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) V4L2_CID_ANALOGUE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) GC4653_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) GC4653_GAIN_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) GC4653_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) GC4653_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) gc4653->test_pattern =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) &gc4653_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ARRAY_SIZE(gc4653_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) 0, 0, gc4653_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) gc4653->h_flip = v4l2_ctrl_new_std(handler, &gc4653_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) gc4653->v_flip = v4l2_ctrl_new_std(handler, &gc4653_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) dev_err(&gc4653->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) gc4653->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) gc4653->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static int gc4653_check_sensor_id(struct gc4653 *gc4653,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) struct device *dev = &gc4653->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) u16 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) u32 reg_H = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) u32 reg_L = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ret = gc4653_read_reg(client, GC4653_REG_CHIP_ID_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) GC4653_REG_VALUE_08BIT, ®_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ret |= gc4653_read_reg(client, GC4653_REG_CHIP_ID_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) GC4653_REG_VALUE_08BIT, ®_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (!(reg_H == (CHIP_ID >> 8) || reg_L == (CHIP_ID & 0xff))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) dev_info(dev, "detected gc%04x sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static int gc4653_configure_regulators(struct gc4653 *gc4653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) for (i = 0; i < GC4653_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) gc4653->supplies[i].supply = gc4653_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return devm_regulator_bulk_get(&gc4653->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) GC4653_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) gc4653->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static int gc4653_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) struct gc4653 *gc4653;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) gc4653 = devm_kzalloc(dev, sizeof(*gc4653), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (!gc4653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) &gc4653->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) &gc4653->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) &gc4653->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) &gc4653->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) gc4653->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) gc4653->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) for (i = 0; i < gc4653->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) gc4653->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (i == gc4653->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) gc4653->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) gc4653->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (IS_ERR(gc4653->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) gc4653->pwren_gpio = devm_gpiod_get(dev, "pwren", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (IS_ERR(gc4653->pwren_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) dev_warn(dev, "Failed to get pwren-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) gc4653->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (IS_ERR(gc4653->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) gc4653->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (IS_ERR(gc4653->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) gc4653->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (!IS_ERR(gc4653->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) gc4653->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) pinctrl_lookup_state(gc4653->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (IS_ERR(gc4653->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) gc4653->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) pinctrl_lookup_state(gc4653->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (IS_ERR(gc4653->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) ret = gc4653_configure_regulators(gc4653);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) mutex_init(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) sd = &gc4653->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) v4l2_i2c_subdev_init(sd, client, &gc4653_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) ret = gc4653_initialize_controls(gc4653);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ret = __gc4653_power_on(gc4653);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) usleep_range(3000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) ret = gc4653_check_sensor_id(gc4653, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) sd->internal_ops = &gc4653_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) gc4653->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) ret = media_entity_pads_init(&sd->entity, 1, &gc4653->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (strcmp(gc4653->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) gc4653->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) GC4653_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) __gc4653_power_off(gc4653);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) v4l2_ctrl_handler_free(&gc4653->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) mutex_destroy(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static int gc4653_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) struct gc4653 *gc4653 = to_gc4653(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) v4l2_ctrl_handler_free(&gc4653->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) mutex_destroy(&gc4653->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) __gc4653_power_off(gc4653);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static const struct of_device_id gc4653_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) { .compatible = "galaxycore,gc4653" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) MODULE_DEVICE_TABLE(of, gc4653_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static const struct i2c_device_id gc4653_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) { "galaxycore,gc4653", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static struct i2c_driver gc4653_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .name = GC4653_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .pm = &gc4653_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .of_match_table = of_match_ptr(gc4653_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .probe = &gc4653_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .remove = &gc4653_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .id_table = gc4653_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return i2c_add_driver(&gc4653_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) i2c_del_driver(&gc4653_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) MODULE_DESCRIPTION("galaxycore gc4653 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags