^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GC4023 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 init version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X02.0X00 update version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 1, update init registers setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2, update gain table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 3, update mirror/flip setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRIVER_VERSION KERNEL_VERSION(0, 0x02, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GC4023_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GC4023_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GC4023_LINK_FREQ_LINEAR 351000000 //2560*1440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GC4023_PIXEL_RATE_LINEAR (GC4023_LINK_FREQ_LINEAR * 2 / 10 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GC4023_XVCLK_FREQ 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CHIP_ID 0x4023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GC4023_REG_CHIP_ID_H 0x03f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GC4023_REG_CHIP_ID_L 0x03f1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GC4023_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GC4023_MODE_SW_STANDBY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GC4023_MODE_STREAMING 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GC4023_REG_EXPOSURE_H 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GC4023_REG_EXPOSURE_L 0x0203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GC4023_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GC4023_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GC4023_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GC4023_GAIN_MIN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GC4023_GAIN_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GC4023_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GC4023_GAIN_DEFAULT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GC4023_REG_TEST_PATTERN 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GC4023_TEST_PATTERN_ENABLE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GC4023_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GC4023_REG_VTS_H 0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GC4023_REG_VTS_L 0x0341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GC4023_OTP_MIRROR_FLIP_REG 0x0a73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GC4023_MIRROR_BIT_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GC4023_MIRROR_FLIP_REG 0x022c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GC4023_FLIP_BIT_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GC4023_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GC4023_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GC4023_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GC4023_NAME "gc4023"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const char * const gc4023_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GC4023_NUM_SUPPLIES ARRAY_SIZE(gc4023_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct gc4023_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct gc4023 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct gpio_desc *pwren_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct regulator_bulk_data supplies[GC4023_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_ctrl *h_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_ctrl *v_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct gc4023_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 cur_pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 cur_link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define to_gc4023(sd) container_of(sd, struct gc4023, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct regval gc4023_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const u32 reg_val_table_liner[26][7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) // 614 615 218 1467 1468 b8 b9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x00, 0x00, 0x00, 0x0D, 0x15, 0x01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x80, 0x02, 0x00, 0x0D, 0x15, 0x01, 0x0B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x01, 0x00, 0x00, 0x0D, 0x15, 0x01, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x81, 0x02, 0x00, 0x0E, 0x16, 0x01, 0x2A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x02, 0x00, 0x00, 0x0E, 0x16, 0x02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x82, 0x02, 0x00, 0x0F, 0x17, 0x02, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x03, 0x00, 0x00, 0x10, 0x18, 0x02, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x83, 0x02, 0x00, 0x11, 0x19, 0x03, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x04, 0x00, 0x00, 0x12, 0x1a, 0x04, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x80, 0x02, 0x20, 0x13, 0x1b, 0x04, 0x2F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x01, 0x00, 0x20, 0x14, 0x1c, 0x05, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x81, 0x02, 0x20, 0x15, 0x1d, 0x06, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x02, 0x00, 0x20, 0x16, 0x1e, 0x08, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x82, 0x02, 0x20, 0x16, 0x1e, 0x09, 0x1E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x03, 0x00, 0x20, 0x18, 0x20, 0x0B, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x83, 0x02, 0x20, 0x18, 0x20, 0x0D, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x04, 0x00, 0x20, 0x18, 0x20, 0x10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x84, 0x02, 0x20, 0x19, 0x21, 0x12, 0x3D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x05, 0x00, 0x20, 0x19, 0x21, 0x16, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x85, 0x02, 0x20, 0x1A, 0x22, 0x1A, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0xb5, 0x04, 0x20, 0x1B, 0x23, 0x20, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x85, 0x05, 0x20, 0x1B, 0x23, 0x25, 0x3A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x05, 0x08, 0x20, 0x1C, 0x24, 0x2C, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x45, 0x09, 0x20, 0x1D, 0x25, 0x35, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x55, 0x0a, 0x20, 0x1F, 0x27, 0x40, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const u32 gain_level_table[26] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 152,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 179,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 212,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 303,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 358,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 425,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 607,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 717,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 849,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 1213,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 1434,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 1699,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 2427,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 2867,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 3398,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * mipi_datarate per lane 864Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct regval gc4023_linear10bit_2560x1440_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x03fe, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x03fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x03fe, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x0a38, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x0a38, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x0a20, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x061c, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x061d, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x061e, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x061f, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x0a21, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x0a34, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x0a35, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x0a36, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x0a37, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x0314, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x0315, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x031c, 0xce},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x0219, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x0342, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x0343, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x0259, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x025a, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x0340, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x0341, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x0347, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x0348, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x0349, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x034a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x034b, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x0094, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x0095, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x0096, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x0097, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x0099, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x009b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x060c, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x060e, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x060f, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x070c, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x070e, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x070f, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x0909, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x0902, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x0904, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x0907, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x0908, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x0903, 0x9d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x072a, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x0724, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x0727, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x072a, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x072b, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x1466, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x1468, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x1467, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x1469, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x146a, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x0707, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x0737, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x0704, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x0706, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x0716, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x0708, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x0718, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x061a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x1430, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x1407, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x1408, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x1409, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x146d, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x146e, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x146f, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x1470, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x1471, 0x3d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x1472, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x1473, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x1474, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x1475, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x1420, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x1464, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x146c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x146d, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x1423, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x1428, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x1462, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x02ce, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x143a, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x142b, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x0245, 0xc9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x023a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x02cd, 0x99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x0612, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x0613, 0xc7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x0243, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x021b, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x0089, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x0040, 0xa3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x0075, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x0004, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x0002, 0xab},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x0053, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x0205, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x0202, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x0203, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x0614, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x0615, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x0181, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x0182, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x0185, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x0180, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x0100, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x0106, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x010d, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x010e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x0113, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x0114, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x0115, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x022c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) //{0x0100, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x0a67, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x0a54, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x0a65, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x0a98, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x05be, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x05a9, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x0029, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x002b, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x0a83, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x0a72, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x0a73, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x0a75, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x0a70, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x0a5a, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {REG_DELAY, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x05be, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x0a70, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x0080, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x0a67, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const struct gc4023_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .width = 2560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .height = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .exp_def = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .hts_def = 0x0AA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .vts_def = 0x05DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .bus_fmt = MEDIA_BUS_FMT_SRGGB10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .reg_list = gc4023_linear10bit_2560x1440_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) GC4023_LINK_FREQ_LINEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const char * const gc4023_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int gc4023_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int gc4023_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (regs[i].addr == REG_DELAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) usleep_range(regs[i].val * 1000, regs[i].val * 2 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = gc4023_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) GC4023_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int gc4023_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int gc4023_get_reso_dist(const struct gc4023_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const struct gc4023_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) gc4023_find_best_fit(struct gc4023 *gc4023, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) for (i = 0; i < gc4023->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dist = gc4023_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int gc4023_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) const struct gc4023_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mutex_lock(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) mode = gc4023_find_best_fit(gc4023, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) mutex_unlock(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) gc4023->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) __v4l2_ctrl_modify_range(gc4023->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) __v4l2_ctrl_modify_range(gc4023->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) GC4023_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) gc4023->cur_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) gc4023->cur_pixel_rate = GC4023_PIXEL_RATE_LINEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) __v4l2_ctrl_s_ctrl_int64(gc4023->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) gc4023->cur_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) __v4l2_ctrl_s_ctrl(gc4023->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) gc4023->cur_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) gc4023->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mutex_unlock(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int gc4023_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) const struct gc4023_mode *mode = gc4023->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mutex_lock(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mutex_unlock(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) mutex_unlock(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int gc4023_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) code->code = gc4023->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int gc4023_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (fse->index >= gc4023->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int gc4023_enable_test_pattern(struct gc4023 *gc4023, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) val = GC4023_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) val = GC4023_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return gc4023_write_reg(gc4023->client, GC4023_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) GC4023_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static int gc4023_set_gain_reg(struct gc4023 *gc4023, u32 gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u32 tol_dig_gain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (gain < 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) gain = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) total = ARRAY_SIZE(gain_level_table) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) for (i = 0; i < total; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (gain_level_table[i] <= gain &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) gain < gain_level_table[i + 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) tol_dig_gain = gain * 64 / gain_level_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) gc4023_write_reg(gc4023->client, 0x614,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) GC4023_REG_VALUE_08BIT, reg_val_table_liner[i][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) gc4023_write_reg(gc4023->client, 0x615,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) GC4023_REG_VALUE_08BIT, reg_val_table_liner[i][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) gc4023_write_reg(gc4023->client, 0x218,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) GC4023_REG_VALUE_08BIT, reg_val_table_liner[i][2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) gc4023_write_reg(gc4023->client, 0x1467,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) GC4023_REG_VALUE_08BIT, reg_val_table_liner[i][3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) gc4023_write_reg(gc4023->client, 0x1468,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) GC4023_REG_VALUE_08BIT, reg_val_table_liner[i][4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) gc4023_write_reg(gc4023->client, 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) GC4023_REG_VALUE_08BIT, reg_val_table_liner[i][5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) gc4023_write_reg(gc4023->client, 0xb9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) GC4023_REG_VALUE_08BIT, reg_val_table_liner[i][6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) gc4023_write_reg(gc4023->client, 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) GC4023_REG_VALUE_08BIT, (tol_dig_gain >> 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) gc4023_write_reg(gc4023->client, 0x65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) GC4023_REG_VALUE_08BIT, ((tol_dig_gain & 0x3f) << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int gc4023_set_mirror_flip(struct gc4023 *gc4023, u8 val, u8 otp_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = gc4023_write_reg(gc4023->client, 0x022c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) GC4023_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ret |= gc4023_write_reg(gc4023->client, 0x0a67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) GC4023_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ret |= gc4023_write_reg(gc4023->client, 0x0a54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) GC4023_REG_VALUE_08BIT, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret |= gc4023_write_reg(gc4023->client, 0x0a65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) GC4023_REG_VALUE_08BIT, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ret |= gc4023_write_reg(gc4023->client, 0x0a98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) GC4023_REG_VALUE_08BIT, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ret |= gc4023_write_reg(gc4023->client, 0x05be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) GC4023_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ret |= gc4023_write_reg(gc4023->client, 0x05a9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) GC4023_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret |= gc4023_write_reg(gc4023->client, 0x0029,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) GC4023_REG_VALUE_08BIT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ret |= gc4023_write_reg(gc4023->client, 0x002b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) GC4023_REG_VALUE_08BIT, 0xa8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ret |= gc4023_write_reg(gc4023->client, 0x0a83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) GC4023_REG_VALUE_08BIT, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret |= gc4023_write_reg(gc4023->client, 0x0a72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) GC4023_REG_VALUE_08BIT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret |= gc4023_write_reg(gc4023->client, 0x0a73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) GC4023_REG_VALUE_08BIT, otp_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret |= gc4023_write_reg(gc4023->client, 0x0a75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) GC4023_REG_VALUE_08BIT, 0x41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ret |= gc4023_write_reg(gc4023->client, 0x0a70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) GC4023_REG_VALUE_08BIT, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret |= gc4023_write_reg(gc4023->client, 0x0a5a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) GC4023_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) usleep_range(20 * 1000, 30 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ret |= gc4023_write_reg(gc4023->client, 0x05be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) GC4023_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ret |= gc4023_write_reg(gc4023->client, 0x0a70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) GC4023_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ret |= gc4023_write_reg(gc4023->client, 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) GC4023_REG_VALUE_08BIT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ret |= gc4023_write_reg(gc4023->client, 0x0a67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) GC4023_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int gc4023_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) const struct gc4023_mode *mode = gc4023->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) mutex_lock(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) mutex_unlock(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static int gc4023_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) const struct gc4023_mode *mode = gc4023->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) val = 1 << (GC4023_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) val = 1 << (GC4023_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static void gc4023_get_module_inf(struct gc4023 *gc4023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) strscpy(inf->base.sensor, GC4023_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) strscpy(inf->base.module, gc4023->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) strscpy(inf->base.lens, gc4023->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static int gc4023_get_channel_info(struct gc4023 *gc4023, struct rkmodule_channel_info *ch_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ch_info->vc = gc4023->cur_mode->vc[ch_info->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ch_info->width = gc4023->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ch_info->height = gc4023->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ch_info->bus_fmt = gc4023->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static long gc4023_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) gc4023_get_module_inf(gc4023, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) hdr->hdr_mode = gc4023->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) w = gc4023->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) h = gc4023->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) for (i = 0; i < gc4023->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) gc4023->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (i == gc4023->cfg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_err(&gc4023->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) w = gc4023->cur_mode->hts_def -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) gc4023->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) h = gc4023->cur_mode->vts_def -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) gc4023->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) __v4l2_ctrl_modify_range(gc4023->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) __v4l2_ctrl_modify_range(gc4023->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) GC4023_VTS_MAX -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) gc4023->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) gc4023->cur_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) gc4023->cur_pixel_rate = GC4023_PIXEL_RATE_LINEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) __v4l2_ctrl_s_ctrl_int64(gc4023->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) gc4023->cur_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) __v4l2_ctrl_s_ctrl(gc4023->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) gc4023->cur_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) gc4023->cur_vts = gc4023->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = gc4023_write_reg(gc4023->client, GC4023_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) GC4023_REG_VALUE_08BIT, GC4023_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ret = gc4023_write_reg(gc4023->client, GC4023_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) GC4023_REG_VALUE_08BIT, GC4023_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ch_info = (struct rkmodule_channel_info *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ret = gc4023_get_channel_info(gc4023, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static long gc4023_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ret = gc4023_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ret = gc4023_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ret = gc4023_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ret = gc4023_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (!ch_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ret = gc4023_ioctl(sd, cmd, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) ret = copy_to_user(up, ch_info, sizeof(*ch_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) kfree(ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static int __gc4023_start_stream(struct gc4023 *gc4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ret = gc4023_write_array(gc4023->client, gc4023->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ret = __v4l2_ctrl_handler_setup(&gc4023->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (gc4023->has_init_exp && gc4023->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret = gc4023_ioctl(&gc4023->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) &gc4023->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dev_err(&gc4023->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ret |= gc4023_write_reg(gc4023->client, GC4023_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) GC4023_REG_VALUE_08BIT, GC4023_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static int __gc4023_stop_stream(struct gc4023 *gc4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) gc4023->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return gc4023_write_reg(gc4023->client, GC4023_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) GC4023_REG_VALUE_08BIT, GC4023_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static int gc4023_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct i2c_client *client = gc4023->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) mutex_lock(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (on == gc4023->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ret = __gc4023_start_stream(gc4023);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) __gc4023_stop_stream(gc4023);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) gc4023->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) mutex_unlock(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static int gc4023_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct i2c_client *client = gc4023->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) mutex_lock(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (gc4023->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ret = gc4023_write_array(gc4023->client, gc4023_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) gc4023->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) gc4023->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) mutex_unlock(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static inline u32 gc4023_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return DIV_ROUND_UP(cycles, GC4023_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static int __gc4023_power_on(struct gc4023 *gc4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct device *dev = &gc4023->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (!IS_ERR_OR_NULL(gc4023->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ret = pinctrl_select_state(gc4023->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) gc4023->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ret = clk_set_rate(gc4023->xvclk, GC4023_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (clk_get_rate(gc4023->xvclk) != GC4023_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ret = clk_prepare_enable(gc4023->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (!IS_ERR(gc4023->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) gpiod_set_value_cansleep(gc4023->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (!IS_ERR(gc4023->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) gpiod_set_value_cansleep(gc4023->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ret = regulator_bulk_enable(GC4023_NUM_SUPPLIES, gc4023->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (!IS_ERR(gc4023->pwren_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) gpiod_set_value_cansleep(gc4023->pwren_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (!IS_ERR(gc4023->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) gpiod_set_value_cansleep(gc4023->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (!IS_ERR(gc4023->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) gpiod_set_value_cansleep(gc4023->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) delay_us = gc4023_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) clk_disable_unprepare(gc4023->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static void __gc4023_power_off(struct gc4023 *gc4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct device *dev = &gc4023->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (!IS_ERR(gc4023->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) gpiod_set_value_cansleep(gc4023->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) clk_disable_unprepare(gc4023->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (!IS_ERR(gc4023->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) gpiod_set_value_cansleep(gc4023->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (!IS_ERR_OR_NULL(gc4023->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ret = pinctrl_select_state(gc4023->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) gc4023->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) regulator_bulk_disable(GC4023_NUM_SUPPLIES, gc4023->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (!IS_ERR(gc4023->pwren_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) gpiod_set_value_cansleep(gc4023->pwren_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static int gc4023_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return __gc4023_power_on(gc4023);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static int gc4023_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) __gc4023_power_off(gc4023);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static int gc4023_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) const struct gc4023_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) mutex_lock(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) mutex_unlock(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static int gc4023_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (fie->index >= gc4023->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define DST_WIDTH 2560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define DST_HEIGHT 1440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * The resolution of the driver configuration needs to be exactly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * the same as the current output resolution of the sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * the input width of the isp needs to be 16 aligned,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * the input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * Can be cropped to standard resolution by this function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * otherwise it will crop out strange resolution according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * to the alignment rules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static int gc4023_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) sel->r.left = CROP_START(gc4023->cur_mode->width, DST_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) sel->r.width = DST_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) sel->r.top = CROP_START(gc4023->cur_mode->height, DST_HEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) sel->r.height = DST_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static const struct dev_pm_ops gc4023_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) SET_RUNTIME_PM_OPS(gc4023_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) gc4023_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static const struct v4l2_subdev_internal_ops gc4023_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .open = gc4023_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static const struct v4l2_subdev_core_ops gc4023_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .s_power = gc4023_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .ioctl = gc4023_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .compat_ioctl32 = gc4023_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) static const struct v4l2_subdev_video_ops gc4023_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .s_stream = gc4023_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .g_frame_interval = gc4023_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static const struct v4l2_subdev_pad_ops gc4023_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .enum_mbus_code = gc4023_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .enum_frame_size = gc4023_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .enum_frame_interval = gc4023_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .get_fmt = gc4023_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .set_fmt = gc4023_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .get_selection = gc4023_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .get_mbus_config = gc4023_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static const struct v4l2_subdev_ops gc4023_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .core = &gc4023_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .video = &gc4023_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .pad = &gc4023_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static int gc4023_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct gc4023 *gc4023 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct gc4023, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct i2c_client *client = gc4023->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) int mirror = 0, flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) int otp_mirror = 0, otp_flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /*Propagate change of current control to all related controls*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /*Update max exposure while meeting expected vblanking*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) max = gc4023->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) __v4l2_ctrl_modify_range(gc4023->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) gc4023->exposure->minimum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) gc4023->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) gc4023->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ret = gc4023_write_reg(gc4023->client, GC4023_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) GC4023_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ctrl->val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ret |= gc4023_write_reg(gc4023->client, GC4023_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) GC4023_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ctrl->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ret = gc4023_set_gain_reg(gc4023, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) gc4023->cur_vts = ctrl->val + gc4023->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ret = gc4023_write_reg(gc4023->client, GC4023_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) GC4023_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) gc4023->cur_vts >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ret |= gc4023_write_reg(gc4023->client, GC4023_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) GC4023_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) gc4023->cur_vts & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) ret = gc4023_enable_test_pattern(gc4023, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ret = gc4023_read_reg(gc4023->client, GC4023_MIRROR_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) GC4023_REG_VALUE_08BIT, &mirror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) ret |= gc4023_read_reg(gc4023->client, GC4023_OTP_MIRROR_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) GC4023_REG_VALUE_08BIT, &otp_mirror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (ctrl->val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) mirror |= GC4023_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) otp_mirror |= GC4023_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) mirror &= ~GC4023_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) otp_mirror &= ~GC4023_MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ret |= gc4023_set_mirror_flip(gc4023, mirror, otp_mirror);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ret = gc4023_read_reg(gc4023->client, GC4023_MIRROR_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) GC4023_REG_VALUE_08BIT, &flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) ret |= gc4023_read_reg(gc4023->client, GC4023_OTP_MIRROR_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) GC4023_REG_VALUE_08BIT, &otp_flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (ctrl->val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) flip |= GC4023_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) otp_flip |= GC4023_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) flip &= ~GC4023_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) otp_flip &= ~GC4023_FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ret |= gc4023_set_mirror_flip(gc4023, flip, otp_flip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static const struct v4l2_ctrl_ops gc4023_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .s_ctrl = gc4023_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static int gc4023_initialize_controls(struct gc4023 *gc4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) const struct gc4023_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) handler = &gc4023->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) mode = gc4023->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) handler->lock = &gc4023->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) gc4023->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) 1, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) gc4023->cur_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) gc4023->cur_pixel_rate = GC4023_PIXEL_RATE_LINEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) __v4l2_ctrl_s_ctrl(gc4023->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) gc4023->cur_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) gc4023->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) 0, GC4023_PIXEL_RATE_LINEAR, 1, GC4023_PIXEL_RATE_LINEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) gc4023->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (gc4023->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) gc4023->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) gc4023->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) gc4023->vblank = v4l2_ctrl_new_std(handler, &gc4023_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) GC4023_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) gc4023->exposure = v4l2_ctrl_new_std(handler, &gc4023_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) V4L2_CID_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) GC4023_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) exposure_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) GC4023_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) gc4023->anal_gain = v4l2_ctrl_new_std(handler, &gc4023_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) V4L2_CID_ANALOGUE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) GC4023_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) GC4023_GAIN_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) GC4023_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) GC4023_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) gc4023->test_pattern =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) &gc4023_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ARRAY_SIZE(gc4023_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) 0, 0, gc4023_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) gc4023->h_flip = v4l2_ctrl_new_std(handler, &gc4023_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) gc4023->v_flip = v4l2_ctrl_new_std(handler, &gc4023_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) dev_err(&gc4023->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) gc4023->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) gc4023->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static int gc4023_check_sensor_id(struct gc4023 *gc4023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) struct device *dev = &gc4023->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) u16 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) u32 reg_H = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) u32 reg_L = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) ret = gc4023_read_reg(client, GC4023_REG_CHIP_ID_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) GC4023_REG_VALUE_08BIT, ®_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) ret |= gc4023_read_reg(client, GC4023_REG_CHIP_ID_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) GC4023_REG_VALUE_08BIT, ®_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (!(reg_H == (CHIP_ID >> 8) || reg_L == (CHIP_ID & 0xff))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) dev_info(dev, "detected gc%04x sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static int gc4023_configure_regulators(struct gc4023 *gc4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) for (i = 0; i < GC4023_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) gc4023->supplies[i].supply = gc4023_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return devm_regulator_bulk_get(&gc4023->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) GC4023_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) gc4023->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static int gc4023_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) struct gc4023 *gc4023;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) gc4023 = devm_kzalloc(dev, sizeof(*gc4023), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (!gc4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) &gc4023->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) &gc4023->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) &gc4023->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) &gc4023->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) gc4023->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) gc4023->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) for (i = 0; i < gc4023->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) gc4023->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (i == gc4023->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) gc4023->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) gc4023->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (IS_ERR(gc4023->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) gc4023->pwren_gpio = devm_gpiod_get(dev, "pwren", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (IS_ERR(gc4023->pwren_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) dev_warn(dev, "Failed to get pwren-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) gc4023->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (IS_ERR(gc4023->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) gc4023->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (IS_ERR(gc4023->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) gc4023->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (!IS_ERR(gc4023->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) gc4023->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) pinctrl_lookup_state(gc4023->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (IS_ERR(gc4023->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) gc4023->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) pinctrl_lookup_state(gc4023->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (IS_ERR(gc4023->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) ret = gc4023_configure_regulators(gc4023);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) mutex_init(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) sd = &gc4023->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) v4l2_i2c_subdev_init(sd, client, &gc4023_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) ret = gc4023_initialize_controls(gc4023);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) ret = __gc4023_power_on(gc4023);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) usleep_range(3000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) ret = gc4023_check_sensor_id(gc4023, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) sd->internal_ops = &gc4023_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) gc4023->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) ret = media_entity_pads_init(&sd->entity, 1, &gc4023->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (strcmp(gc4023->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) gc4023->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) GC4023_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) __gc4023_power_off(gc4023);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) v4l2_ctrl_handler_free(&gc4023->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) mutex_destroy(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) static int gc4023_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) struct gc4023 *gc4023 = to_gc4023(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) v4l2_ctrl_handler_free(&gc4023->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) mutex_destroy(&gc4023->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) __gc4023_power_off(gc4023);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static const struct of_device_id gc4023_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) { .compatible = "galaxycore,gc4023" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) MODULE_DEVICE_TABLE(of, gc4023_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static const struct i2c_device_id gc4023_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) { "galaxycore,gc4023", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static struct i2c_driver gc4023_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .name = GC4023_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .pm = &gc4023_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .of_match_table = of_match_ptr(gc4023_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .probe = &gc4023_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .remove = &gc4023_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .id_table = gc4023_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) return i2c_add_driver(&gc4023_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) i2c_del_driver(&gc4023_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) MODULE_DESCRIPTION("galaxycore gc4023 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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